DS75U MAXIM | Alldatasheet
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Technical content
FEATURES
Temperature Measurements Require No External Components Measures Temperatures from -55°C to ±2°C Accuracy Over a -25°C to +100°C Range Thermometer Resolution is User- Configurable from Nine (Default) to 12 Bits (0.5°C to 0.0625°C Resolution) 9-Bit Conversion Time is 150ms (Max) Thermostatic Settings are User-Definable Data is Read/Written Via 2-Wire Serial (Interface (SDA and SCL Pins) Multidrop Capability Simplifies Distributed Temperature-Sensing Applications Wide Power-Supply Range (+2.7V to +5.5V). Pin/software Compatible with the LM75 Available in 8-Pin μMAX® and SO Packages. See Table 1 for Ordering Information Applications Include Personal Computers, Cellular Base Stations, Office Equipment, or Any Thermally Sensitive System PIN ASSIGNMENT PIN DESCRIPTION SDA – Open-Drain Data I/O SCL – Clock Input GND – Ground O.S. – Open-Drain Thermostat Output A 0 – Address Input A1 – Address Input A2 – Address Input V DD – Power Supply
DESCRIPTION
The DS75 digital thermometer and th ermostat provides 9, 10, 11, or 12 -bit digital temperature readings over a -55°C to +125°C range with ±2°C accuracy over a -25°C to +100°C range. At power-up, the DS75 defaults to 9-bit resolution for software compatibility with the LM75. Communi cation with the DS75 is achieved via a simple 2–wire serial interface. Three address pins allow up to eight DS75 devices to operate on the same 2–wire bus, which greatly simplifies distributed temperature sensing applications. The DS75 thermostat has a dedicated open–drain output (O.S.) and programmable fault tolerance, which allows the user to define the num ber of consecutive error conditions that must occur before O.S is activated. There are two thermostatic operating m odes that control thermost at operation based on user- defined trip-points (TOS and THYST). A block diagram of the DS75 is shown in Figure 1 and detailed pin descriptions are given in Table 2. DS75 Digital Thermometer and Thermostat www.maxim-ic.com DS75U+ (μMAX) SCL VDD A2 GND O.S. SDA DS75 DS75S+ (8-Pin SO — 150mil) SCL VDD A2 GND O.S. SDA DS75 µMAX is a registered trademark of Maxim Integrated Products, Inc.
Table 1. ORDERING INFORMATION Table 2. DETAILED PIN DESCRIPTION 1 SDA Data input/output pin for 2-wire serial communication port. Open drain. 2 SCL Clock input pin for 2-wire serial communication port. 3 O.S. Thermostat output. Open drain. 8 V DD Supply Voltage. +2.7V to +5.5V supply pin.
Figure 1. DS75 FUNCTIONAL BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS* Voltage on VDD, Relative to Ground –0.3V to +7.0V Voltage on any other pin, Relative to Ground –0.3V to (V DD + 0.3V) Operating Temperature –55 °C to +125°C Storage Temperature –55 °C to +125°C Soldering Temperature +260 °C for 10 seconds * These are stress ratings only and f unctional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (-55°C to +125°C; 2.7V ≤ VDD ≤ 5.5V) PARAMETER SYMBOL CONDITION MIN MAX UNITS NOTES Supply Voltage V DD 2.7 5.5 V -25 to +100 ± 2.0 Thermometer Error T ERR -55 to +125 ± 3.0 °C 2 Input Logic High V IH 0.7V DD V DD+0.5 V 1 Input Logic Low V IL -0.5 0.3V DD V 1 VOL1 3 mA sink current 0 0.4 SDA Output Logic Low Voltage VOL2 6 mA sink current 0 0.6 V 1 O.S. Saturation Voltage V OL 4 mA sink current 0.8 V 1, 2 Input current each I/O pin 0.4 < VI/O<
0.9 VDD -10 +10 μA
I/O Capacitance C I/O 10 pF Standby Current I DD1 1 µA 3, 4 Active Temp. Conversions 1000 Active Current I DD Communica- tion only 100 µA 3, 4
AC ELECTRICAL CHARACTERISTICS (-55°C to +125°C; 2.7V ≤ VDD ≤ 5.5V) PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES Resolution 9 12 bits 9-bit conversions 150 10-bit conversions 300 11-bit conversions 600 Temperature Conversion Time tCONVT 12-bit conversions 1200 ms SCL Frequency f SCL 400 KHz Bus Free Time Between a STOP and START Condition t BUF 1.3 μs 5 START and Repeated START Hold Time from Falling SCL t HD:STA 0.6 μs 5, 6 Low Period of SCL t LOW 1.3 μs 5 High Period of SCL t HIGH 0.6 μs 5 Repeated START Condition Setup Time to Rising SCL t SU:STA 0.6 μs 5 Data-Out Hold Time from Falling SCL tHD:DAT 0 0.9 μs 5 Data-In Setup Time to Rising SCL tSU:DAT 100 ns 5 Rise Time of SDA and SCL tR 20 + 0.1C B 1000 ns 5, 7 Fall Time of SDA and SCL tF 20 + 0.1CB 300 ns 5, 7 STOP Setup Time to Rising SCL tSU:STO 0.6 μs 5 Capacitive Load for Each Bus Line CB 400 pF Input Capacitance C I 5 pF NOTES: 1. All voltages are referenced to ground. 2. Internal heating caused by O.S. loading will cause the DS75 to read approximately 0.5 °C higher if O.S. is sinking the max rated current. 3. I DD specified with O.S. pin open. 4. I DD specified with VDD at 5.0V and SDA, SCL = 5.0V, 0°C to 70°C. 6. After this period, the first clock pulse is generated. 7. For example, if CB = 300pF, then tR[min] = tF[min] = 50ns.
Figure 2. TIMING DIAGRAM Note: The DS75 does not delay the SDA line internally with respect to SCL for any length of time. used. The DS75 is factory-calibrated and requires no external components to measure temperature. conversion time doubles for each additional bit of resolution. does not affect the operation in progress. gives examples of 12-bit resolution digital output data and the corresponding temperatures.
Figure 3. TEMPERATURE, TH, and TL REGISTER FORMAT Table 3. 12-BIT RESOLUTION TEMPERATURE/DATA RELATIONSHIP shutdown mode, and writing a 0 to the SD bit returns the DS75 to normal operation. up, so standalone operation is not possible. power-up the fault tolerance is 1.
comparison is equal to the conversion resolution set by the R1 and R0 bits in th e configuration register. power-up default is active low. HYST. Putting the device into shutdown mode doe s not clear O.S. in comparator mode. Thermostat comparator mode operation with FT = 2 is illustrated in Figure 4. cyclical between T OS and T HYST events (i.e, T OS, clear, T HYST, clear, T OS, clear, T HYST, clear, etc.). Thermostat interrupt mode operation with FT = 2 is illustrated in Figure 4. Figure 4. O.S. OUTPUT OPERATION EXAMPLE
Figure 5. CONFIGURATION REGISTER
0 R1 R0 F1 F0 POL TM SD
Table 4. CONFIGURATION REGISTER BIT DESCRIPTIONS The master can write to this bit, but it will always read out as a 0. Sets the thermostat fault tolerance (see Table 6). Sets the thermostat fault tolerance (see Table 6). POL = 0 — O.S. is active low. POL = 1 — O.S. is active high. SD = 0 — Active conversion and thermostat operation. Table 5. RESOLUTION CONFIGURATION
Table 6. Fault Tolerance Configuration The four DS75 registers each have a unique two-bit po inter designation, which is defined in Table 7. same register is being written to twice in a row. immediately without resetting the pointer. Table 7. POINTER DEFINITION and open-drain SDA I/O pin. All communication is MSb first. device generates the SCL signal and START and STOP conditions. Slave: All devices on the bus other than the master. The DS75 always functions as a slave. high by a pullup resistor (if the SCL output is open-drain). Transmitter: A device (master or slave) that is sending data on the bus. Receiver: A device (master or slave) that is receiving data from the bus.
GENERAL 2-WIRE INFORMATION All data is transmitted MSb first over the 2-wire bus. One bit of data is transmitted on the 2-wire bus each SCL period. A pullup resistor is required on the SDA line and, when the bus is idle, both SDA and SCL must remain in a logic-high state. All bus communication must be initiated with a START condition and terminated with a STOP condition. During a START or STOP is the only time SD A is allowed to change states while SCL is high. At all other times, changes on the SDA line can only occur when SCL is low: SDA must remain stable when SCL is high. After every 8-bit (1-byte) transf er, the receiving device must answ er with an ACK (or NACK), which takes one SCL period. Therefore, nine clocks are required for every one-byte data transfer. Writing to the DS75 — To write to the DS75, the master must generate a START followed by an address byte containing the DS75 bu s address. The value of the R/ W bit must be a 0, which indicates that a write is about to take place. The DS75 will respond with an ACK after receiving the address byte. This must be followed by a pointer byte from the master, which tells the DS75 which register is being written to. The DS75 will again respond with an ACK after re ceiving the pointer byte. Following this ACK the master device must immediately begin transmitting data to the DS75. When writing to the configuration register, the master must send one byte of data (see Figure 9a ), and when writing to the T OS or T HYST registers the master must send two bytes of data (see Figure 9b). After receiving each data byte, the DS75 will respond with an ACK, and the transaction is finished with a STOP from the master. Reading from the DS75— When reading from the DS75, if the pointer was already pointed to the desired register during a previous transaction, the read can be perfor med immediately without changing the pointer setting. In this cas e the master sends a START followe d by an address byte containing the DS75 bus address. The R/W bit must be a 1, which te lls the DS75 that a read is being performed. After the DS75 sends an ACK in response to the address byte, the DS75 will begin transmitting the requested data on the next clock cycle. When reading from the configuration register, the DS75 will transmit one byte of data, after which the master must respond with a NACK followed by a STOP (see Figure 9c). For two-byte reads (i.e., from the Temperature, T OS or T HYST register), the DS75 will transmit two bytes of data, and the master must respond to the first data byte with an ACK and to the second byte with a NACK followed by a STOP (see Figure 9d). If only the most significant byte of data is needed, the master can issue a NACK followed by a STOP after reading the first data byte in which case the transaction will be the same as for a read from the configuration register. If the pointer is not already pointing to the desired re gister, the pointer must fi rst be updated as shown in Figure 9e, which shows a pointer update followe d by a single-byte read. The value of the R/ W bit in the initial address byte is a 0 (“write”) since the master is going to write a pointer byte to the DS75. After the DS75 to the address byte with an ACK, the master sends a pointer byte that corresponds to the desired register. The master must then perform a repeated start followed by a standa rd one or two byte read sequence (with R/W =1) as described in the previous paragraph.
Figure 9. 2-WIRE INTERFACE TIMING
REVISION HISTORY
022108 Deleted all references to flip-chip package. Added registered trademark symbol to µMAX. 1, 2