DS64MB201_13 TI1 | Alldatasheet

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www.ti.com SNLS307E – JANUARY 2011– REVISED JULY 2013 DS64MB201DualLane2:1/1:2Mux/BufferwithEqualizationand De-Emphasis Check for Samples: DS64MB201 1FEATURES DESCRIPTION The DS64MB201 is a dual lane 2:1 multiplexer and 2• Up to 6.4 Gbps dual lane 2:1 mux, 1:2 switch 1:2 switch or fan-out buffer with signal conditioningor fan-out suitable for SATA/SAS and other high-speed bus• Adjustable receive equalization up to +33 dB applications up to 6.4 Gbps. The device performs gain both receive equalization and transmit de-emphasis, allowing maximum flexibility of physical placement• Adjustable transmit de-emphasis up to −12 dB within a system. The receiver's continuous time linear• Adjustable transmit VOD equalizer (CTLE) provides a boost of up to +33 dB at• <0.25 UI of residual DJ at 6.4 Gbps with 40” 3 GHz and is capable of opening an input eye that is FR4 trace completely closed due to inter-symbol interference (ISI) induced by the interconnect medium. The• SATA/SAS: OOB signal pass-through transmitter features a programmable output de-• Adjustable electrical IDLE detect threshold emphasis driver and allows amplitude voltage levels• Low power to be selected from 600 mVp-p to 1200 mVp-p to suit

  • Signal conditioning programmable via pin multiple application scenarios. The signal conditioning settings are programmable via control pin settings orselection or SMBus interface SMBus interface.• Single 2.5V supply operation To enable seamless upgrade from SAS/SATA 3.0• >6 kV HBM ESD Rating Gbps to 6.0 Gbps data rates without compromising• 3.3V tolerant SMBus interface physical reach, DS64MB201 automatically detects
  • High speed signal flow–thru pinout package: the incoming data rate and selects the optimal de- 54-pin WQFN (10 mm x 5.5 mm) emphasis pulse width. The device detects the out-of- band (OOB) idle and active signals of the SAS/SATA specification and passes through with minimum signalAPPLICATIONS distortion.• SAS and SATA (1.5, 3.0 and 6 Gbps)
  • XAUI (3.125 Gbps), RXAUI (6.25 Gbps)
  • sRIO – Serial Rapid I/O
  • Fibre Channel (4.25 Gbps)
  • 10GBase-CX4, InfiniBand (SDR & DDR)
  • FR-4 backplane traces Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2011–2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Cs > 10 nF Cs > 10 nF DIN1+- DIN0+- SIB0+- SIA0+- SIB1+- SIA1+- SOB1+- SOA1+- SOB0+- SOA0+- DS64MB201 SNLS307E – JANUARY 2011– REVISED JULY 2013 www.ti.com Typical Application Figure 1.

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multiple (minimum of 4) vias to ensure optimal electrical and thermal performance. Figure 2. DS64MB201 Pin Diagram 54L WQFN

Table 1. Pin Descriptions SOA1+, SOA1- 31, 30 emphasis. Fully compatible with AC coupled CML inputs. SOB1+, SOB1- 29, 28 emphasis. Fully compatible with AC coupled CML inputs. DOUT1+, DOUT1- 7, 8 emphasis. Fully compatible with AC coupled CML inputs. ENSMB 48 I, LVCMOS w/ System Management Bus (SMBus) enable pin. used to program VOD, rate, idle detection, equalization and de-emphasis settings. EQA, 46, I, Float, EQA/B/D, 3–level input controls the level of equalization. EQB, 49, LVCMOS EQA controls the level of equalization of the SIA0 and SIA1 inputs. EQD 53 EQB controls the level of equalization of the SIB0 and SIB1 inputs. EQD controls the level of equalization of the DIN0 and DIN1 inputs. The pins are active only when ENSMB is de-asserted (Low). DEMA, 47, I, Float, DEMA/B/D, 3–level input controls the level of de-emphasis. DEMB, 50, LVCMOS DEMA controls the level of de-emphasis of the SOA0 and SOA1 outputs. DEMD 54 DEMB controls the level of de-emphasis of the SOB0 and SOB1 outputs. DEMD controls the level of de-emphasis of the DOUT0 and DOUT1 outputs. The pins are active only when ENSMB is de-asserted (Low). RATE 21 I, Float, RATE, 3–level input controls the pulse width of de-emphasis of the output. LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.

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Table 1. Pin Descriptions (continued) TXIDLEDO 24 I, Float, TXIDLEDO, 3–level input controls the driver output. LVCMOS TXIDLEDO = 0 disables the signal detect/squelch function for DOUT. TXIDLEDO = 1 forces the DOUT to be muted (electrical idle). TXIDLESO 25 I, Float, TXIDLESO, 3–level input controls the driver output. LVCMOS TXIDLESO = 0 disables the signal detect/squelch function for SOUT. TXIDLESO = 1 forces the SOUT to be muted (electrical idle). FANOUT 26 I, LVCMOS w/ FANOUT = 1 enables both A/B outputs for broadcast mode. internal pull- SEL0, SEL1 = 0 selects B input and B output. VOD0, VOD1 22, 23 I, LVCMOS w/ VOD[1:0] adjusts the output differential amplitude voltage level on all outputs. Note: VOD should be set to a minimum of 1000 mV to achieve stated DE levels. VDD 9, 14, 36, 41, Power 2.5V Power supply pins. lower the ground impedance and improve the thermal performance of the package. during storage or handling to prevent electrostatic damage to the MOS gates.

SNLS307E – JANUARY 2011– REVISED JULY 2013 www.ti.com Absolute Maximum Ratings (1)(2) Supply Voltage (VDD) -0.5V to +3.0V LVCMOS Input/Output Voltage -0.5V to +4.0V Differential Input Voltage -0.5V to (VDD+0.5V) Differential Output Voltage -0.5V to (VDD+0.5V) Analog (SD_TH) -0.5V to (VDD+0.5V) Junction Temperature +125°C Storage Temperature -40°C to +125°C Maximum Package Power Dissipation at NJY Package 4.21 W 25°C Derate NJY Package 52.6mW/°C above +25°C ESD Rating HBM, STD - JESD22-A114C ≥6 kV MM, STD - JESD22-A115-A ≥250 V CDM, STD - JESD22-C101-C ≥1250 V Thermal Resistance θJC 11.5°C/W θJA, No Airflow, 4 layer JEDEC 19.1°C/W For soldering specifications: See product folder at http://www.ti.com/lit/SNOA549 (1) “Absolute Maximum Ratings”indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications. Recommended Operating Conditions Min Typ Max Units Supply Voltage VDD to GND 2.375 2.5 2.625 V Ambient Temperature(1) -40 25 +85 °C SMBus (SDA, SCL) 0 3.6 V CML Differential Input Voltage 0 2.0 Vp-p Supply Noise Tolerance up to 50 MHz(2) 100 mVP-P (1) OOB signal pass-through limited to a minimum ambient temperature of -10C (2) Allowed supply noise (mVP-P sine wave) under typical conditions.

Electrical Characteristics

Over recommended operating supply and temperature ranges with default register settings unless other specified.(1) Symbol Parameter Conditions Min Typ Max Units POWER PD Power Dissipation EQx = 0, DEMx = 0 dB, 2.5V Operation K28.5 pattern, 850 950 mW VOD = 1.0 V p-p Channel powerdown(2) 11 mW LVCMOS / LVTTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 3.6 V VIL Low Level Input Voltage 0 0.8 V IIH Input High Current VIN = 3.3V -15 +15 μA (1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. (2) Measured with ENSMB = 1, all channels disabled using SMBus registers 0x01 and 0x02, and EQ in bypass (Default)

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www.ti.com SNLS307E – JANUARY 2011– REVISED JULY 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges with default register settings unless other specified.(1) Symbol Parameter Conditions Min Typ Max Units IIL Input Low Current VIN = 0V -15 +15 μA CML RECEIVER INPUTS (IN_n+, IN_n-) RLRX-DIFF Rx Differential Return Loss 150 MHz – 1.5 GHz -20 (SDD11) (3) 150 MHz – 3.0 GHz -13.5 dB 150 MHz – 6.0 GHz -8 RLRX-CM Rx Common Mode Input Return 150 MHz – 3.0 GHz -10 dBLoss (SCC11) See(3) RRX-IB Rx Impedance Balance (SDC11) 150 MHz – 3.0 GHz -27 dBSee(3) IIN Maximum current allowed at IN+ or −30 +30 mAIN- input pin. RIN Input Resistance Single ended to VDD 50 ΩSee (3) RITD Input Differential Impedance See (3) between 85 100 115 Ω IN+ and IN- RITIB Input Differential Impedance See (3) 5 ΩImbalance RICM Input Common Mode Impedance See (4) 20 25 40 Ω VRX-DIFF Differential Rx peak to peak DC voltage, 0.1 1.2 Vvoltage SD_TH = 20 kΩ to GND VRX-SD_TH Electrical Idle detect threshold SD_TH = Float 40 175 mVp-p(differential) See(5) and Figure 7 DIFFERENTIAL OUTPUTS (OUT_n+, OUT_n-) VOD Output Differential Voltage Swing RL = 50 Ω ±1% to GND (AC coupled with 10 with de-emphasis disabled nF), 6.4 Gbps DEMA = DEMB = 0 dB, 500 600 700 mVP-P VOD1–0 = 00 See (6) VOD1–0 = 11 1100 1265 1450 mVP-P VOCM Output Common-Mode Voltage Single-ended measurement DC-Coupled with VDD –50Ω termination V1.4See (4) TTX-RF Transmitter Rise/ Fall Time 20% to 80% of differential output voltage, measured within 1”from output pins 65 85 ps See (4), (6), and Figure 3 TRF-DELTA Tx rise/fall mismatch 20% to 80% of differential output voltage 0.1 UISee (4) and (6) RLTX-DIFF Tx Differential Return Loss Repeating 1100b (D24.3) pattern, (SDD22) VOD = 1.0 Vp-p, -11 See (4) 150 MHz – 1.5 GHz dB 1.5 GHz – 3.0 GHz -10 3 GHz – 6.0 GHz -5 RLTX-CM Tx Common Mode Return Loss Repeating 1100b (D24.3) pattern, (SCC22) VOD = 1.0 Vp-p, -10 dB50 MHz – 3.0 GHz See (4) (3) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (4) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (5) Measured at package pins of receiver. Less than 65 mVp-p is IDLE, greater than 175 mVp-p is ACTIVE. SD_TH pin connected with resistor to GND overrides this default setting. (6) Measured with clock-like {11111 00000} pattern. Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DS64MB201

SNLS307E – JANUARY 2011– REVISED JULY 2013 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges with default register settings unless other specified.(1) Symbol Parameter Conditions Min Typ Max Units RTX-IB Tx Impedance Balance Repeating 1100b (D24.3) pattern, (SDC22) VOD = 1.0 Vp-p, -30 dB50 MHz – 3.0 GHz See (4) ITX-SHORT Tx Output Short Circuit Current 90 mALimit ROTD Output Differential Impedance See (4) 85 100 125 Ωbetween OUT+ and OUT- ROTIB Output Differential Impedance See (4) 5 ΩImbalance ROCM Output Common Mode Impedance See (4) 20 25 35 Ω VTX-CM-DELTA Common Mode Voltage Delta Minimum Temperature for OOB signal pass- between active burst and electrical through is -10C. ±40 mVIdle of an OOB signal VIN = 800 mVp-p, at 3 Gbps, See (7) TDI Max time to transition to valid Minimum Temperature for OOB signal pass- electrical idle after leaving active through is -10C. 6.5 9.5 nsburst in OOB signaling VIN = 800 mVp-p, at 3 Gbps, See Figure 5 TID Max time to transition to valid Minimum Temperature for OOB signal pass- active burst after leaving idle in through is -10C. 5.5 8.0 nsOOB signaling VIN = 800 mVp-p, at 3 Gbps, See Figure 5 TPD Differential Propagation Delay (Low Propagation delay measure at midpoint to High and High to Low Edge crossing between input to outputEQx[1:0] = 150 200 250 ps11, DEMx[1:0] = — 6 dB See Figure 4 EQz[1:0] = OFF, DEMx[1:0] = 0 dB 120 170 220 ps TLSK Lane to Lane Skew in a Single Part VDD = 2.5V, TA = 25C 27 ps TPPSK Part to Part Propagation Delay VDD = 2.5V, TA = 25C 35 psSkew TSM Switch/Mux Time Time to switch/mux between A and B 150 nsinput/output signals EQUALIZATION DJ1 Residual Deterministic Jitter at 6.4 Tx Launch Amplitude = 0.8 to Gbps 1.2 Vp–p, 40”4–mil FR4 trace, ENSMB = 1, EQ setting = 0x3B, DEMx[1:0] = 0.12 0.25 UIP-P 0dB, VOD = 1.0 Vp-p, K28.5, SD_TH = float See (8) DJ2 Residual Deterministic Jitter at 3.2 Tx Launch Amplitude = 0.8 to Gbps 1.2 Vp–p, 40”4–mil FR4 trace, EQ setting = 0x3C, DEMx[1:0] = 0dB, VOD = 0.05 0.125 UIP-P 1.0 Vp-p, K28.5, SD_TH = float See (8) RJ Random Jitter Tx Launch Amplitude = 0.8 to 0.5 psrms1.2 Vp–p, Repeating 1100b (D24.3) pattern DE-EMPHASIS DJ3 Residual Deterministic Jitter at 6.4 Tx Launch Amplitude = 0.8 to Gbps 1.2 Vp–p, 10”4–mil FR4 trace, EQx = off, DEMx = −6 dB, 0.09 0.20 UIP-P VOD = 1.0 Vp-p, K28.5, RATE = 1 See (8) (7) Common-mode voltage (VCM) is expressed mathematically as the average of the two signal voltages with respect to local ground.VCM = (A + B) / 2, A = OUT+, B = OUT-. (8) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization and are not ensured.

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www.ti.com SNLS307E – JANUARY 2011– REVISED JULY 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges with default register settings unless other specified.(1) Symbol Parameter Conditions Min Typ Max Units DJ4 Residual Deterministic Jitter at 3.2 Tx Launch Amplitude = 0.8 to Gbps 1.2 Vp–p, 20”4–mil FR4 trace, EQx = off, DEMx = −6 dB, 0.07 0.18 UIP-P VOD = 1.0 Vp-p, K28.5, RATE = 0 See (8) Electrical Characteristics — Serial Management Bus Interface Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ Max Units SERIAL BUS INTERFACE DC SPECIFICATIONS VIL Data, Clock Input Low Voltage 0.8 V VIH Data, Clock Input High Voltage 2.1 3.6 V IPULLUP Current Through Pull-Up Resistor High Power Specification 4 mAor Current Source VDD Nominal Bus Voltage 2.375 3.6 V ILEAK-Bus Input Leakage Per Bus Segment See (1) -200 +200 µA ILEAK-Pin Input Leakage Per Device Pin -15 µA CI Capacitance for SDA and SDC See (1) and (2) 10 pF RTERM External Termination Resistance VDD3.3, 2000 Ωpull to VDD = 2.5V ± 5% OR 3.3V ± See (1), (2), and (3) SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure 6 FSMB Bus Operating Frequency See (4) 10 100 kHz TBUF Bus Free Time Between Stop and 4.7 µsStart Condition THD:STA Hold time after (Repeated) Start At IPULLUP, Max Condition. After this period, the first 4.0 µs clock is generated. TSU:STA Repeated Start Condition Setup 4.7 µsTime TSU:STO Stop Condition Setup Time 4.0 µs THD:DAT Data Hold Time 300 ns TSU:DAT Data Setup Time 250 ns TTIMEOUT Detect Clock Low Timeout See (4) 25 35 ms TLOW Clock Low Period 4.7 µs THIGH Clock High Period See (4) 4.0 50 µs TLOW:SEXT Cumulative Clock Low Extend Time See (4) 2 ms(Slave Device) tF Clock/Data Fall Time See (4) 300 ns tR Clock/Data Rise Time See (4) 1000 ns tPOR Time in which a device must be See (4) 500 msoperational after power-on reset (1) Recommended value. Parameter not tested in production. (2) Recommended maximum capacitance load per bus segment is 400pF. (3) Maximum termination voltage should be identical to the device supply voltage. SMBus common AC specifications for details. Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DS64MB201

Figure 3. LPDS Output Transition Times Figure 4. Propagation Delay Timing Diagram Figure 5. Idle Timing Diagram Figure 6. SMBus Timing Parameters

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Control Mode (ENSMB = 0) and SMBus Mode (ENSMB = 1). electrical idle detect threshold is also programmable via an optional external resistor on the SD_TH pin. registers are reset to their default state. Table 2. Equalization Input Select Pins for SIA, SIB and DIN (3–Level Input) (1) F = Float (No Connect), 1 = High and 0 = Low. Table 3. De-Emphasis Input Select Pins for SOA, SOB and DOUT (3–Level Input) emphasis. Please refer to VOD1 and VOD0 pin description to set the output differential voltage level.

Table 4. Idle Control (3–Level Input) on EQ settings. Idle state not ensured. 1 Manual override, output in electrical Idle. Differential inputs are ignored. Table 5. Receiver Electrical Idle Detect Threshold Adjust Figure 7. Typical Idle Threshold vs. SD_TH resistor value

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Table 6. Logic Table of Switch and Mux Control 0 0 0 DOUT0 connects to SIB0. DIN0 connects to SOB0. SOA0 is in idle (output muted). DIN1 connects to SOB1. SOA1 is in idle (output muted). 0 0 1 DOUT0 connects to SIB0. DIN0 connects to SOB0. SOA0 is in idle (output muted). DIN1 connects to SOA1. SOB1 is in idle (output muted). 0 1 0 DOUT0 connects to SIA0. DIN0 connects to SOA0. SOB0 is in idle (output muted). DIN1 connects to SOB1. SOA1 is in idle (output muted). 0 1 1 DOUT0 connects to SIA0. DIN0 connects to SOA0. SOB0 is in idle (output muted). DIN1 connects to SOA1. SOB1 is in idle (output muted). 1 0 0 DOUT0 connects to SIB0. DIN0 connects to SOB0 and SOA0. DIN1 connects to SOB1 and SOA1. 1 0 1 DOUT0 connects to SIB0. DIN0 connects to SOB0 and SOA0. DIN1 connects to SOA1 and SOB1. 1 1 0 DOUT0 connects to SIA0. DIN0 connects to SOA0 and SOB0. DIN1 connects to SOB1 and SOA1. 1 1 1 DOUT0 connects to SIA0. DIN0 connects to SOA0 and SOB0. DIN1 connects to SOA1 and SOB1.

pulled high to enable SMBus mode and allow access to the configuration registers. the AD[3:0] inputs. Below are some examples. During normal operation the data on SDA must be stable during the time when SDC is High. START: A High-to-Low transition on SDA while SDC is High indicates a message START condition. STOP: A Low-to-High transition on SDA while SDC is High indicates a message STOP condition. are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state. Only), default value and function information. (0x18, 0x26, 0x2E, 0x35, 0x3C, 0x43) requires one of the following De-emphasis settings when in SMBus mode. The VOD for each output should be set via register write or pin control to be a minimum of 1000 mV. Table 7. De-Emphasis Register Settings (must write one of the following when in SMBus mode) To write a register, the following protocol is used (see SMBus 2.0 specification).

  1. The Host drives a START condition, the 7-bit SMBus address, and a “0”indicating a WRITE.
  2. The Device (Slave) drives the ACK bit (“0”).
  3. The Host drives the 8-bit Register Address.
  4. The Device drives an ACK bit (“0”).
  5. The Host drive the 8-bit data byte.

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  1. The Device drives an ACK bit (“0”).
  2. The Host drives a STOP condition.

To read a register, the following protocol is used (see SMBus 2.0 specification).

  1. The Host drives a START condition, the 7-bit SMBus address, and a “0”indicating a WRITE.
  2. The Device (Slave) drives the ACK bit (“0”).
  3. The Host drives the 8-bit Register Address.
  4. The Device drives an ACK bit (“0”).
  5. The Host drives a START condition.
  6. The Host drives the 7-bit SMBus Address, and a “1”indicating a READ.
  7. The Device drives an ACK bit “0”.
  8. The Device drives the 8-bit data value (register contents).
  9. The Host drives a NACK bit “1”indicating end of the READ transfer.
  10. The Host drives a STOP condition.

Table 7, Table 8 for additional information and recommended settings.

  1. Reset the SMBus registers to default values:
  2. Set de-emphasis to -6 dB for all lanes:
  3. Set equalization to external pin level EQ[1:0] = 00 (~9 dB at 3 GHz) for all lanes:
  4. Set VOD = 1.0 Vp-p for all lanes:

Table 8. SMBus Register Map 0x00 Reset 7:1 Reserved R/W 0x00 Set bits to 0.

0 Reset SMBus Reset

Table 8. SMBus Register Map (continued) 0x02 PWDN Control 7:1 Reserved R/W 0x00 Set bits to 0.

0 PWDN Control 0: Normal operation

0x03 SEL / FANOUT 7:3 Reserved R/W 0x00 Set bits to 0.

1 SEL0 0: Selects SIB0 input and SOB0 output

0 FANOUT 0: Enable only A or B output depends on SEL1 and

0x08 Pin Control Override 7:5 Reserved R/W 0x00 Set bits to 0.

4 Override IDLE 0: Allow IDLE pin control

2 Override RATE 0: Allow RATE pin control

1 Override SEL 0: Allow SEL pin control

0 Override 0: Allow FANOUT pin control

0x0F SIA0 7:6 Reserved R/W 0x20 Set bits to 0. 0x12 SIA0 7:4 Reserved R/W 0x00 Set bits to 0. 0x15 DOUT0 7:6 Reserved R/W 0x00 Set bits to 0.

4 IDLE select 0: Output is ON (SD is disabled)

1 RATE auto 0: Allow RATE_sel control in Bit 0

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0x16 SIB0 7:6 Reserved R/W 0x20 Set bits to 0. 0x17 DOUT0 7 Reserved R/W 0x03 Set bit to 0. 0x19 SIB0 7:4 Reserved R/W 0x00 Set bits to 0. 0x1D SIA1 7:6 Reserved R/W 0x20 Set bits to 0. 0x20 SIA1 7:4 Reserved R/W 0x00 Set bits to 0.

0x23 DOUT1 7:6 Reserved R/W 0x00 Set bits to 0. 0x24 SIB1 7:6 Reserved R/W 0x20 Set bits to 0. 0x25 DOUT1 7 Reserved R/W 0x03 Set bit to 0. 0x27 SIB1 7:4 Reserved R/W 0x00 Set bits to 0. 0x2B SOA0 7:6 Reserved R/W 0x00 Set bits to 0.

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0x2C DIN0 7:6 Reserved R/W 0x20 Set bits to 0. 0x2D SOA0 7 Reserved R/W 0x03 Set bit to 0. 0x2F DIN0 7:4 Reserved R/W 0x00 Set bits to 0. 0x32 SOB0 7:6 Reserved R/W 0x00 Set bits to 0. 0x34 SOB0 7 Reserved R/W 0x03 Set bit to 0.

0x39 SOA1 7:6 Reserve R/W 0x00 Set bits to 0. 0x3A DIN1 7:6 Reserved R/W 0x20 Set bits to 0. 0x3B SOA1 7 Reserved R/W 0x03 Set bit to 0. 0x3D DIN1 7:4 Reserved R/W 0x00 Set bits to 0.

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0x40 SOB1 7:6 Reserved R/W 0x00 Set bits to 0. 0x42 SOB1 7 Reserved R/W 0x03 Set bit to 0. 0x47 Global VOD Adjust 7:2 Reserved R/W 0x02 Set bits to 0.

Unless otherwise noted, Typical Performance is measured at room temperature and nominal supply voltage. Figure 8. Electrical Specification DJ1: 40" 4-mil microstrip trace on Input Figure 9. Electrical Specification DJ2: 40" 4-mil microstrip trace on Input

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SNLS307E – JANUARY 2011– REVISED JULY 2013 www.ti.com APPLICATIONS INFORMATION General Recommendations The DS64MB201 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer to the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity design issues. PCB Layout Considerations for Differential Pairs The CML inputs and LPDS outputs must have a controlled differential impedance of 100Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-1187 (SNOA401) for additional information on WQFN packages. Power Supply Bypassing Two approaches are recommended to ensure that the DS64MB201 is provided with an adequate power supply. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.01 μF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the DS64MB201. Smaller body size capacitors can help facilitate proper component placement. Additionally, three capacitors with capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic.

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www.ti.com SNLS307E – JANUARY 2011– REVISED JULY 2013

REVISION HISTORY

Changes from Revision C (April 2013) to Revision D Page Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: DS64MB201

www.ti.com 30-Jul-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS64MB201SQ/NOPB ACTIVE WQFN NJY 54 2000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 DS64MB201 SQ DS64MB201SQE/NOPB ACTIVE WQFN NJY 54 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 DS64MB201 SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS64MB201SQ/NOPB WQFN NJY 54 2000 367.0 367.0 38.0 DS64MB201SQE/NOPB WQFN NJY 54 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2013 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 54X 0.3 0.2 3.51±0.1 50X 0.5 54X 0.5 0.3

0.8 MAX

8.5 7.5±0.1 2X 4 A 10.1 9.9 B 5.6 5.4 0.3 0.2 0.5 0.3 (0.1) 4214993/A 07/2013 WQFNNJY0054A WQFN PIN 1 INDEX AREA SEATING PLANE 18 28 19 27 54 46

0.1 C A B

0.05 C (OPTIONAL) PIN 1 ID DETAIL SEE TERMINAL NOTES: 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 2.000 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT (3.51)

0.07 MIN

0.07 MAX

54X (0.6) 54X (0.25) (9.8) (5.3) ( ) TYP VIA 0.2 50X (0.5) (1.16) (1) TYP (7.5) (1.17) TYP 4214993/A 07/2013 WQFNNJY0054A WQFN SYMM SEE DETAILS 19 27 4654 SYMM LAND PATTERN EXAMPLE SCALE:8X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING METAL SOLDER MASK DEFINED METAL SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (1.17) TYP (5.3) 54X (0.6) 54X (0.25) 12X (1.51) (9.8) (0.855) TYP 12X (0.97) 50X (0.5) 4214993/A 07/2013 WQFNNJY0054A WQFN NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM TYP METAL SOLDERPASTE EXAMPLE BASED ON 0.125mm THICK STENCIL EXPOSED PAD 67% PRINTED SOLDER COVERAGE BY AREA SCALE:10X 19 27 4654 SYMM

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