DS64EV400SQX

DS64EV400 NSC | Alldatasheet

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Technical content

Features

■ Equalizes up to 24 dB loss at 10 Gbps ■ Equalizes up to 22 dB loss at 6.4 Gbps ■ 8 levels of programmable equalization ■ Settable through control pins or SMBus interface ■ Operates up to 10 Gbps with 30” FR4 traces ■ Operates up to 6.4 Gbps with 40” FR4 traces ■ 0.175 UI residual deterministic jitter at 6.4 Gbps with 40” FR4 traces ■ Single 2.5V or 3.3V power supply ■ Signal Detect for individual channels ■ Standby mode for individual channels ■ Supports AC or DC-Coupling with wide input common- mode ■ Low power consumption: 375 mW Typ at 2.5V ■ Small 7 mm x 7 mm 48-pin LLP package ■ 9 kV HBM ESD Rating ■ -40 to 85°C operating temperature range Simplified Application Diagram 30032024 © 2008 National Semiconductor Corporation 300320 www.national.com DS64EV400 Programmable Quad Equalizer

Pin Name Pin # I/O, Type Description HIGH SPEED DIFFERENTIAL I/O IN_0+ IN_0– I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating resistor is connected between IN_0+ and IN_0-. Refer to Figure 6. IN_1+ IN_1– I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating resistor is connected between IN_1+ and IN_1-. Refer to Figure 6. IN_2+ IN_2– I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating resistor is connected between IN_2+ and IN_2-. Refer to Figure 6. IN_3+ IN_3– I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating resistor is connected between IN_3+ and IN_3-. Refer to Figure 6. OUT_0+ OUT_0– O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω terminating resistor connects OUT_0+ to VDD and OUT_0- to VDD. OUT_1+ OUT_1– O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω terminating resistor connects OUT_1+ to VDD and OUT_1- to VDD. OUT_2+ OUT_2– O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω terminating resistor connects OUT_2+ to VDD and OUT_2- to VDD. OUT_3+ OUT_3– O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω terminating resistor connects OUT_3+ to VDD and OUT_3- to VDD. EQUALIZATION CONTROL BST_2 BST_1 BST_0 I, LVCMOS BST_2, BST_1, and BST_0 select the equalizer strength for all EQ channels. BST_2 is internally pulled high. BST_1 and BST_0 are internally pulled low. DEVICE CONTROL EN0 44 I, LVCMOS Enable Equalizer Channel 0 input. When held High, normal operation is selected. When held Low, standby mode is selected. EN is internally pulled High. EN1 42 I, LVCMOS Enable Equalizer Channel 1 input. When held High, normal operation is selected. When held Low, standby mode is selected. EN is internally pulled High. EN2 40 I, LVCMOS Enable Equalizer Channel 2 input. When held High, normal operation is selected. When held Low, standby mode is selected. EN is internally pulled High. EN3 38 I, LVCMOS Enable Equalizer Channel 3 input. When held High, normal operation is selected. When held Low, standby mode is selected. EN is internally pulled High. FEB 21 I, LVCMOS Force External Boost. When held high, the equalizer boost setting is controlled by BST_[2:0] pins. When held low, the equalizer boost setting is controlled by SMBus (see Table 1) register bits. FEB is internally pulled High. SD0 45 O, LVCMOS Equalizer Ch0 Signal Detect Output. Produces a High when signal is detected. SD1 43 O, LVCMOS Equalizer Ch1 Signal Detect Output. Produces a High when signal is detected. SD2 41 O, LVCMOS Equalizer Ch2 Signal Detect Output. Produces a High when signal is detected. SD3 39 O, LVCMOS Equalizer Ch3 Signal Detect Output. Produces a High when signal is detected. POWER VDD 3, 6, 7, 10, 13, 15, 46 Power VDD = 2.5V ± 5% or 3.3V ± 10%. VDD pins should be tied to VDD plane through low inductance path. A 0.01μF bypass capacitor should be connected between each VDD pin to GND planes. GND 22, 24, 27, 30, 31, 34 Power Ground reference. GND should be tied to a solid ground plane through a low impedance path. DAP PAD Power Ground reference. The exposed pad at the center of the package must be connected to ground plane of the board. www.national.com 2 DS64EV400

Pin Name Pin # I/O, Type Description SERIAL MANAGEMENT BUS (SMBus) INTERFACE CONTROL PINS SDA SDC CS I/O, LVCMOS I, LVCMOS I, LVCMOS Data input/output (bi-directional). Internally pulled high. Clock input. Internally pulled high. Chip select. When pulled high, access to the equalizer SMBus registers are enabled. When pulled low, access to the equalizer SMBus registers are disabled. Please refer to “SMBus configuration Registers” section for detail information. Other Reserv 19, 20 47,48 Reserved. Do not connect. Note: I = Input O = Output Connection Diagram 30032026

Ordering Information

DS64EV400SQ 48–pin LLP (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch, reel of 250 SQA48D DS64EV400SQX 48–pin LLP (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch, reel of 2500 SQA48D 3 www.national.com DS64EV400

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) −0.5V to +4.0V CMOS Input Voltage −0.5V + 4.0V CMOS Output Voltage −0.5V to 4.0V CML Input/Output Voltage −0.5V to 4.0V Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4 Seconds) +260°C ESD Rating HBM, 1.5 k Ω, 100 pF > 9 kV CML Inputs > 250V Thermal Resistance θJA, No Airflow 30°C/W Recommended Operating Conditions Min Typ Max Units Supply Voltage (note 9) VDD2.5 to GND 2.375 2.5 2.625 V VDD3.3 to GND 3.0 3.3 3.6 V Ambient Temperature −40 25 +85 °C

Electrical Characteristics

Over recommended operating supply and temperature ranges with default register settings unless other specified. Symbol Parameter Conditions Min Typ (note 2) Max Units POWER P Power Supply Consumption Device Output Enabled (EN [0–3] = High), VDD3.3 490 700 mW Device Output Disable (EN [0–3] = Low), VDD3.3 100 mW P Power Supply Consumption Device Output Enabled (EN [0–3] = High), VDD2.5 360 490 mW Device Output Disable (EN [0–3] = Low), VDD2.5 N Supply Noise Tolerance (Note 4) 50 Hz — 100 Hz

100 Hz — 10 MHz

10 MHz — 1.6 GHz 100 mVP-P mVP-P mVP-P LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage VDD3.3 2.0 VDD3.3 V VDD2.5 1.6 VDD2.5 V VIL Low Level Input Voltage -0.3 0.8 V VOH High Level Output Voltage IOH = -3mA, VDD3.3 2.4 V IOH = -3mA, VDD2.5 2.0 VOL Low Level Output Voltage IOL = 3mA 0.4 V IIN Input Leakage Current VIN = VDD +15 μA VIN = GND -15 μA IIN-P Input Leakage Current with Internal Pull-Down/Up Resistors VIN = VDD, with internal pull-down resistors +120 μA VIN = GND, with internal pull-up resistors -20 μA SIGNAL DETECT SDH Signal Detect ON Threshold Level Default input signal level to assert SD pin, 6.4 Gbps 70 mVp-p SDI Signal Detect OFF Threshold Level Default input signal level to de- assert SD, 6.4 Gbps 40 mVp-p www.national.com 4 DS64EV400

0.8 VDDTX –

Figure 6. 85 100 115 Ω

0.20 UIP-P

Symbol Parameter Conditions Min Typ (note 2) Max Units SIGNAL DETECT and ENABLE TIMING tZISD Input OFF to ON detect — SD Output High Response Time Response time measurement at VIN to SD output, VIN = 800 mVP-P,

100 Mbps, 40” of 6 mil microstrip

(Figure 1, 4), (Note 7) 35 ns tIZSD Input ON to OFF detect — SD Output Low Response Time 400 ns tOZOED EN High to Output ON Response Time Response time measurement at EN input to VO, VIN = 800 mVP-P, (Figure 1, 5), (Note 7) 150 ns tZOED EN Low to Output OFF Response Time 5 ns Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only. Note 2: Typical values represent most likely parametric norms at VDD = 3.3V or 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 4: Allowed supply noise (mVP-P sine wave) under typical conditions. Note 5: Specification is guaranteed by characterization at optimal boost setting and is not tested in production. Note 6: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1). Random jitter is removed through the use of averaging or similar means. Note 7: Measured with clock-like {11111 00000} pattern. Note 8: Random jitter contributed by the equalizer is defined as sqrt (JOUT2 – JIN2). JOUT is the random jitter at equalizer outputs in ps-rms, see point C of Figure 1; JIN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 1. www.national.com 6 DS64EV400

Electrical Characteristics — Serial Management Bus Interface Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ Max Units SERIAL BUS INTERFACE DC SPECIFICATIONS VIL Data, Clock Input Low Voltage 0.8 V VIH Data, Clock Input High Voltage 2.1 VDD V IPULLUP Current Through Pull-Up Resistor or Current Source High Power Specification 4 mA VDD Nominal Bus Voltage 2.375 3.6 V ILEAK-Bus Input Leakage Per Bus Segment (Note 10) -200 +200 µA ILEAK-Pin Input Leakage Per Device Pin -15 µA CI Capacitance for SDA and SDC (Note 10, 11) 10 pF RTERM External Termination Resistance pull to VDD = 2.5V ± 5% OR 3.3V ± 10% VDD3.3, (Note 10, 11, 12) 2000 Ω VDD2.5, (Note 10, 11, 12) 1000 Ω SERIAL BUS INTERFACE TIMING SPECIFICATIONS (Figure 7) FSMB Bus Operating Frequency (Note 13) 10 100 kHz TBUF Bus Free Time Between Stop and Start Condition 4.7 µs THD:STA Hold time after (Repeated) Start Condition. After this period, the first clock is generated. At IPULLUP, Max 4.0 µs TSU:STA Repeated Start Condition Setup Time 4.7 µs TSU:STO Stop Condition Setup Time 4.0 µs THD:DAT Data Hold Time 300 ns TSU:DAT Data Setup Time 250 ns TTIMEOUT Detect Clock Low Timeout (Note 13) 25 35 ms TLOW Clock Low Period 4.7 µs THIGH Clock High Period (Note 13) 4.0 50 µs TLOW:SEXT Cumulative Clock Low Extend Time (Slave Device) (Note 13) 2 ms tF Clock/Data Fall Time (Note 13) 300 ns tR Clock/Data Rise Time (Note 13) 1000 ns tPOR Time in which a device must be operational after power-on reset (Note 13) 500 ms Note 10: Recommended value. Parameter not tested in production. Note 11: Recommended maximum capacitance load per bus segment is 400pF. Note 12: Maximum termination voltage should be identical to the device supply voltage. AC specifications for details. 7 www.national.com DS64EV400

System Management Bus (SMBus) and Configuration Registers The System Management Bus interface is compatible to SM- Bus 2.0 physical layer specification. The use of the Chip Select signal is required. Holding the CS pin High enables the SMBus port allowing access to the configuration registers. Holding the CS pin Low disables the device's SMBus allowing communication from the host to other slave devices on the bus. In the STANDBY state, the System Management Bus remains active. When communication to other devices on the SMBus is active, the CS signal for the DS32EV400s must be driven Low. The address byte for all DS64EV400s is AC'h. Based on the SMBus 2.0 specification, the DS64EV400 has a 7-bit slave address of 1010110'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 1100'b or AC'h. The SDC and SDA pins are 3.3V LVCMOS signaling and in- clude high-Z internal pull up resistors. External low impedance pull up resistors maybe required depending upon SMBus loading and speed. Note, these pins are not 5V tol- erant. Transfer of Data via the SMBus During normal operation the data on SDA must be stable dur- ing the time when SDC is High. There are three unique states for the SMBus: START: A High-to-Low transition on SDA while SDC is High indicates a message START condition. STOP: A Low-to-High transition on SDA while SDC is High indicates a message STOP condition. IDLE: If SDC and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state. SMBus Transactions The device supports WRITE and READ transactions. See Register Description table for register address, type (Read/ Write, Read Only), default value and function information. Writing a Register To write a register, the following protocol is used (see SMBus 2.0 specification). 1. The Host (Master) selects the device by driving its SMBus Chip Select (CS) signal High. 2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 3. The Device (Slave) drives the ACK bit (“0”). 4. The Host drives the 8-bit Register Address. 5. The Device drives an ACK bit (“0”). 6. The Host drive the 8-bit data byte. 7. The Device drives an ACK bit (“0”). 8. The Host drives a STOP condition. 9. The Host de-selects the device by driving its SMBus CS signal Low. The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. Reading a Register To read a register, the following protocol is used (see SMBus 2.0 specification). 1. The Host (Master) selects the device by driving its SMBus Chip Select (CS) signal High. 2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 3. The Device (Slave) drives the ACK bit (“0”). 4. The Host drives the 8-bit Register Address. 5. The Device drives an ACK bit (“0”). 6. The Host drives a START condition. 7. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ. 8. The Device drives an ACK bit “0”. 9. The Device drives the 8-bit data value (register contents). 10. The Host drives a NACK bit “1”indicating end of the READ transfer. 11. The Host drives a STOP condition. 12. The Host de-selects the device by driving its SMBus CS signal Low. The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. Please see Table 1 for more information. www.national.com 8 DS64EV400

TABLE 1. SMBus Register Address

FIGURE 8. Simplified Block Diagram TABLE 2. EQ Boost Control Table

24 AWG

3.2 GHz

Bus port, as well as the signal detection circuit remain active. TABLE 3. Controlling Device State

that has exceeded the ON threshold value (called SD_ON). signal minus negative signal) at the input of the device. TABLE 4. Signal Detect Threshold Values TABLE 5. Output Level Control Settings to be placed in the STANDBY state.

FIGURE 9. Automatic Enable Configuration tips to address signal integrity design issues. placed symmetrically for each side of a given differential pair. tional information on LLP packages. DS64EV400 is provided with an adequate power supply. capacitor is placed as close as possible to the DS64EV400. should be placed as close as possible to the DS64EV400.

Physical Dimensions inches (millimeters) unless otherwise noted 48-pin LLP Package (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch) Order Number DS64EV400SQ 17 www.national.com DS64EV400

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