DS64EV400SQ/NOPB

DS64EV400_15 TI1 | Alldatasheet

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www.ti.com SNLS281H –AUGUST 2007–REVISED APRIL 2013 DS64EV400ProgrammableQuadEqualizer Check forSamples: DS64EV400 1FEATURES DESCRIPTION The DS64EV400 programmable quad equalizer 2• Equalizesup to24 dB Loss at10 Gbps provides compensation for transmissionmedium• Equalizesup to22 dB Loss at6.4Gbps lossesand reducesthemedium-induceddeterministic

• 8 LevelsofProgrammable Equalization jitterforfourNRZ datachannels.The DS64EV400 is optimizedforoperationup to10 Gbps forbothcables• Settablethrough ControlPins or SMBus and FR4 traces.Each equalizerchannel has eightTnterface levelsof inputequalizationthatcan be programmed• Operates up to10 Gbps with30” FR4 Traces by threecontrolpins,or individuallythrougha Serial
• Operates up to6.4Gbps with40” FR4 Traces Management Bus (SMBus) interface.
• 0.175UI ResidualDeterministicJitterat6.4 The equalizersupportsbothAC and DC-coupleddata Gbps with40” FR4 Traces paths for long run lengthdata patternssuch as PRBS-31, and balancedcodes such as 8b/10b.The• Single2.5Vor 3.3VPower Supply device uses differentialcurrent-modelogic(CML)• SignalDetectforIndividualChannels inputsand outputs.The DS64EV400 isavailableina• Standby Mode forIndividualChannels 7 mm x 7 mm 48-pinleadlessWQFN package.
• Supports AC or DC-Coupling withWide Input Power issuppliedfromeithera 2.5Vor3.3Vsupply. Common-Mode
• Low Power Consumption: 375 mW Typ at2.5V
• Small 7 mm x 7 mm 48-PinWQFN Package
• 9 kV HBM ESD Rating
• -40to85°C OperatingTemperature Range SimplifiedApplicationDiagram Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2007–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS281H –AUGUST 2007–REVISED APRIL 2013 www.ti.com Pin Descriptions Pin Name Pin No. I/O,Type (1) Description HIGH SPEED DIFFERENTIAL I/O IN_0+ 1 I,CML Invertingand non-invertingCML differentialinputstotheequalizer.An on-chip100Ω IN_0– 2 terminatingresistorisconnectedbetween IN_0+ and IN_0-.RefertoFigure7. IN_1+ 4 I,CML Invertingand non-invertingCML differentialinputstotheequalizer.An on-chip100Ω IN_1– 5 terminatingresistorisconnectedbetween IN_1+ and IN_1-.RefertoFigure7. IN_2+ 8 I,CML Invertingand non-invertingCML differentialinputstotheequalizer.An on-chip100Ω IN_2– 9 terminatingresistorisconnectedbetween IN_2+ and IN_2-.RefertoFigure7. IN_3+ 11 I,CML Invertingand non-invertingCML differentialinputstotheequalizer.An on-chip100Ω IN_3– 12 terminatingresistorisconnectedbetween IN_3+ and IN_3-.RefertoFigure7. OUT_0+ 36 O, CML Invertingand non-invertingCML differentialoutputsfromtheequalizer.An on-chip50Ω OUT_0 – 35 terminatingresistorconnectsOUT_0+ toVDD and OUT_0- toVDD . OUT_1+ 33 O, CML Invertingand non-invertingCML differentialoutputsfromtheequalizer.An on-chip50Ω OUT_1 – 32 terminatingresistorconnectsOUT_1+ toVDD and OUT_1- toVDD . OUT_2+ 29 O, CML Invertingand non-invertingCML differentialoutputsfromtheequalizer.An on-chip50Ω OUT_2 – 28 terminatingresistorconnectsOUT_2+ toVDD and OUT_2- toVDD . OUT_3+ 26 O, CML Invertingand non-invertingCML differentialoutputsfromtheequalizer.An on-chip50Ω OUT_3 – 25 terminatingresistorconnectsOUT_3+ toVDD and OUT_3- toVDD . EQUALIZATION CONTROL BST_2 37 I,LVCMOS BST_2, BST_1, and BST_0 selecttheequalizerstrengthforallEQ channels.BST_2 is BST_1 14 internallypulledhigh.BST_1 and BST_0 areinternallypulledlow. BST_0 23 DEVICE CONTROL EN0 44 I,LVCMOS EnableEqualizerChannel0 input.When heldHigh,normaloperationisselected.When held Low, standbymode isselected.EN isinternallypulledHigh. EN1 42 I,LVCMOS EnableEqualizerChannel1 input.When heldHigh,normaloperationisselected.When held Low, standbymode isselected.EN isinternallypulledHigh. EN2 40 I,LVCMOS EnableEqualizerChannel2 input.When heldHigh,normaloperationisselected.When held Low, standbymode isselected.EN isinternallypulledHigh. EN3 38 I,LVCMOS EnableEqualizerChannel3 input.When heldHigh,normaloperationisselected.When held Low, standbymode isselected.EN isinternallypulledHigh. FEB 21 I,LVCMOS ForceExternalBoost.When heldhigh,theequalizerboostsettingiscontrolledby BST_[2:0] pins.When heldlow,theequalizerboostsettingiscontrolledby SMBus (Table1)registerbits. FEB isinternallypulledHigh. SD0 45 O, LVCMOS EqualizerCh0 SignalDetectOutput.Producesa Highwhen signalisdetected. SD1 43 O, LVCMOS EqualizerCh1 SignalDetectOutput.Producesa Highwhen signalisdetected. SD2 41 O, LVCMOS EqualizerCh2 SignalDetectOutput.Producesa Highwhen signalisdetected. SD3 39 O, LVCMOS EqualizerCh3 SignalDetectOutput.Producesa Highwhen signalisdetected. POWER VDD 3,6,7, Power VDD = 2.5V± 5% or3.3V± 10%. VDD pinsshouldbe tiedtoVDD planethroughlowinductance 10,13, path.A 0.01μF bypasscapacitorshouldbe connectedbetween each VDD pintoGND planes. 15,46 GND 22,24, Power Ground reference.GND shouldbe tiedtoa solidgroundplanethrougha lowimpedance path. 27,30, 31,34 DAP PAD Power Ground reference.The exposed pad atthecenterofthepackage must be connectedtoground planeoftheboard. SERIAL MANAGEMENT BUS (SMBus) INTERFACE CONTROL PINS SDA 18 I/O,LVCMOS Data input/output(bi-directional).Internallypulledhigh. SDC 17 I,LVCMOS Clockinput.Internallypulledhigh. CS 16 I,LVCMOS Chipselect.When pulledhigh,accesstotheequalizerSMBus registersareenabled.When pulledlow,accesstotheequalizerSMBus registersaredisabled.Pleasereferto“SMBus configurationRegisters”sectionfordetailinformation. Other Reserv 19,20 Reserved.Do notconnect. 47,48 (1) Note:I= Input O = Output

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IN_3- IN_3+ IN_2- IN_2+ IN_1- IN_1+ IN_0- IN_0+ OUT_3- OUT_3+ OUT_2- OUT_2+ OUT_1- OUT_1+ OUT_0- OUT_0+ VDD VDD VDD VDD GND GND GND GND VDD VDD GND GND BST_1 BST_0 CS SDC SDA Reserv VDD SD0 EN0 SD1 EN1 SD2 EN2 SD3 EN3 Reserv BST_2 Reserv Reserv FEB DS64EV400 TOP VIEW DAP = GND DS64EV400 www.ti.com SNLS281H –AUGUST 2007–REVISED APRIL 2013 Connection Diagram Figure1. WQFN Package See Package Number NJU0048D These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2) SupplyVoltage(VDD ) −0.5Vto+4.0V CMOS InputVoltage −0.5V+ 4.0V CMOS OutputVoltage −0.5Vto4.0V CML Input/OutputVoltage −0.5Vto4.0V JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature(Soldering,4 Seconds) +260°C ESD Rating HBM, 1.5kΩ,100 pF > 9 kV EIAJ,0Ω,200 pF > 250V ThermalResistance θJA,No Airflow 30°C/W (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions.Absolute Maximum Numbers areensuredfora junctiontemperaturerangeof-40°C to+125°C. Models arevalidatedtoMaximum Operating Voltagesonly. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS64EV400

SNLS281H –AUGUST 2007–REVISED APRIL 2013 www.ti.com Recommended OperatingConditions Min Typ Max Units SupplyVoltage VDD2.5 toGND 2.375 2.5 2.625 V VDD3.3 toGND 3.0 3.3 3.6 V AmbientTemperature −40 25 +85 °C ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangeswithdefaultregistersettingsunlessotherspecified. Parameter TestConditions Min Typ (1) Max Units POWER P Power SupplyConsumption DeviceOutputEnabled 490 700 mW(EN [0–3]= High),VDD3.3 (2) DeviceOutputDisable 100 mW(EN [0–3]= Low),VDD3.3 P Power SupplyConsumption DeviceOutputEnabled 360 490 mW(EN [0–3]= High),VDD2.5 (2) DeviceOutputDisable 30(EN [0–3]= Low),VDD2.5 (2) N SupplyNoiseTolerance(3) 50 Hz — 100 Hz 100 mV P-P

100 Hz — 10 MHz 40 mV P-P

10 MHz — 1.6GHz 10 mV P-P LVCMOS DC SPECIFICATIONS VIH HighLevelInputVoltage VDD3.3 2.0 VDD3.3 V VDD2.5 1.6 VDD2.5 V VIL Low LevelInputVoltage -0.3 0.8 V VOH HighLevelOutputVoltage IOH = -3mA, VDD3.3 2.4 V IOH = -3mA, VDD2.5 2.0 VOL Low LevelOutputVoltage IOL = 3mA 0.4 V IIN InputLeakage Current VIN = VDD +15 μA VIN = GND -15 μA IIN-P InputLeakage CurrentwithInternal VIN = VDD ,withinternalpull-downresistors +120 μA Pull-Down/UpResistors VIN = GND, withinternalpull-upresistors -20 μA SIGNAL DETECT SDH SignalDetectON ThresholdLevel DefaultinputsignalleveltoassertSD pin,6.4 70 mV p-p Gbps SDI SignalDetectOFF ThresholdLevel Defaultinputsignalleveltode-assertSD, 6.4 40 mV p-p Gbps CML RECEIVER INPUTS (IN_n+,IN_n-) VTX SourceTransmitLaunch SignalLevel AC-Coupled orDC-Coupled Requirement, (INdiff) Differentialmeasurement atpointA. 400 1600 mV P-P Figure2 VINTRE InputThresholdVoltage Differentialmeasurement at 120 mV P-PpointB.Figure2 VDDTX SupplyVoltageofTransmittertoEQ DC-Coupled Requirement(4) 1.6 VDD V VICMDC InputCommon Mode Voltage DC-Coupled Requirement,Differential VDDTX – VDDTX Vmeasurement atpointA.Figure2,(5) 0.8 – 0.2 R LI DifferentialInputReturnLoss 100 MHz – 3.2GHz, withfixture’s effectde- 10 dBembedded (1) Typicalvaluesrepresentmost likelyparametricnorms atVDD = 3.3Vor2.5V,TA = 25°C, and attheRecommended Operation Conditionsatthetimeofproductcharacterizationand arenotensured. (3) Allowedsupplynoise(mV P-P sinewave) undertypicalconditions. (4) Recommended value.Parameternottestedinproduction. (5) Measured withclock-like{1111100000}pattern.

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www.ti.com SNLS281H –AUGUST 2007–REVISED APRIL 2013 ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangeswithdefaultregistersettingsunlessotherspecified. Parameter TestConditions Min Typ (1) Max Units R IN InputResistance DifferentialacrossIN+ and IN-,Figure7 85 100 115 Ω CML OUTPUTS (OUT_n+, OUT_n-) VOD OutputDifferentialVoltageLevel Differentialmeasurement withOUT+ and OUT- (OUT diff) terminatedby 50Ω toGND, AC-Coupled 500 620 725 mV P-P Figure3 VOCM OutputCommon Mode Voltage Single-endedmeasurement DC-Coupled with VDD – VDD – V50Ω terminations(5) 0.2 0.1 tR ,tF TransitionTime 20% to80% ofdifferentialoutputvoltage, measured within1”fromoutputpins. 20 60 ps Figure3,(5) R O OutputResistance Singleended toVDD 42 50 58 Ω R LO DifferentialOutputReturnLoss 100 MHz – 1.6GHz, withfixture’s effectde- 10 dBembedded. IN+ = statichigh. tPLHD DifferentialLow toHighPropagation Propagationdelaymeasurement at50% VO 240 psDelay between inputtooutput,100 Mbps. Figure4, (5) tPHLD DifferentialHightoLow Propagation 240 psDelay tCCSK InterPairChanneltoChannelSkew Differencein50% crossingbetween channels 7 ps tPPSK ParttoPartOutputSkew Differencein50% crossingbetween outputs 20 ps EQUALIZATION DJ1 ResidualDeterministicJitter 30”of6 milmicrostripFR4, 0.20 UIP-Pat10 Gbps EQ Setting0x06,PRBS-7 (27-1)pattern.(6) DJ2 ResidualDeterministicJitter 40”of6 milmicrostripFR4, 0.17 0.26 UIP-Pat6.4Gbps EQ Setting0x06,PRBS-7 (27-1)pattern.(7)(6) DJ3 ResidualDeterministicJitter 40”of6 milmicrostripFR4, 0.12 0.20 UIP-Pat5 Gbps EQ Setting0x07,PRBS-7 (27-1)pattern.(7)(6) DJ4 ResidualDeterministicJitter 40”of6 milmicrostripFR4, 0.1 0.16 UIP-Pat2.5Gbps EQ Setting0x07,PRBS-7 (27-1)pattern.(7)(6) RJ Random Jitter See (8)(9) 0.5 psrms SIGNAL DETECT and ENABLE TIMING tZISD InputOFF toON detect— SD Output Response timemeasurement atVIN toSD 35 nsHighResponse Time output,VIN = 800 mV P-P,100 Mbps, 40”of6 mil microstripFR4tIZSD InputON toOFF detect— SD Output 400 nsFigure2 and Figure5,(8) Low Response Time tOZOED EN HightoOutputON Response Response timemeasurement atEN inputto 150 nsTime VO ,VIN = 800 mV P-P,100 Mbps, 40”of6 mil microstripFR4tZOED EN Low toOutputOFF Response 5 nsFigure2 and Figure7,(8) Time (6) Deterministicjitterismeasured atthedifferentialoutputs(pointC ofFigure2),minus thedeterministicjitterbeforethetestchannel(point A ofFigure2).Random jitterisremoved throughtheuse ofaveragingorsimilarmeans. (7) Specificationisensuredby characterizationatoptimalboostsettingand isnottestedinproduction. (8) Measured withclock-like{1111100000}pattern. (9) Random jittercontributedby theequalizerisdefinedas sqrt(JOUT 2 – JIN 2).JOUT istherandom jitteratequalizeroutputsinps-rms,see pointC ofFigure2;JIN istherandom jitterattheinputoftheequalizerinps-rms,see pointB ofFigure2. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS64EV400

SNLS281H –AUGUST 2007–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics— SerialManagement Bus Interface Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Parameter TestConditions Min Typ Max Units SERIAL BUS INTERFACE DC SPECIFICATIONS VIL Data,ClockInputLow Voltage 0.8 V VIH Data,ClockInputHighVoltage 2.1 VDD V IPULLUP CurrentThroughPull-UpResistoror HighPower Specification 4 mACurrentSource VDD NominalBus Voltage 2.375 3.6 V ILEAK-Bus InputLeakage Per Bus Segment See (1) -200 +200 µA ILEAK-Pin InputLeakage Per DevicePin -15 µA C I CapacitanceforSDA and SDC See (1)(2) 10 pF R TERM ExternalTerminationResistancepull VDD3.3,(1)(2)(3) 2000 Ω toVDD = 2.5V± 5% OR VDD2.5,(1)(2)(3) 1000 Ω3.3V± 10% SERIAL BUS INTERFACE TIMING SPECIFICATIONS (Figure8) FSMB Bus OperatingFrequency See (4) 10 100 kHz TBUF Bus FreeTime Between Stopand 4.7 µsStartCondition THD:STA Holdtimeafter(Repeated)Start AtIPULLUP ,Max Condition.Afterthisperiod,thefirst 4.0 µs clockisgenerated. TSU:STA Repeated StartConditionSetupTime 4.7 µs TSU:STO StopConditionSetupTime 4.0 µs THD:DAT Data HoldTime 300 ns TSU:DAT Data SetupTime 250 ns TTIMEOUT DetectClockLow Timeout See (4) 25 35 ms TLOW ClockLow Period 4.7 µs THIGH ClockHighPeriod See (4) 4.0 50 µs TLOW :SEXT CumulativeClockLow ExtendTime See (4) 2 ms(SlaveDevice) tF Clock/DataFallTime See (4) 300 ns tR Clock/DataRiseTime See (4) 1000 ns tPOR Time inwhicha devicemust be See (4) 500 msoperationalafterpower-onreset (1) Recommended value.Parameternottestedinproduction. (2) Recommended maximum capacitanceloadperbus segment is400pF. (3) Maximum terminationvoltageshouldbe identicaltothedevicesupplyvoltage. SMBus common AC specificationsfordetails.

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www.ti.com SNLS281H –AUGUST 2007–REVISED APRIL 2013 System Management Bus (SMBus) and ConfigurationRegisters The System Management Bus interfaceiscompatibletoSMBus 2.0physicallayerspecification.The use ofthe Chip Selectsignalis required. Holdingthe CS pin High enables the SMBus portallowingaccess to the configurationregisters.HoldingtheCS pinLow disablesthedevice'sSMBus allowingcommunicationfrom the hostto otherslavedeviceson the bus.In the STANDBY state,the System Management Bus remainsactive. When communicationto otherdeviceson the SMBus isactive,the CS signalforthe DS32EV400s must be drivenLow. The addressbyteforallDS64EV400s isAC'h.Based on theSMBus 2.0specification,theDS64EV400 has a 7- bitslaveaddressof1010110'b.The LSB issetto0'b(fora WRITE), thusthe8-bitvalueis1010 1100'borAC'h. The SDC and SDA pinsare 3.3V LVCMOS signalingand includehigh-Zinternalpullup resistors.Externallow impedance pullup resistorsmaybe requireddependingupon SMBus loadingand speed.Note,thesepinsarenot 5V tolerant. TransferofData viatheSMBus Duringnormaloperationthedataon SDA must be stableduringthetimewhen SDC isHigh. TherearethreeuniquestatesfortheSMBus: START A High-to-Lowtransitionon SDA whileSDC isHighindicatesa message START condition. STOP A Low-to-Hightransitionon SDA whileSDC isHighindicatesa message STOP condition. IDLE IfSDC and SDA arebothHighfora timeexceedingtBUF fromthelastdetectedSTOP conditionorifthey areHighfora totalexceedingthemaximum specificationfortHIGH thenthebus willtransfertotheIDLE state. SMBus Transactions The devicesupportsWRITE and READ transactions.See RegisterDescriptiontableforregisteraddress,type (Read/Write,Read Only),defaultvalueand functioninformation. Writinga Register To writea register,thefollowingprotocolisused (seeSMBus 2.0specification). 1. The Host(Master)selectsthedeviceby drivingitsSMBus ChipSelect(CS)signalHigh. 2. The Hostdrivesa START condition,the7-bitSMBus address,and a “0”indicatinga WRITE. 3. The Device(Slave)drivestheACK bit(“0”). 4. The Hostdrivesthe8-bitRegisterAddress. 5. The Devicedrivesan ACK bit(“0”). 6. The Hostdrivethe8-bitdatabyte. 7. The Devicedrivesan ACK bit(“0”). 8. The Hostdrivesa STOP condition. 9. The Hostde-selectsthedeviceby drivingitsSMBus CS signalLow. The WRITE transactioniscompleted,the bus goes IDLE and communicationwithotherSMBus devicesmay now occur. Reading a Register To reada register,thefollowingprotocolisused (seeSMBus 2.0specification). 1. The Host(Master)selectsthedeviceby drivingitsSMBus ChipSelect(CS)signalHigh. 2. The Hostdrivesa START condition,the7-bitSMBus address,and a “0”indicatinga WRITE. 3. The Device(Slave)drivestheACK bit(“0”). 4. The Hostdrivesthe8-bitRegisterAddress. 5. The Devicedrivesan ACK bit(“0”). 6. The Hostdrivesa START condition. 7. The Hostdrivesthe7-bitSMBus Address,and a “1”indicatinga READ. 8. The Devicedrivesan ACK bit“0”. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS64EV400

SNLS281H –AUGUST 2007–REVISED APRIL 2013 www.ti.com 9. The Devicedrivesthe8-bitdatavalue(registercontents). 10. The Hostdrivesa NACK bit“1”indicatingend oftheREAD transfer. 11. The Hostdrivesa STOP condition. 12. The Hostde-selectsthedeviceby drivingitsSMBus CS signalLow. The READ transactioniscompleted,thebus goes IDLE and communicationwithotherSMBus devicesmay now occur. See Table1 formore information. Table1.SMBus RegisterAddress TypeName Address Default Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0(1) Status 0x00 0x00 RO ID Revision SD3 SD2 SD1 SD0 Status 0x01 0x00 RO EN1 Boost1 EN0 Boost0 Status 0x02 0x00 RO EN3 Boost3 EN2 Boost2 Enable/Boost 0x03 0x44 RW EN1 Output BoostControlforCH1 EN0 BoostControlforCH0 (CH 0,1) 0:Enable 000 (MinBoost) Output 000 (MinBoost) 1:Disable 001 0:Enable 001 010 1:Disable 010 011 011 100 (Default) 100 (Default) 101 101 110 110 111 (Max Boost) 111 (Max Boost) Enable/Boost 0x04 0x44 RW EN3 Output BoostControlforCH3 EN2 BoostControlforCH2 (CH 2,3) 0:Enable 000 (MinBoost) Output 000 (MinBoost) 1:Disable 001 0:Enable 001 010 1:Disable 010 011 011 100 (Default) 100 (Default) 101 101 110 110 111 (Max Boost) 111 (Max Boost) SignalDetect 0x05 0x00 RW SD3 ON Threshold SD2 ON Threshold SD1 ON Threshold SD0 ON Threshold Select Select Select Select 00:70 mV (Default) 00:70 mV (Default) 00:70 mV (Default) 00:70 mV (Default) 01:55 mV 01:55 mV 01:55 mV 01:55 mV 10:90 mV 10:90 mV 10:90 mV 10:90 mV 11:75 mV 11:75 mV 11:75 mV 11:75 mV SignalDetect 0x06 0x00 RW SD3 OFF Threshold SD2 OFF Threshold SD1 OFF Threshold SD0 OFF Threshold Select Select Select Select 00:40 mV (Default) 00:40 mV (Default) 00:40 mV (Default) 00:40 mV (Default) 01:30 mV 01:30 mV 01:30 mV 01:30 mV 10:55 mV 10:55 mV 10:55 mV 10:55 mV 11:45 mV 11:45 mV 11:45 mV 11:45 mV SMBus 0x07 0x00 RW Reserved SMBus Control Enable Control 0:Disable 1:Enable Output Level 0x08 0x78 RW Reserved OutputLevel: Reserved 00:400 mV P-P 01:540 mV P-P 10:620 mV P- P(Default) 11:760 mV P-P (1) Note:RO = Read Only,RW = Read/Write

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1.5V1.5V IN diff tPLHD tPHLD OUT diff IN diff 0V 20% 80% 80% 20% OUT diff = (OUT+) ± (OUT-) tFtR DS64EV400 INPUT OUTPUT 6 mils Trace Width, FR4 Microstrip Test Channel SMA Connector SMA Connector Signal Source A B C DS64EV400 www.ti.com SNLS281H –AUGUST 2007–REVISED APRIL 2013 Figure2. TestSetup Diagram Figure3. CML Output TransitionTimes Figure4. PropagationDelay Timing Diagram Figure5. SignalDetect(SD)Delay Timing Diagram Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS64EV400

tBUF tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA ST SP tSU:STO SDC SDA CS tSU:CS ST VDD 10k IN + EQ IN - VDD 10k tOZED VDD 1.5VEN 1.5V 0VOUT diff tZOED DS64EV400 SNLS281H –AUGUST 2007–REVISED APRIL 2013 www.ti.com Figure6. Enable (EN)Delay Timing Diagram Figure7. SimplifiedReceiverInputTerminationCircuit Figure8. SMBus Timing Parameters DS64EV400 FUNCTIONAL DESCRIPTIONS The DS64EV400 isa programmable quad equalizeroptimizedforoperationup to10 Gbps forbackplaneand cableapplications. DATA CHANNELS The DS64EV400 providesfourdata channels.Each data channelconsistsof an equalizerstage,a limiting amplifier,a DC offsetcorrectionblock,and a CML driveras shown inFigure9.

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IN_n + Input Termination Equalizer Limiting Amplifier DC Offset CorrectionData Channel (0-3) Boost Setting BST_0:BST_2 BST CNTL EN EN EN- FEB ENn SMBus Register IN_n OUT_n OUT_n SDSDn VDD SMBus Register Reg 07 bit 0 Reg 03,04 bit 7, 3 VDD DS64EV400 www.ti.com SNLS281H –AUGUST 2007–REVISED APRIL 2013 Figure9. SimplifiedBlock Diagram EQUALIZER BOOST CONTROL Each datachannelsupporteightprogrammablelevelsofequalizationboost.The stateoftheFEB pindetermines how theboostsettingsarecontrolled.IftheFEB pinisheldHigh,thentheequalizerboostsettingiscontrolledby theBoostSet pins(BST_[2:0])inaccordancewithTable2.Ifthisprogrammingmethod ischosen,thentheboost settingselectedon theBoost Set pinsisappliedtoallchannels.When theFEB pinisheldLow, theequalizer boostleveliscontrolledthroughtheSMBus. Thisprogramming method isaccessed viatheappropriateSMBus registers(see Table 1).Using thisapproach,equalizerboost settingscan be programmed foreach channel individually.FEB isinternallypulledHigh (defaultsetting);thereforeifleftunconnected,the boostsettingsare controlledby the Boost Set pins(BST_[0:2]).The eightlevelsof boost settingsenablesthe DS64EV400 to addressa widerangeofmedia lossand datarates. Table2. EQ Boost ControlTable 6 milMicrostripFR4 24 AWG Twin-AX cable Channel Loss at3.2GHz Channel Loss at5 GHz BST_N Trace Length (m) length(m) (dB) (dB) [2,1,0] 0 0 0 0 0 0 0 5 2 5 6 0 0 1 10 3 7.5 10 0 1 0 15 4 10 14 0 1 1 20 5 12.5 18 1 0 0 (Default) 25 6 15 21 1 0 1 30 7 17 24 1 1 0 40 10 22 30 1 1 1 DEVICE STATE AND ENABLE CONTROL The DS64EV400 has an enablefeatureon each datachannelwhichprovidestheabilitytocontroldevicepower consumption.Thisfeaturecan be controlledeitheran Enable Pin (EN_n) withReg 07 = 00'h(defaultvalue),or by theEnableControlBitregisterwhichcan be configuredthroughtheSMBus port(seeTable1 and Table3 for detailregisterinformation),whichrequiresettingReg 07 = 01'hand changingregistervalueofReg 03,04.Ifthe Enable isactivatedusingeitherthe externalEN_n pinor SMBUS register,the correspondingdata channelis placedintheACTIVE stateand alldeviceblocksfunctionas described.The DS64EV400 can alsobe placedin STANDBY mode tosave power.IntheSTANDBY mode onlythecontrolinterfaceincludingtheSMBus port,as wellas thesignaldetectioncircuitremainactive. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS64EV400

SNLS281H –AUGUST 2007–REVISED APRIL 2013 www.ti.com Table3. ControllingDevice State CH 0: Reg. 03 bit3 CH 1: Reg. 03 bit7 Register070 ENn Pin (CMOS) CH 2: Device State Reg. 04 bit3 CH 3: Reg. 04 bit7 (EN Control) 0 :Disable 1 X ACTIVE 0 :Disable 0 X STANDBY 1 :Enable X 0 ACTIVE 1 :Enable X 1 STANDBY SIGNAL DETECT The DS64EV400 featuresa signaldetectcircuiton each datachannel.The statusofthesignalofeach channel can be determinedby eitherreadingtheSignalDetectbit(SDn) intheSMBus registers(seeTable1)orby the stateof each SDn pin.An outputlogichigh indicatesthe presence of a signalthathas exceeded the ON thresholdvalue(calledSD_ON). An outputlogicLow means thatthe inputsignalhas fallenbelow the OFF thresholdvalue(calledSD_OFF). These valuesareprogrammed viatheSMBus (Table1).Ifnotprogrammed via theSMBus, thethresholdstakeon thedefaultvaluesas shown inTable4.The SignalDetectthresholdvalues can be changed throughthe SMBus. Allthresholdvaluesspecifiedare DC peak-to-peakdifferentialsignals (positivesignalminus negativesignal)attheinputofthedevice. Table4. SignalDetectThresholdValues Channel 0:Bit1 Channel 0:Bit0 Channel 1:Bit3 Channel 1:Bit2 SD_OFF Threshold SD_ON Threshold Channel 2:Bit5 Channel 2:Bit4 Register06 (mV) Register05 (mV) Channel 3:Bit7 Channel 3:Bit6 0 0 40 (Default) 70 (Default) 0 1 30 55 1 0 55 90 1 1 45 75 OUTPUT LEVEL CONTROL The outputamplitudeoftheCML driversforeach channelcan be controlledviatheSMBus (seeTable1).The defaultoutputlevelis620 mV p-p.The followingTablepresentstheoutputlevelvaluessupported: Table5. Output LevelControlSettings AllChannels :Bit3 AllChannels :Bit2 Output LevelRegister08 (mV P-P) 0 0 400 0 1 540 1 0 620 (Default) 1 1 760 AUTOMATIC ENABLE FEATURE Itmay be desirableto placeunused channelsinpower-savingStandby mode. Thiscan be accomplishedby connectingtheSignaldetect(SDn)pintotheEnable(ENn)pinforeach channel(See Figure10).Inorderforthis optiontofunctionproperly,theregistervalueforReg. 07 shouldbe 00'h(defaultvalue).Ifan inputsignalswing appliedtoa datachannelisabove thevoltagelevelthresholdas shown inTable4,thentheSDn outputpinis assertedHigh.IftheSDn pinisconnectedtotheENn pin,thiswillenabletheequalizer,limitingamplifier,and outputbufferon thedatachannels;thustheDS64EV400 willautomaticallyentertheACTIVE state.Iftheinput signalswing fallsbelow the SD_OFF thresholdlevel,then the SDn outputwillbe assertedLow, causingthe channeltobe placedintheSTANDBY state.

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IN_n r ENn SDn Equalizer Limiting Amplifier CML Driver Signal Detect OUT_n r Reg 07 = K¶00 (Default) DS64EV400 www.ti.com SNLS281H –AUGUST 2007–REVISED APRIL 2013 DS64EV400 ApplicationsInformation Figure10. Automatic Enable Configuration UNUSED EQUALIZER CHANNELS Itisrecommended toputallunused channelsintostandbymode. GENERAL RECOMMENDATIONS The DS64EV400 isa high performancecircuitcapableof deliveringexcellentperformance.Carefulattention must be paidtothedetailsassociatedwithhigh-speeddesignas wellas providinga cleanpower supply.Refer totheLVDS Owner'sManual formore detailedinformationon highspeed designtipstoaddresssignalintegrity designissues. PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS The CML inputsand outputsmust have a controlleddifferentialimpedance of100Ω.ItispreferabletorouteCML linesexclusivelyon one layeroftheboard,particularlyfortheinputtraces.The use ofviasshouldbe avoidedif possible.Ifviasmust be used,theyshouldbe used sparinglyand must be placedsymmetricallyforeach sideof a givendifferentialpair.Route theCML signalsaway fromothersignalsand noisesourceson theprintedcircuit board.See AN-1187(SNOA401) foradditionalinformationon WQFN packages. POWER SUPPLY BYPASSING Two approachesarerecommended toensurethattheDS64EV400 isprovidedwithan adequatepower supply. First,thesupply(VDD )and ground(GND) pinsshouldbe connectedtopower planesroutedon adjacentlayersof the printedcircuitboard.The layerthicknessof the dielectricshouldbe minimizedso thatthe VDD and GND planes createa low inductancesupply with distributedcapacitance.Second, carefulattentionto supply bypassingthroughthe properuse of bypass capacitorsis required.A 0.01μF bypass capacitorshould be connectedtoeach VDD pinsuch thatthecapacitorisplacedas closeas possibletotheDS64EV400. Smaller body size capacitorscan help facilitateproper component placement.Additionally,three capacitorswith capacitanceintherange of2.2μF to10 μF shouldbe incorporatedinthepower supplybypassingdesignas well.These capacitorscan be eithertantalumor an ultra-lowESR ceramicand shouldbe placedas closeas possibletotheDS64EV400. DC COUPLING The DS64EV400 supportsbothAC couplingwithexternalac couplingcapacitor,and DC couplingtoitsupstream driver,ordownstream receiver.WithDC coupling,usersmust ensuretheinputsignalcommon mode iswithinthe rangeoftheelectricalspecificationVICMDC and thedeviceoutputisterminatedwith50 Ω toVDD .When power-up and power-down thedevice,boththeDS64EV400 and thedownstream receivershouldbe power-upand power- down together.ThisistoavoidtheinternalESD structuresattheoutputoftheDS64EV400 atpower-down from beingturnedon by thedownstream receiver. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS64EV400

SNLS281H –AUGUST 2007–REVISED APRIL 2013 www.ti.com TypicalPerformance Eye Diagrams and Curves Figure11.EqualizedSignal Figure12.EqualizedSignal (40InFR4, 2.5Gbps,PRBS7, 0x07 Setting) (40InFR4, 5Gbps, PRBS7, 0x07 Setting) Figure13. EqualizedSignal Figure14. EqualizedSignal (40InFR4, 6.4Gbps, PRBS7, 0x06 Setting) (40InFR4, 6.4Gbps, PRBS31, 0x06 Setting) Figure15.EqualizedSignal Figure16.EqualizedSignal (30InFR4, 10 Gbps, PRBS7, 0x06 Setting) (10m 24 AWG Twin-Ax Cable,6.4Gbps, PRBS7, 0x07 Setting)

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www.ti.com SNLS281H –AUGUST 2007–REVISED APRIL 2013 TypicalPerformance Eye Diagrams and Curves (continued) Figure17.EqualizedSignal Figure18.DJ vs.EQ Setting(10Gbps) (32InTyco XAUI Backplane,6.25Gbps, PRBS7, 0x06 Setting) Figure19.DJ vs EQ Setting(6.4Gbps) Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS64EV400

SNLS281H –AUGUST 2007–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionG (April2013)toRevisionH Page

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www.ti.com 8-Oct-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS64EV400SQ/NOPB ACTIVE WQFN NJU 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 DS64EV400 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 8-Oct-2015 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS64EV400SQ/NOPB WQFN NJU 48 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 2

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