DS64EV100_08 NSC | Alldatasheet

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Technical content

Features

■ Equalizes up to 24 dB loss at 10 Gbps ■ Equalizes up to 22 dB loss at 6.4 Gbps ■ 8 levels of programmable equalization ■ Operates up to 10 Gbps with 30” FR4 traces ■ Operates up to 6.4 Gbps with 40” FR4 traces ■ 0.175 UI residual deterministic jitter at 6.4 Gbps with 40” FR4 traces ■ Single 2.5V or 3.3V power supply ■ Supports AC or DC-Coupling with wide input common- mode ■ Low power consumption: 100 mW Typ at 2.5V ■ Small 3 mm x 4 mm 14-pin LLP package ■ > 8 kV HBM ESD Rating ■ -40 to 85°C operating temperature range Simplified Application Diagram 20196401 © 2008 National Semiconductor Corporation 201964 www.national.com DS64EV100 Programmable Single Equalizer

14-Pin LLP Package (3 mm x 4 mm x 0.8 mm, 0.5 mm pitch) See NS Package Number SQA14A

Ordering Information

DS64EV100SD 14–pin LLP (3 mm x 4 mm x 0.8 mm, 0.5 mm pitch, reel of 1000 SDA14A DS64EV100SDX 14–pin LLP (3 mm x 4 mm x 0.8 mm, 0.5 mm pitch, reel of 4500 SDA14A Pin Descriptions Pin Name Pin # I/O, Type Description HIGH SPEED DIFFERENTIAL I/O IN+ IN− I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating resistor is connected between IN+ and IN-. Refer to Figure 4. OUT+ OUT− O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω terminating resistor connects OUT+ to VDD and OUT- to VDD. EQUALIZATION CONTROL BST_2 BST_1 BST_0 I, CMOS BST_2, BST_1, and BST_0 select the equalizer strength. BST_2 is internally pulled high. BST_1 and BST_0 are internally pulled low. POWER VDD 5 I, Power VDD = 2.5V ±5% or 3.3V ±10%. VDD pins should be tied to VDD plane through low inductance path. A 0.01μF bypass capacitor should be connected between each VDD pin to GND planes. GND 2, 6, 9, 10, I, Power Ground reference. GND should be tied to a solid ground plane through a low impedance path. DAP PAD I, Power Ground reference. The exposed pad at the center of the package must be connected to ground plane of the board. OTHER NC 1 Reserved. Do not connect. Note: I = Input, O = Output www.national.com 2 DS64EV100

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. If Military/Aerospace specified devices are required, please contact the National Semiconductor sales offices/ distributors for availability and specifications. Supply Voltage (VDD) −0.5V to +4V CMOS Input Voltage −0.5V to +4.0V CMOS Output Voltage −0.5V to +4.0V CML Input/Output Voltage −0.5V to +4.0V Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature Soldering, 4 sec +260°C ESD Rating HBM, 1.5 k Ω, 100 pF > 8 kV EIAJ, 0 Ω, 200 pF > 250 V Thermal Resistance, θJA, No Airflow 40 °C/W Recommended Operating Conditions Min Typ Max Units Supply Voltage (Note 9) V DD2.5 to GND 2.375 2.5 2.625 V V DD3.3 to GND 3.0 3.3 3.6 V Ambient Temperature −40 25 +85 °C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless other specified. (Notes 2, 3) Symbol Parameter Conditions Min Typ (Note 2) Max Units POWER P Power Supply Consumption VDD3.3 140 200 mW VDD2.5 100 150 mW N Supply Noise Tolerance (Note 4)

50 Hz – 100 Hz

100 Hz – 10 MHz

10 MHz – 1.6 GHz 100 mVP-P mVP-P mVP-P LVTTL DC SPECIFICATIONS VIH High Level Input Voltage VDD2.5 1.6 VDD2.5 V VDD3.3 2.0 VDD3.3 V VIL Low Level Input Voltage −0.3 0.8 V VOH High Level Output Voltage IOH = –3 mA, VDD3.3 2.4 V IOH = –3 mA, VDD2.5 2.0 V VOL Low Level Output Voltage IOL = 3 mA 0.4 V IIN Input Current VIN = VDD +1.8 +15 µA VIN = GND −15 0 µA IIN-P Input Leakage Current with Internal Pull-Down/Up Resistors VIN = GND, with internal pull-down resistors +95 µA VIN = GND, with internal pull-up resistors –20 µA CML RECEIVER INPUTS (IN+, IN−) VTX Source Transmit Launch Signal Level (IN diff) AC-Coupled or DC-Coupled Requirement, Differential measurement at point A. (Figure 1) 400 1600 mVP-P VINTRE Input Threshold Voltage Differential measurement at point B . (Figure 1) 120 mVP-P VDDTX Supply Voltage of Transmitter to EQ DC-Coupled Requirement 1.6 VDD V VICMDC Input Common-Mode Voltage DC-Coupled Requirement Differential measurement at point A. (Figure 1), (Note 7) VDDTX-0.8 VDDTX-0.2 V 3 www.national.com DS64EV100

Symbol Parameter Conditions Min Typ (Note 2) Max Units RLI Differential Input Return Loss 100 MHz – 3.2 GHz, with fixture’s effect de- embedded 10 dB RIN Input Resistance Differential Across IN+ and IN-. (Figure 4) 85 100 115 Ω CML OUTPUTS (OUT+, OUT−) VOD Output Differential Voltage Level (OUT diff) Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled (Figure 2) 550 620 725 mVP-P VOCM Output Common- Mode Voltage Single-ended measurement DC-Coupled with 50Ω terminations (Note 7) VDD-0.2 VDD-0.1 V tR, tF Transition Time 20% to 80% of differential output voltage, measured within 1” from output pins. (Figure 2) (Note 7) 20 60 ps RO Output Resistance Single-ended to VDD 42 50 58 Ω RLO Differential Output Return Loss 100 MHz – 1.6 GHz, with fixture’s effect de- embedded. IN+ = static high. 10 dB tPLHD Differential Low to High Propagation Delay Propagation delay measurement at 50% VOD between input to output, 100 Mbps (Figure 3), (Note 7) 240 ps tPHLD Differential High to Low Propagation Delay 240 ps EQUALIZATION DJ1 Residual Deterministic Jitter at

10 Gbps

30” of 6 mil microstrip FR4, EQ Setting 0x06, PRBS-7 (27-1) pattern (Note 5, 6)

0.20 UIP-P

6.4 Gbps

40” of 6 mil microstrip FR4, EQ Setting 0x06, PRBS-7 (27-1) pattern (Note 5, 6) 0.17 0.26 UIP-P DJ3 Residual Deterministic Jitter at

5 Gbps

40” of 6 mil microstrip FR4, EQ Setting 0x07, PRBS-7 (27-1) pattern (Note 5, 6) 0.12 0.20 UIP-P DJ4 Residual Deterministic Jitter at

2.5 Gbps

40” of 6 mil microstrip FR4, EQ Setting 0x07, PRBS-7 (27-1) pattern (Note 5, 6) 0.10 0.16 UIP-P RJ Random Jitter (Note 7, 8) 0.5 psrms Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of –40°C to +125°C. Models are validated to Maximum Operating Voltages only. Note 2: Typical values represent most likely parametric norms at VDD = 3.3V or 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 4: Allowed supply noise (mVP-P sine wave) under typical conditions. Note 5: Specification is guaranteed by characterization at optimal boost setting and is not tested in production. Note 6: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1). Random jitter is removed through the use of averaging or similar means. Note 7: Measured with clock-like {11111 00000} pattern. Note 8: Random jitter contributed by the equalizer is defined as sqrt (JOUT2 – JIN2). JOUT is the random jitter at equalizer outputs in psrms, see point C of Figure 1; JIN is the random jitter at the input of the equalizer in psrms, see Figure 1. www.national.com 4 DS64EV100

operation up to 10 Gbps for backplane and cable applications. FIGURE 5. Simplified Block Diagram range of media loss and data rates. TABLE 1. EQ Boost Control Table

24 AWG

3.2 GHz

tips to address signal integrity design issues. placed symmetrically for each side of a given differential pair. tional information on LLP packages. DS64EV100 is provided with an adequate power supply. capacitor is placed as close as possible to the DS64EV100. should be placed as close as possible to the DS64EV100.

Physical Dimensions inches (millimeters) unless otherwise noted 14-Pin Leadless LLP Package (3 mm x 4 mm x 0.8 mm, 0.5 mm pitch) Order Number DS64EV100SD 9 www.national.com DS64EV100

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