DS64EV100

DS64EV100_14 TI1 | Alldatasheet

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www.ti.com SNLS232D –OCTOBER 2007–REVISED APRIL 2008 DS64EV100ProgrammableSingleEqualizer Check forSamples: DS64EV100 1FEATURES • Single2.5Vor 3.3Vpower supply

• Supports AC or DC-Coupling withwide input 2• Equalizesup to24 dB lossat10 Gbps common-mode• Equalizesup to22 dB lossat6.4Gbps
• Low power consumption: 100 mW Typ at2.5V• 8 levelsofprogrammable equalization
• Small 3 mm x 4 mm 14-pinLLP package• Operates up to10 Gbps with30” FR4 traces
• > 8 kV HBM ESD Rating• Operates up to6.4Gbps with40” FR4 traces
• -40to85°C operatingtemperaturerange• 0.175UI residualdeterministicjitterat6.4 Gbps with40” FR4 traces

DESCRIPTION

The DS64EV100 programmable equalizerprovidescompensationfortransmissionmedium lossesand reduces themedium-induceddeterministicjitterforNRZ datachannel.The DS64EV100 isoptimizedforoperationup to 10 Gbps forbothcablesand FR4 traces.The equalizerchannelhas eightlevelsofinputequalizationthatcan be programmed by threecontrolpins. The equalizersupportsbothAC and DC-coupleddatapathsforlongrunlengthdatapatternssuch as PRBS-31, and balancedcodes such as 8b/10b.The deviceuses differentialcurrent-modelogic(CML) inputsand outputs. The DS64EV100 isavailableina 3 mm x 4 mm 14-pinleadlessLLP package.Power issuppliedfrom eithera 2.5Vor3.3Vsupply. SimplifiedApplicationDiagram Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2007–2008,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

BST_1 NC BST_2 GND OUT_+ OUT_- GND GND BST_0 DS64EV100 TOP VIEW DAP = GND DS64EV100 SNLS232D –OCTOBER 2007–REVISED APRIL 2008 www.ti.com Pin Diagram Figure1. 14-PinLLP Package (3mm x 4 mm x 0.8mm, 0.5mm pitch) Pin Functions Pin Descriptions I/O,Pin Name Pin # DescriptionType HIGH SPEED DIFFERENTIAL I/O IN+ 3 I,CML Invertingand non-invertingCML differentialinputstotheequalizer.An on-chip100Ω terminating IN− 4 resistorisconnectedbetween IN+ and IN-.RefertoFigure4. OUT+ 12 O, CML Invertingand non-invertingCML differentialoutputsfromtheequalizer.An on-chip50Ω OUT − 11 terminatingresistorconnectsOUT+ toVDD and OUT- toVDD . EQUALIZATION CONTROL BST_2 14 I,CMOS BST_2, BST_1, and BST_0 selecttheequalizerstrength.BST_2 isinternallypulledhigh.BST_1 BST_1 7 and BST_0 areinternallypulledlow. BST_0 8 POWER VDD 5 I,Power VDD = 2.5V±5% or3.3V±10%. VDD pinsshouldbe tiedtoVDD planethroughlowinductance path.A 0.01μF bypasscapacitorshouldbe connectedbetween each VDD pintoGND planes. GND 2,6,9,10, I,Power Ground reference.GND shouldbe tiedtoa solidgroundplanethrougha lowimpedance path. DAP PAD I,Power Ground reference.The exposed pad atthecenterofthepackage must be connectedtoground planeoftheboard. OTHER NC 1 Reserved.Do notconnect. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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www.ti.com SNLS232D –OCTOBER 2007–REVISED APRIL 2008 AbsoluteMaximum Ratings (1) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheNationalSemiconductor sales offices/distributorsforavailabilityand specifications. SupplyVoltage(VDD ) −0.5Vto+4V CMOS InputVoltage −0.5Vto+4.0V CMOS OutputVoltage −0.5Vto+4.0V CML Input/OutputVoltage −0.5Vto+4.0V JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature Soldering,4 sec +260°C ESD Rating HBM, 1.5kΩ,100 pF > 8 kV EIAJ,0Ω,200 pF > 250 V ThermalResistance,θJA, No Airflow 40 °C/W (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions.Absolute Maximum Numbers areguaranteedfora junctiontemperaturerangeof–40°C to+125°C. Models arevalidatedtoMaximum Operating Voltagesonly. Recommended OperatingConditions Min Typ Max Units SupplyVoltage(Note9) VDD2.5 toGND 2.375 2.5 2.625 V VDD3.3 toGND 3.0 3.3 3.6 V AmbientTemperature −40 25 +85 °C ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherspecified.(1)(2) TypSymbol Parameter Conditions Min Max Units(1) POWER P Power Supply VDD3.3 140 200 mWConsumption VDD2.5 100 150 mW N SupplyNoise 50 Hz – 100 Hz 100 mV P-P Tolerance(2) 100 Hz – 10 MHz 40 mV P-P 10 MHz – 1.6GHz 10 mV P-P LVTTL DC SPECIFICATIONS VIH HighLevelInput VDD2.5 1.6 VDD2.5 V Voltage VDD3.3 2.0 VDD3.3 V VIL Low LevelInput −0.3 0.8 VVoltage (1) Typicalvaluesrepresentmost likelyparametricnorms atVDD = 3.3Vor2.5V,TA = 25°C.,and attheRecommended Operation Conditionsatthetimeofproductcharacterizationand arenotguaranteed. (2) The ElectricalCharacteristicstableslistguaranteedspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotguaranteed. (1) Typicalvaluesrepresentmost likelyparametricnorms atVDD = 3.3Vor2.5V,TA = 25°C.,and attheRecommended Operation Conditionsatthetimeofproductcharacterizationand arenotguaranteed. (2) Allowedsupplynoise(mV P-P sinewave) undertypicalconditions. Copyright© 2007–2008,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS64EV100

SNLS232D –OCTOBER 2007–REVISED APRIL 2008 www.ti.com TypSymbol Parameter Conditions Min Max Units(1) VOH HighLevelOutput IOH = –3 mA, VDD3.3 2.4 V Voltage IOH = –3 mA, VDD2.5 2.0 V VOL Low LevelOutput IOL = 3 mA 0.4 VVoltage IIN InputCurrent VIN = VDD +1.8 +15 µA VIN = GND −15 0 µA IIN-P InputLeakage VIN = GND, withinternalpull-downresistors +95 µA CurrentwithInternal VIN = GND, withinternalpull-upresistorsPull-Down/Up –20 µA Resistors CML RECEIVER INPUTS (IN+,IN−) VTX SourceTransmit AC-Coupled orDC-Coupled Requirement, Launch SignalLevel Differentialmeasurement atpointA. 400 1600 mV P-P (INdiff) (Figure1) VINTRE InputThreshold Differentialmeasurement atpointB . 120 mV P-PVoltage (Figure1) VDDTX SupplyVoltageof DC-Coupled Requirement 1.6 VDD VTransmittertoEQ VICMDC InputCommon-Mode DC-Coupled RequirementDifferential Voltage measurement atpointA. VDDTX -0.8 VDDTX -0.2 V (Figure1),(Note7) R LI DifferentialInput 100 MHz – 3.2GHz, withfixture’s effectde- 10 dBReturnLoss embedded R IN InputResistance DifferentialAcrossIN+ and IN-.(Figure4) 85 100 115 Ω CML OUTPUTS (OUT+, OUT −) VOD OutputDifferential Differentialmeasurement withOUT+ and OUT- VoltageLevel(OUT terminatedby 50Ω toGND, AC-Coupled 550 620 725 mV P-P diff) (Figure2) VOCM OutputCommon- Single-endedmeasurement DC-Coupled with Mode Voltage 50Ω terminations VDD -0.2 VDD -0.1 V (Note7) tR ,tF TransitionTime 20% to80% ofdifferentialoutputvoltage, measured within1”fromoutputpins. 20 60 ps(Figure2) (Note7) R O OutputResistance Single-endedtoVDD 42 50 58 Ω R LO DifferentialOutput 100 MHz – 1.6GHz, withfixture’s effectde- 10 dBReturnLoss embedded. IN+ = statichigh. tPLHD DifferentialLow to Propagationdelaymeasurement at50% VOD HighPropagation between inputtooutput,100 Mbps 240 ps Delay (Figure3),(Note7) tPHLD DifferentialHighto Low Propagation 240 ps Delay EQUALIZATION DJ1 Residual 30”of6 milmicrostripFR4, EQ Setting0x06, DeterministicJitterat PRBS-7 (27-1)pattern 0.20 UIP-P

10 Gbps (Note5,6)

DJ2 Residual 40”of6 milmicrostripFR4, EQ Setting0x06, DeterministicJitterat PRBS-7 (27-1)pattern 0.17 0.26 UIP-P 6.4Gbps (Note5,6) DJ3 Residual 40”of6 milmicrostripFR4, EQ Setting0x07, DeterministicJitterat PRBS-7 (27-1)pattern 0.12 0.20 UIP-P

5 Gbps (Note5,6)

DJ4 Residual 40”of6 milmicrostripFR4, EQ Setting0x07, DeterministicJitterat PRBS-7 (27-1)pattern 0.10 0.16 UIP-P 2.5Gbps (Note5,6) RJ Random Jitter (Note7,8) 0.5 psrms

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20% 80% 80% 20% OUT diff = (OUT+) ± (OUT-) tFtR DS64EV100 INPUT OUTPUT 6 mils Trace Width, FR4 Microstrip Test Channel SMA Connector SMA Connector Signal Source A B C DS64EV100 www.ti.com SNLS232D –OCTOBER 2007–REVISED APRIL 2008 Timing Diagrams Figure2. TestSetup Diagram Figure3. CML Output TransitionTimes Figure4. PropagationDelay Timing Diagram Figure5. SimplifiedReceiverInputTerminationCircuit DS64EV100 ApplicationsInformation The DS64EV100 isa programmable equalizeroptimizedforoperationup to10 Gbps forbackplaneand cable applications.The equalizerchannelconsistsof an equalizerstage,a limitingamplifier,a DC offsetcorrection block,and a CML driveras shown inFigure5. Copyright© 2007–2008,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS64EV100

Termination Equalizer Limiting Amplifier DC Offset Correction 3 3 BST_0 : BST_2 BST CNTL OUT OUT IN+ -IN DS64EV100 SNLS232D –OCTOBER 2007–REVISED APRIL 2008 www.ti.com Figure6. SimplifiedBlock Diagram EQUALIZER BOOST CONTROL The equalizerchannelsupportseightprogrammablelevelsofequalizationboost,and iscontrolledby theBoost Set pins(BST_[2:0])inaccordancewithTable1.The eightlevelsofboostsettingsenablestheDS64EV100 to addressa widerangeofmedia lossand datarates. Table1. EQ Boost ControlTable 6 milMicrostripFR4 24 AWG Twin-AX Cable Channel Loss at3.2GHz Channel Loss at5 GHz BST_N Trace Length (in) Length (m) (db) (dB) [2,1,0] 0 0 0 0 0 0 0 5 2 5 6 0 0 1 10 3 7.5 10 0 1 0 15 4 10 14 0 1 1 20 5 12.5 18 1 0 0 (Default) 25 6 15 21 1 0 1 30 7 17 24 1 1 0 40 10 22 30 1 1 1 GENERAL RECOMMENDATIONS The DS64EV100 isa high performancecircuitcapableof deliveringexcellentperformance.Carefulattention must be paidtothedetailsassociatedwithhigh-speeddesignas wellas providinga cleanpower supply.Refer totheLVDS Owner ’s Manual formore detailedinformationon high-speeddesigntipstoaddresssignalintegrity designissues. PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS The CML inputsand outputsmust have a controlleddifferentialimpedance of100Ω.ItispreferabletorouteCML linesexclusivelyon one layeroftheboard,particularlyfortheinputtraces.The use ofviasshouldbe avoidedif possible.Ifviasmust be used,theyshouldbe used sparinglyand must be placedsymmetricallyforeach sideof a givendifferentialpair.Route theCML signalsaway fromothersignalsand noisesourceson theprintedcircuit board.See AN-1187 foradditionalinformationon LLP packages. POWER SUPPLY BYPASSING Two approachesarerecommended toensurethattheDS64EV100 isprovidedwithan adequatepower supply. First,thesupply(VDD )and ground(GND) pinsshouldbe connectedtopower planesroutedon adjacentlayersof the printedcircuitboard.The layerthicknessof the dielectricshouldbe minimizedso thatthe VDD and GND planes createa low inductancesupply with distributedcapacitance.Second, carefulattentionto supply bypassingthroughthe properuse of bypass capacitorsis required.A 0.01μF bypass capacitorshould be connectedtoeach VDD pinsuch thatthecapacitorisplacedas closeas possibletotheDS64EV100. Smaller body size capacitorscan help facilitateproper component placement.Additionally,three capacitorswith capacitanceintherange of2.2μF to10 μF shouldbe incorporatedinthepower supplybypassingdesignas well.These capacitorscan be eithertantalumor an ultra-lowESR ceramicand shouldbe placedas closeas possibletotheDS64EV100.

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www.ti.com SNLS232D –OCTOBER 2007–REVISED APRIL 2008 DC COUPLING The DS64EV100 supportsbothAC couplingwithexternalac couplingcapacitor,and DC couplingtoitsupstream driver,ordownstream receiver.WithDC coupling,usersmust ensuretheinputsignalcommon mode iswithinthe rangeoftheelectricalspecificationVICMDC and thedeviceoutputisterminatedwith50 Ω toVDD . Copyright© 2007–2008,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS64EV100

SNLS232D –OCTOBER 2007–REVISED APRIL 2008 www.ti.com TypicalPerformance Eye Diagrams and Curves Figure7.EqualizedSignal Figure8.EqualizedSignal (40inFR4, 2.5Gbps, PRBS7, 0x07 Setting) (40inFR4, 5 Gbps, PRBS7, 0x07 Setting) Figure9.EqualizedSignal Figure10.EqualizedSignal (40inFR4, 6.4Gbps, PRBS7, 0x06 Setting) (40inFR4, 6.4Gbps, PRBS31, 0x06 Setting) Figure11.EqualizedSignal Figure12.EqualizedSignal (30inFR4, 10 Gbps, PRBS7, 0x06 Setting) (10m 24 AWG Twin-AX Cable,6.4Gbps, PRBS7, 0x06 Setting)

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001 010 011 100 101 110 111 EQ SETTING (BST_2, BST_1, BST_0) 0.1 0.2 0.3 0.4 0.5 DJ (UI) 000 40 in 30 in 20 in 10 in 6 in DS64EV100 www.ti.com SNLS232D –OCTOBER 2007–REVISED APRIL 2008 TypicalPerformance Eye Diagrams and Curves (continued) Figure13.EqualizedSignal Figure14.DJ vs.EQ Setting(6.4Gbps) (32inTyco XAUI Backplane,6.25Gbps, PRBS7, 0x06 Setting) Figure15.DJ vs.EQ Setting(10Gbps) Copyright© 2007–2008,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS64EV100

www.ti.com 17-Nov-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Samples (Requires Login) DS64EV100SD/NOPB ACTIVE WSON NHK 14 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM DS64EV100SDX/NOPB ACTIVE WSON NHK 14 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS64EV100SD/NOPB WSON NHK 14 1000 203.0 190.0 41.0 DS64EV100SDX/NOPB WSON NHK 14 4500 349.0 337.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 Pack Materials-Page 2

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