DS64BR401SQ/NOPB

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www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013 DS64BR401QuadBi-DirectionalRepeaterwithEqualizationand De-Emphasis Check forSamples: DS64BR401 1FEATURES DESCRIPTION The DS64BR401 isa quad lanebi-directionalsignal 2• Quad lanebi-directionalrepeaterup to6.4 extended reach equalizationand transmitde-emphasison each ofits 8 channelstocompensate forchannelloss,allowing• Adjustablereceiveequalizationup to+33 dB maximum flexibilityof physicalplacement withinagain system. The receiver'scontinuous time linear• Adjustabletransmitde-emphasis up to−12 dB equalizer(CTLE) providesa boostofup to+33 dB at

AdjustabletransmitVOD (600mVp-p to1200 3 GHz and iscapableofopeningan inputeye thatis mVp-p) completelyclosed due to inter-symbolinterference (ISI)induced by the interconnectmedium. The• <0.25UI ofresidualDJ at6.4Gbps with40” transmitterfeaturesa programmable output de-FR4 trace emphasis driverand allowsamplitudevoltagelevels• Automatic de-emphasis scalingbased on rate tobe selectedfrom600 mVp-p to1200 mVp-p tosuitdetect multipleapplicationscenarios.This Low Power
SATA/SAS: OOB signalpass-through, DifferentialSignaling(LPDS) outputdriverisa power efficientimplementationthatmaintainscompatibility– <3 ns (typ)envelope distortion withAC coupled CML receiver.The programmable• AdjustableelectricalIDLE detectthreshold settingscan be appliedvia pin settingsor SMBus
Low power (100mW/channel),per-channel interface. power down To enable seamless upgrade from SAS/SATA 3.0
Programmable viapinselectionor SMBus Gbps to 6.0 Gbps data rateswithoutcompromising interface physicalreach,DS64BR401 automaticallydetectsthe incoming data rate and selectsthe optimalde-• Singlesupply operationat2.5V±5% emphasis pulsewidth.The devicedetectstheout-of-• >6 kV HBM ESD Rating band (OOB) idleand activesignalsoftheSAS/SATA
3.3VLVCMOS inputtolerantforSMBus specificationand passesthroughwithminimum signal interface distortion.
High speed signalflow–thrupinoutpackage: With a typicalpower consumptionof 200 mW/lane54-pinWQFN (10mm x 5.5mm) (100mW/channel)at6.4Gbps, and controltoturn-off unused channels,the DS64BR401 ispartof Texas APPLICATIONS Instruments'PowerWise familyof energy efficient devices.• SATA (1.5,3.0and 6 Gbps)
SAS (1.5,3.0and 6 Gbps)
XAUI (3.125Gbps),RXAUI (6.25Gbps)
sRIO – SerialRapid I/O
FibreChannel (4.25Gbps)
10GBase-CX4, InfiniBand4x (SDR & DDR)
QSFP activecopper cablemodules
High-speed activecableand FR-4 backplane traces Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

Cs > 10 nF Cs > 10 nF SATA/SAS Host Controller SATA/SAS Disk Drives Interconnect Cable DS64BR401 Slice 1 of 4 DS64BR401 Slice 1 of 4 Cs > 10 nF Cs > 10 nF DS64BR401 SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com TYPICAL CABLE APPLICATION TYPICAL APPLICATION CONNECTION DIAGRAM

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OB_0+ OB_0- OB_1+ VOD1 VOD0 SD_TH TOP VIEW DAP = GND OB_1- OB_2+ OB_2- IA_3- IA_0+ IA_0- VDD IA_1+ IA_1- EQA0 IA_2+ IA_2- IA_3+ OA_1+ OA_1- EQA1 OA_2+ OA_2- OA_3+ OA_3- TXIDLEA TXIDLEB IB_3+ IB_3- VDD RATE OA_0+ OA_0- IB_0+ IB_0- IB_1+ IB_1- IB_2- IB_2+ VDD DEMA1/SCL50 DEMA0/SDA ENSMB OB_3+ OB_3- SMBUS AND CONTROL DEMB1/AD0 DEMB0/AD1 NC EQB1/AD2 EQB0/AD3 PWDN VDD VDD Ix_n+ Ix_n- EQ RATE DET LIMITER IDLE DET OUTBUF SMBus VOD/DE-EMPHASIS CONTROLVDD SMBus TX Idle Enable SMBus DEMA/B EQA/B Ox_n+ Ox_n- TXIDLEx DS64BR401 www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013 BLOCK DIAGRAM -DETAIL VIEW OF THE EACH CHANNEL (1OF 8) PIN DIAGRAM Figure1. DS64BR401 Pin Diagram 54L WQFN Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com Table1.PIN DESCRIPTIONS Pin Name Pin Number I/O,Type Pin Descriptions DifferentialHigh Speed I/O's IA_0+,IA_0-, 10,11 I,CML Invertingand non-invertingCML differentialinputstotheequalizer.A IA_1+,IA_1-, 12,13 gatedon-chip50Ω terminationresistorconnectsINA_n+ toVDD and IA_2+,IA_2-, 15,16 INA_n-toVDD when enabled. IA_3+,IA_3- 17,18 OA_0+, OA_0-, 35,34 O, LPDS Invertingand non-invertinglowpower differentialsignaling(LPDS) 50Ω OA_1+, OA_1-, 33,32 outputswithde-emphasis.CompatiblewithAC coupledCML inputs. OA_3+, OA_3- 29,28 IB_0+,IB_0-, 45,44 I,CML Invertingand non-invertingCML differentialinputstotheequalizer.A IB_1+,IB_1-, 43,42 gatedon-chip50Ω terminationresistorconnectsINB_n+ toVDD and IB_2+,IB_2-, 40,39 INB_n-toVDD when enabled. IB_3+,IB_3- 38,37 OB_0+, OB_0-, 1,2 O, LPDS Invertingand non-invertinglowpower differentialsignaling(LPDS) 50Ω OB_1+, OB_1-, 3,4 outputswithde-emphasis.CompatiblewithAC coupledCML inputs. OB_2+, OB_2-, 5,6 OB_3+, OB_3- 7,8 ControlPins — Shared (LVCMOS) ENSMB 48 I,LVCMOS w/ System Management Bus (SMBus) enablepin. internalpull- When pulledhighprovideaccessinternaldigitalregistersthatarea down means ofauxiliarycontrolforsuch functionsas equalization,de- emphasis,VOD, rate,and idledetectionthreshold. When pulledlow,accesstotheSMBus registersaredisabledand SMBus functionpinsareused tocontroltheEqualizerand De-Emphasis. PleaserefertoSYSTEM MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS sectionand ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE for detailinformation. ENSMB = 1 (SMBUS MODE) SCL 50 I,LVCMOS ENSMB = 1 SMBUS clockinputpinisenabled.Externalpull-upresistormaybe needed.RefertoR TERM intheSMBus specification. SDA 49 I,LVCMOS ENSMB = 1 O, Open Drain The SMBus bi-directionalSDA pinisenabled.Data inputoropen drain output.Externalpull-upresistorisrequired. RefertoR TERM intheSMBus specification. AD0 –AD3 54,53,47,46 I,LVCMOS w/ ENSMB = 1 internalpull- SMBus SlaveAddressInputs.InSMBus mode, thesepinsaretheuser down setSMBus slaveaddressinputs.See section— SYSTEM MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS foradditionalinformation. ENSMB = 0 (NORMAL PIN MODE) EQA0, EQA1 20,19 I,Float, EQA/B, 3–levelcontrolsthelevelofequalizationoftheA/B sides.The EQB0, EQB1 46,47 LVCMOS EQA/B pinsareactiveonlywhen ENSMB isde-asserted(Low).Each of the4 A/B channelshave thesame levelunlesscontrolledby theSMBus controlregisters.When ENSMB goes hightheSMBus registersprovide independentcontrolofeach lane.See Table2,Table3,Table4 DEMA0, DEMA1 49,50 I,Float, DEMA/B, 3–levelcontrolsthelevelofde-emphasisoftheA/B sides.The DEMB0, DEMB1 53,54 LVCMOS DEMA/B pinsareonlyactivewhen ENSMB isde-asserted(Low).Each ofthe4 A/B channelshave thesame levelunlesscontrolledby the SMBus controlregisters.When ENSMB goes HightheSMBus registers provideindependentcontrolofeach lane.See Table5 ControlPins — Both Modes (LVCMOS) RATE 21 I,Float, RATE, 3–levelcontrolsthepulsewidthofde-emphasisoftheoutput. LVCMOS RATE = 0 forces3 Gbps, RATE = 1 forces6 Gbps, RATE = Floatenablesautoratedetectionand thepulsewidth(pull-back) issetappropriatelyaftereach exitfromIDLE.Thisrequiresthetransition fromIDLE toACTIVE state— OOB signal.See Table5

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www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013 Table1.PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O,Type Pin Descriptions TXIDLEA,TXIDLEB 24,25 I,Float, TXIDLEA/B,3–levelcontrolsthedriveroutput. LVCMOS TXIDLEA/B = 0 disablesthesignaldetect/squelchfunctionforallA/B outputs. TXIDLEA/B = 1 forcestheoutputstobe muted (electricalidle). TXIDLEA/B = Floatenablesthesignalautodetect/squelchfunctionand thesignaldetectvoltagethresholdlevelcan be adjustedusingthe SD_TH pin.See Table6 VOD0, VOD1 22,23 I,LVCMOS w/ VOD[1:0]adjuststheoutputdifferentialamplitudevoltagelevel. internalpull- VOD[1:0]= 00 setsoutputVOD = 600 mV (Default) down VOD[1:0]= 01 setsoutputVOD = 800 mV VOD[1:0]= 10 setsoutputVOD = 1000 mV VOD[1:0]= 11 setsoutputVOD = 1200 mV PWDN 52 I,LVCMOS PWDN = 0 enablesthedevice(normaloperation). PWDN = 1 disablesthedevice(lowpower mode). Pinmust be driventoa logiclowatalltimesfornormaloperation Analog SD_TH 27 I,ANALOG Thresholdselectpinforelectricalidledetectthreshold.Floatpinfor typicaldefault130 mVp-p (differential),otherwiseconnectresistorfrom SD_TH toGND tosetthresholdvoltage.See Table7,Figure6 Power VDD 9,14,36,41,51 Power Power supplypins.2.5V +/-5% GND DAP Power DAP isthelargemetalcontactatthebottomside,locatedatthecenter ofthe54 pinWQFN package.Itshouldbe connectedtotheGND plane withatleast4 viatolowerthegroundimpedance and improvethe thermalperformanceofthepackage. NC 26 No Connect— Leave pinopen These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1)(2) SupplyVoltage(VDD) -0.5Vto+3.0V LVCMOS Input/OutputVoltage -0.5Vto+4.0V CML InputVoltage -0.5Vto(VDD+0.5V) LPDS OutputVoltage -0.5Vto(VDD+0.5V) Analog(SD_TH) -0.5Vto(VDD+0.5V) JunctionTemperature +125°C StorageTemperature -40°C to+125°C Maximum Package Power Dissipationat25°C DerateNJY Package 52.6mW/°C above +25°C ESD Rating HBM, STD -JESD22-A114C ≥6 kV MM, STD -JESD22-A115-A ≥250 V CDM, STD -JESD22-C101-C ≥1250 V ThermalResistance θJC 11.5°C/W θJA,No Airflow,4 layerJEDEC 19.1°C/W Forsolderingspecifications: See SNOA549 (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions.Absolute Maximum Numbers arespecifiedfora junctiontemperaturerangeof-40°C to+125°C. Models arevalidatedtoMaximum Operating Voltagesonly. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsfor availabilityand specifications. RECOMMENDED OPERATING CONDITIONS Min Typ Max Units SupplyVoltage VDD toGND 2.375 2.5 2.625 V AmbientTemperature -10 25 +85 °C SMBus (SDA, SCL) 0 3.6 V CML DifferentialInputVoltage 0 2.0 Vp-p SupplyNoiseToleranceup to50 MHz, (1) 100 mVp-p (1) Allowedsupplynoise(mV P-P sinewave) undertypicalconditions.

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www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013

ELECTRICAL CHARACTERISTICS

Over recommended operatingsupplyand temperaturerangeswithdefaultregistersettingsunlessotherspecified.(1) Symbol Parameter Conditions Min Typ Max Units POWER PD Power Dissipation PWDN = 0, EQx = 0,DEMx = 0 dB, 758 950 mWK28.5pattern VOD = 1.0Vp-p PWDN = 1,ENSMB = 0 0.92 1.125 mW LVCMOS /LVTTL DC SPECIFICATIONS VIH HighLevelInputVoltage 2.0 3.6 V VIL Low LevelInputVoltage 0 0.8 V IIH InputHighCurrent VIN = 3.3V, -15 +15 μAInputsOPEN: SDA, SCL, PWDN VIN = 3.3V, InputswithPULL-DOWN -15 +120 uA and FLOAT — mid level IIL InputLow Current VIN = 0V, InputsOPEN: SDA, SCL, PWDN and with -15 +15 μA PULL-DOWN VIN = 0V, -80 +15 uAInputswithFLOAT — mid level CML RECEIVER INPUTS (IN_n+,IN_n-) RL RX-DIFF Rx DifferentialReturnLoss 150 MHz – 1.5GHz -20 (SDD11), 150 MHz – 3.0GHz -13.5 dB(2) 150 MHz – 6.0GHz -8 RL RX-CM Rx Common Mode Input 150 MHz – 3.0GHz, (2) -10 dBReturnLoss (SCC11) R RX-IB Rx Impedance Balance 150 MHz – 3.0GHz, (2) -27 dB(SDC11) IIN Maximum currentallowedat −30 +30 mAIN+ orIN-inputpin. R IN InputResistance Singleended toVDD ,(2) 50 Ω R ITD InputDifferentialImpedance DC tested,(2) between 85 100 115 Ω IN+ and IN- R ITIB InputDifferentialImpedance DC tested,(2) 5 ΩImbalance R ICM InputCommon Mode DC tested,(2) 20 25 35 ΩImpedance VRX-DIFF DifferentialRx peak topeak DC voltage, 0.1 1.2 Vvoltage SD_TH = 20 kΩ toGND VRX-SD_TH ElectricalIdledetect SD_TH = Float,(3),Figure6 40 175 mVp-pthreshold(differential) LPDS OUTPUTS (OUT_n+, OUT_n-) VOD OutputVoltageSwing R L = 50 Ω ±1% toGND (AC coupledwith10 nF),6.4Gbps, (4) 500 600 700 mV P-PDEMx = 0 dB, VOD[1:0]= 00 VOD[1:0]= 11 1100 1265 1450 mV P-P (1) The ElectricalCharacteristicstableslistverifiedspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwise modifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenot verified. (2) Typicalvaluesrepresentmost likelyparametricnorms atVDD = 2.5V,TA = 25°C.,and attheRecommended OperationConditionsatthe timeofproductcharacterizationand arenotverified. (3) Measured atpackage pinsofreceiver.The 130 mVp-p isa typicalthresholdleveland does notincludehysteresis,thuslessthan40 mVp-p isIDLE,greaterthan175 mVp-p isACTIVE. SD_TH pinconnectedwithresistortoGND overridesthisdefaultsetting. (4) Measured withclock-like{1111100000}pattern. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operatingsupplyand temperaturerangeswithdefaultregistersettingsunlessotherspecified.(1) Symbol Parameter Conditions Min Typ Max Units VOCM OutputCommon-Mode Single-endedmeasurement DC-Coupled with VDD –Voltage 50Ω termination, V1.4(2) TTX-RF TransmitterRise/FallTime 20% to80% ofdifferentialoutputvoltage, measured within1”fromoutputpins, 67 85 ps (2)(4),Figure2 TRF-DELTA Tx rise/fallmismatch 20% to80% ofdifferentialoutputvoltage,(2)

0.1 UI(4)

RL TX-DIFF Tx DifferentialReturnLoss Repeating1100b (D24.3)pattern, (SDD22), VOD = 1.0Vp-p, -11 (2) 150 MHz – 1.5GHz dB 150 MHz – 3.0GHz -10 150 MHz – 6.0GHz -5 RL TX-CM Tx Common Mode Return Repeating1100b (D24.3)pattern, Loss VOD = 1.0Vp-p,(2) -10 dB (SCC22) 50 MHz – 3.0GHz R TX-IB Tx Impedance Balance Repeating1100b (D24.3)pattern, (SDC22) VOD = 1.0Vp-p,(2) -30 dB 50 MHz – 3.0GHz ITX-SHORT Tx OutputShortCircuit OA/B_n = GND 90 mACurrentLimit R OTD OutputDifferential DC tested,(5) Impedance between OUT+ 85 100 125 Ω and OUT- R OTIB OutputDifferential DC tested,(5) 5 ΩImpedance Imbalance R OCM OutputCommon Mode DC tested,(5) 20 25 35 ΩImpedance VTX-CM-DELTA Common Mode Voltage (6) Deltabetween activeburst ±40 mVand electricalIdleofan OOB signal TDI Max timetotransitionto VIN = 800 mVp-p, repeating1100b (D24.3) validelectricalidleafter patternat3 Gbps, 6.5 9.5 nsleavingactiveburstinOOB SD_TH = Float,Figure4 signaling TID Max timetotransitionto VIN = 800 mVp-p, repeating1100b (D24.3) validactiveburstafter patternat3 Gbps, 5.5 8 nsleavingidleinOOB SD_TH = Float,Figure4 signaling TPD DifferentialPropagation Propagationdelaymeasured atmidpoint Delay(Low toHighand High crossingbetween inputtooutput,Figure3, 150 200 250 ps toLow Edge) EQx[1:0]= 11,DEMx[1:0]= −6 dB EQx[1:0]= OFF, DEMx[1:0]= 0 dB 120 170 220 ps TLSK Lane toLane Skew ina VDD = 2.5V,TA = 25°C 27 psSinglePart TPPSK ParttoPartPropagation VDD = 2.5V,TA = 25°C 35 psDelaySkew EQUALIZATION DJ1 ResidualDeterministicJitterTx Launch Amplitude= 0.8to at6.4Gbps 1.2Vp–p,40”4–milFR4 trace, EQx[1:0]= 0F,DEMx[1:0]= 0 dB, 0.12 0.25 UIP-P VOD = 1.0Vp-p,K28.5, SD_TH = float,(5) (5) Typicalvaluesrepresentmost likelyparametricnorms atVDD = 2.5V,TA = 25°C.,and attheRecommended OperationConditionsatthe timeofproductcharacterizationand arenotverified. (6) Common-mode voltage(VCM) isexpressedmathematicallyas theaverageofthetwo signalvoltageswithrespecttolocalground.VCM = (A + B) /2,A = OUT+, B = OUT-.

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www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) Over recommended operatingsupplyand temperaturerangeswithdefaultregistersettingsunlessotherspecified.(1) Symbol Parameter Conditions Min Typ Max Units DJ2 ResidualDeterministicJitterTx Launch Amplitude= 0.8to at6.4Gbps 1.2Vp–p,12 meters(30AWG), EQx[1:0]= 1F,DEMx[1:0]= 0 dB, 0.05 0.15 UIP-P VOD = 1.0Vp-p,K28.5, SD_TH = float,(5) DJ3 ResidualDeterministicJitterTx Launch Amplitude= 0.8to at3.2Gbps 1.2Vp–p,40”4–milFR4 trace, EQx[1:0]= 0F,DEMx[1:0]= 0 dB, 0.05 0.12 UIP-P VOD = 1.0Vp-p,K28.5, SD_TH = float,(5) DJ4 ResidualDeterministicJitterTx Launch Amplitude= 0.8to at3.2Gbps 1.2Vp–p,12 meters(30AWG), EQx[1:0]= 1F,DEMx[1:0]= 0 dB, 0.06 0.16 UIP-P VOD = 1.0Vp-p,K28.5, SD_TH = float,(5) RJ Random Jitter Tx Launch Amplitude= 0.8to1.2Vp–p, 0.5 psrmsRepeating1100b (D24.3)pattern DE-EMPHASIS DJ5 ResidualDeterministicJitterTx Launch amplitude= 0.8to at6.4Gbps 1.2Vp–p,10”4–milFR4 trace, 0.09 0.20 UIP-PEQx[1:0]= OFF, DEMx[1:0]= −6 dB, VOD = 1.0Vp-p,K28.5,RATE = 1 (5) DJ6 ResidualDeterministicJitterTx Launch amplitude= 0.8to at3.2Gbps 1.2Vp–p,20”4–milFR4 trace, 0.07 0.18 UIP-PEQx[1:0]= OFF, DEMx[1:0]= −6 dB, VOD = 1.0Vp-p,K28.5,RATE = 0 (7) (7) Typicalvaluesrepresentmost likelyparametricnorms atVDD = 2.5V,TA = 25°C.,and attheRecommended OperationConditionsatthe timeofproductcharacterizationand arenotverified. ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ Max Units SERIAL BUS INTERFACE DC SPECIFICATIONS VOL Data (SDA) Low LevelOutput IOL = 3mA 0.4 VVoltage VIL Data (SDA),Clock(SCL)InputLow 0.8 VVoltage VIH Data (SDA),Clock(SCL)InputHigh 2.1 3.6 VVoltage IPULLUP CurrentThroughPull-UpResistor HighPower Specification 4 mAorCurrentSource VDD NominalBus Voltage 2.375 3.6 V ILEAK-Bus InputLeakage Per Bus Segment (1) -200 +200 µA ILEAK-Pin InputLeakage Per DevicePin -15 µA C I CapacitanceforSDA and SCL (1)(2) 10 pF R TERM ExternalTerminationResistance VDD3.3, 2000 ΩpulltoVDD = 2.5V± 5% OR 3.3V± (1)(2)(3) SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure5 FSMB Bus OperatingFrequency (4) 10 100 kHz (1) Recommended value.Parameternottestedinproduction. (2) Recommended maximum capacitanceloadperbus segment is400pF. (3) Maximum terminationvoltageshouldbe identicaltothedevicesupplyvoltage. SMBus common AC specificationsfordetails. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE (continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ Max Units TBUF Bus FreeTime Between Stopand 4.7 µsStartCondition THD:STA Holdtimeafter(Repeated)Start AtIPULLUP ,Max Condition.Afterthisperiod,thefirst 4.0 µs clockisgenerated. TSU:STA Repeated StartConditionSetup 4.7 µsTime TSU:STO StopConditionSetupTime 4.0 µs THD:DAT Data HoldTime 300 ns TSU:DAT Data SetupTime 250 ns TTIMEOUT DetectClockLow Timeout (4) 25 35 ms TLOW ClockLow Period 4.7 µs THIGH ClockHighPeriod (4) 4.0 50 µs TLOW :SEXT CumulativeClockLow ExtendTime (4) 2 ms(SlaveDevice) tF Clock/DataFallTime (4) 300 ns tR Clock/DataRiseTime (4) 1000 ns tPOR Time inwhicha devicemust be (4) 500 msoperationalafterpower-onreset

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tBUF tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA ST SP tSU:STO SCL SDA ST DS64BR401 www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013 TIMING DIAGRAMS Figure2. LPDS Output TransitionTimes Figure3. PropagationDelay Timing Diagram Figure4. IdleTiming Diagram Figure5. SMBus Timing Parameters Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS64BR401 isa quad repeateroptimizedforbackplanetraceor cableinterconnectup to 6.4 Gbps. The DS64BR401 operatesintwo modes: PinControlMode (ENSMB = 0)and SMBus Mode (ENSMB = 1). PinControlMode: When inpinmode (ENSMB = 0),therepeaterisconfigurablewithexternalpins.Equalizationand de-emphasis can be selectedvia pin foreach side independently.When de-emphasisis assertedVOD is automatically increasedper the De-Emphasis tablebelow forimprovedperformanceover lossymedia.Rate optimizationis alsopincontrollable,withpinselectionsfor3 Gbps, 6 Gbps, and autodetect.The receiverelectricalidledetect thresholdisalsoprogrammableviaan optionalexternalresistoron theSD_TH pin. SMBUS MODE When inSMBus mode theequalization,de-emphasisareallprogrammableon a individuallanebasis,insteadof groupedby sidesas inthepinmode case.Upon assertionofENSMB theRATE, EQx and DEMx functionsrevert toregistercontrolimmediately.The EQx and DEMx pinsareconvertedtoAD0-AD3 SMBus addressinputs.The otherexternalcontrolpinsremain activeunlesstheirrespectiveregistersare writtento and the appropriate overridebitisset,inwhichcase theyareignoreduntilENSMB isdrivenlow.On powerup and when ENSMB is drivenlow allregistersareresettotheirdefaultstate.IfPWDN = 1 isassertedwhileENSMB = 1,theregisters retaintheircurrentstate. Equalizationsettingsaccessibleviathe pincontrolswere chosen to meet the needs of most applications.If additionalfinetuningor adjustmentisneeded,additionalequalizationsettingscan be accessed viatheSMBus registers.Each inputhas a totalof24 possibleequalizationsettings.The tablesshow a typicalgainforeach gain stage(GST[4:3])and boostlevel(BST[2:0])combination.When usingSMBus mode, theEqualizationand De- Emphasis levelsaresetusingregisters.See Table9 (registermap) formore information. Table2. EqualizationSettingswithGST=1 forPins or SMBus Registers EQ Setting EQ Gain (dB) EQ1 ( EQ0 ( Suggested UseGST[4 BST[2: 1.5GHz 3.0GHz1) 1) :3] 0] F F 00 000 0 0 Bypass -DefaultSetting 01 000 2.0 3.8 01 001 2.6 4.9 1 1 01 010 3.3 5.8 8 inchFR4 (4-miltrace)or< 0.7m (30AWG) 01 011 3.9 6.8 01 100 4.9 8.2 01 101 5.5 8.9 01 110 6.0 9.4 01 111 6.5 10.0 (1) F=Float(don'tdrivepin,each floatpinhas an internal50K Ohm resistortoVDD and GND), 1=High,0=Low Table3.EqualizationSettingswithGST=2 forPins or SMBus Registers EQ Setting EQ Gain (dB) EQ1 ( EQ0 ( Suggested UseGST[4 BST[2: 1.5GHz 3.0GHz1) 1) :3] 0] 0 0 10 000 4.8 9.2 12”FR4 (4-miltrace)or1m (30AWG) F 0 10 001 6.3 11.7 20”FR4 (4-miltrace)or5m (30AWG) 10 010 7.6 13.6 10 011 9.1 15.6 F 1 10 100 11.1 18.4 35”FR4 (4-miltrace)or9m (30AWG) 0 1 10 101 12.4 20.0 40”FR4 (4-miltrace)or10m (30AWG) 10 110 13.4 20.9 (1) F=Float(don'tdrivepin,each floatpinhas an internal50K Ohm resistortoVDD and GND), 1=High,0=Low

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www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013 Table3.EqualizationSettingswithGST=2 forPins or SMBus Registers(continued) EQ Setting EQ Gain (dB) EQ1 ( EQ0 ( Suggested UseGST[4 BST[2: 1.5GHz 3.0GHz1) 1) :3] 0] 10 111 14.5 22.0 Table4.EqualizationSettingswithGST=3 forPins or SMBus Registers EQ Setting EQ Gain (dB) EQ1 ( EQ0 ( Suggested UseGST[4 BST[2: 1.5GHz 3.0GHz1) 1) :3] 0] 1 0 11 000 7.7 14.6 25”FR4 (4-miltrace)or6m (30AWG) 11 001 10.1 18.4 0 F 11 010 12.2 21.2 10m (30AWG) 11 011 14.4 24.4 1 F 11 100 17.5 28.4 12m (30AWG) 11 101 19.4 30.6 11 110 20.9 32.1 11 111 22.6 33.8 (1) F=Float(don'tdrivepin,each floatpinhas an internal50K Ohm resistortoVDD and GND), 1=High,0=Low Table5.De-Emphasis InputSelectPins forA and B ports(3–LevelInput) RATE DEM1 DEM0 De- DE Pulse(1) (1) Emphasis Width VOD (typical) Suggested UseLevel (typ)(typ) 0/F 0 0 0 dB 0 ps VOD: 600 to1200 mVp-p 10 inchFR4 traceor1 meter(28AWG) 0/F 0 1 -3.5dB 330 ps VOD = 1000 mVp-p 20 inchFR4 traceor2 meters(28AWG) -2dB 330 ps VOD = 1200 mVp-p 15 inchFR4 traceor2 meters(28AWG) 0/F 1 0 -6dB 330 ps VOD = 1000 mVp-p 25 inchFR4 traceor3 meters(28AWG) -3dB 330 ps VOD = 1200 mVp-p 20 inchFR4 traceor2 meters(28AWG) 0/F 1 1 -9dB 300 ps VOD = 1000 mVp-p 5 meters(28AWG) enhanced -11dB 300 ps VOD = 1200 mVp-p 7 meters(28AWG) enhanced 0/F 0 F -6dB 300 ps VOD = 1000 mVp-p 5 meters(26AWG) enhanced -8dB 300 ps VOD = 1200 mVp-p 7 meters(26AWG) enhanced 0/F 1 F -12dB 300 ps VOD = 1000 mVp-p 8 meters(24AWG) enhanced -13dB 300 ps VOD = 1200 mVp-p 9 meters(24AWG) enhanced 0/F F 0 -9dB 250 ps VOD = 1000 + 200 mVp-p 8 meters(26AWG) enhanced -10dB 250 ps VOD = 1200 + 200 mVp-p 9 meters(26AWG) enhanced 0/F F 1 -12dB 250 ps VOD: (1000to1200)+ 200 mVp-p 10 meters(24AWG) enhanced 0/F F F Reserved,don'tuse 1/F 0 0 0 dB 0 ps VOD: 600 to1200 mVp-p 5 inchFR4 traceor0.5meter(28AWG) (1) F = Float(don'tdrivepin),1 = Highand 0 = Low. Enhanced DE pulsewidthprovidesde-empahsison second bit. When RATE = F (autoratedetectionactive),theDE leveland pulsewidthsettingsfollowdetectedrateafterexitingIDLE.RATE = 0 is3 Gbps and RATE = 1 is6 Gbps. De-emphasisshouldonlybe used withVOD = 1000 mVp-p or1200 mVp-p. VOD lessthen1000 mVp-p isnotrecommended withde-emphasis.PleaserefertoVOD1 and VOD0 pindescriptiontosettheoutputdifferentialvoltagelevel. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com Table5.De-Emphasis InputSelectPins forA and B ports(3–LevelInput)(continued) RATE DEM1 DEM0 De- DE Pulse(1) (1) Emphasis Width VOD (typical) Suggested UseLevel (typ)(typ) 1/F 0 1 -3.5dB 200 ps VOD = 1000 mVp-p 10 inchFR4 traceor1 meter(28AWG) -2dB 200 ps VOD = 1200 mVp-p 10 inchFR4 traceor1 meters(28AWG) 1/F 1 0 -6dB 200 ps VOD = 1000 mVp-p 20 inchFR4 traceor2 meters(28AWG) -3dB 200 ps VOD = 1200 mVp-p 15 inchFR4 traceor1 meters(28AWG) 1/F 1 1 -9dB 180 ps VOD = 1000 mVp-p 3 meters(28AWG) enhanced -11dB 180 ps VOD = 1200 mVp-p 4 meters(28AWG) enhanced 1/F 0 F -6dB 180 ps VOD = 1000 mVp-p 3 meters(26AWG) enhanced -8dB 180 ps VOD = 1200 mVp-p 4 meters(26AWG) enhanced 1/F 1 F -12dB 180 ps VOD = 1000 mVp-p 5 meters(24AWG) enhanced -13dB 180 ps VOD = 1200 mVp-p 6 meters(24AWG) enhanced 1/F F 0 -9dB 160 ps VOD = 1000 + 200 mVp-p 5 meters(26AWG) enhanced -10dB 160 ps VOD = 1200 + 200 mVp-p 6 meters(26AWG) enhanced 1/F F 1 -12dB 160 ps VOD: (1000to1200)+ 200 mVp-p 7 meters(24AWG) enhanced 1/F F F Reserved,don'tuse Table6.IdleControl(3–LevelInput) TXIDLEA/B Function

0 Thisstateisforlossymedia,dedicatedIdlethresholddetectcircuitdisabled,

outputfollowsinputbased on EQ settings.Idlestatenotverified. Float Floatenablesautomaticidledetection.Idleon theinputispassed tothe output.Internal50KΩ resistorsholdTXIDLEA/B pinata mid level-don't connectthispiniftheautomaticidledetectfunctionisdesired.Thisisthe defaultstate.OutputinIdleifdifferentialinputsignallessthanvaluesetby SD_TH pin. 1 Manual override,outputinelectricalIdle.Differentialinputsareignored. Table7.ReceiverElectricalIdleDetectThresholdAdjust SD_TH resistorvalue(Ω)(1) ReceiverElectricalIdleDetectThreshold(DIFFp-p) Float(noresistorrequired) 130 mV (defaultcondition) 0 225 mV 80k 20 mV (1) SD_TH resistorvaluecan be setfrom0 through80k ohms toachievedesiredidledetectthreshold,see Figure6

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VOD - DIFFERENTIAL OUTPUT VOLTAGE (mVp-p) PD - POWER DISSIPATION (mW) VDD = 2.5 V, TA = 25° C 100 150 200 250 0 10k 20k 30k 40k 50k 60k 70k 80k SD_TH RESISTOR VALUE ( :) ELECTRICAL IDLE DETECT THRESHOLD (DIFF mVp-p) VDD = 2.5V TA = 25° C DS64BR401 www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013 TYPICAL PERFORMANCE CURVES Figure6.TypicalIdleThresholdvs.SD_TH resistor Figure7.TypicalPower Dissipation(PD)vs. value Output DifferentialVoltage(VOD) SYSTEM MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS The System Management Bus interfaceiscompatibletoSMBus 2.0physicallayerspecification.ENSMB must be pulledhightoenableSMBus mode and allowaccesstotheconfigurationregisters. The DS64BR401 has theAD[3:0]inputsinSMBus mode. These pinssettheSMBus slaveaddressinputs.The AD[3:0]pinshave internalpull-down.When leftfloatingor pulledlow the AD[3:0]= 0000'b,the devicedefault address byte isA0'h.Based on the SMBus 2.0 specification,the DS64BR401 has a 7-bitslaveaddress of 1010000'b.The LSB issetto 0'b(fora WRITE), thusthe 8-bitvalueis1010 0000'bor A0'h.The boldbits indicatetheAD[3:0]pinmap totheslaveaddressbits[4:1].The deviceaddressbytecan be setwiththeuse of theAD[3:0]inputs.Below aresome examples. AD[3:0]= 0001'b,thedeviceaddressbyteisA2'h AD[3:0]= 0010'b,thedeviceaddressbyteisA4'h AD[3:0]= 0100'b,thedeviceaddressbyteisA8'h AD[3:0]= 1000'b,thedeviceaddressbyteisB0'h The SDA, SCL pinsare 3.3V tolerant,butare not5V tolerant.Externalpull-upresistorisrequiredon theSDA. The resistorvaluecan be from 1 kΩ to5 kΩ dependingon thevoltage,loadingand speed.The SCL may also requirean externalpull-upresistorand itdepends on theHostthatdrivesthebus. TRANSFER OF DATA VIA THE SMBUS Duringnormaloperationthedataon SDA must be stableduringthetimewhen SCL isHigh. TherearethreeuniquestatesfortheSMBus: START: A High-to-Lowtransitionon SDA whileSCL isHighindicatesa message START condition. STOP: A Low-to-Hightransitionon SDA whileSCL isHighindicatesa message STOP condition. IDLE: IfSCL and SDA arebothHigh fora timeexceedingtBUF fromthelastdetectedSTOP conditionorifthey areHighfora totalexceedingthemaximum specificationfortHIGH thenthebus willtransfertotheIDLE state. SMBUS TRANSACTIONS The devicesupportsWRITE and READ transactions.See RegisterDescriptiontableforregisteraddress,type (Read/Write,Read Only),defaultvalueand functioninformation. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com When SMBus isenabled,theDS64BR401 must use one of the followingDe-emphasis settings(Table8). The driverde-emphasisvalueisseton a perchannelbasisusing8 differentregisters.Each register(0x11,0x18, 0x1F,0x26,0x2E,0x35,0x3C,0x43)requiresone ofthefollowingDe-emphasissettingswhen inSMBus mode. Table8.De-Emphasis RegisterSettings(must writeone ofthefollowingwhen inSMBus mode) De-Emphasis Value RegisterSetting 3 Gbps Operation 6 Gbps Operation 0.0dB 0x01 10”traceor1 meter28 awg cable 5”traceor0.5meter28 awg cable -3.5dB 0x38 20”traceor2 meters28 awg cable 10”traceor1meters28 awg cable -6dB 0x88 25”traceor3 meterscable 20”traceor2 meterscable -9dB 0x90 5 meters28 awg cable 3 meters28 awg cable -12dB 0xA0 8 meters28 awg cable 5 meters28 awg cable WRITING A REGISTER To writea register,thefollowingprotocolisused (seeSMBus 2.0specification). 1. The Hostdrivesa START condition,the7-bitSMBus address,and a “0”indicatinga WRITE. 2. The Device(Slave)drivestheACK bit(“0”). 3. The Hostdrivesthe8-bitRegisterAddress. 4. The Devicedrivesan ACK bit(“0”). 5. The Hostdrivethe8-bitdatabyte. 6. The Devicedrivesan ACK bit(“0”). 7. The Hostdrivesa STOP condition. The WRITE transactioniscompleted,the bus goes IDLE and communicationwithotherSMBus devicesmay now occur. READING A REGISTER To reada register,thefollowingprotocolisused (seeSMBus 2.0specification). 1. The Hostdrivesa START condition,the7-bitSMBus address,and a “0”indicatinga WRITE. 2. The Device(Slave)drivestheACK bit(“0”). 3. The Hostdrivesthe8-bitRegisterAddress. 4. The Devicedrivesan ACK bit(“0”). 5. The Hostdrivesa START condition. 6. The Hostdrivesthe7-bitSMBus Address,and a “1”indicatinga READ. 7. The Devicedrivesan ACK bit“0”. 8. The Devicedrivesthe8-bitdatavalue(registercontents). 9. The Hostdrivesa NACK bit“1”indicatingend oftheREAD transfer. 10. The Hostdrivesa STOP condition. The READ transactioniscompleted,thebus goes IDLE and communicationwithotherSMBus devicesmay now occur. RECOMMENDED SMBUS REGISTER SETTINGS When SMBus mode isenabled(ENSMB = 1),thedefaultregisterarenotconfiguredtoan appropriatesettings. Below is the recommended settingsto configurethe EQ, VOD and DE to a medium levelthatsupports interconnectlength of 20 inches FR4 trace or 3 to 5 meters of cable length.Please referto , Table2,Table3,Table4,Table5,Table8,Table9 foradditionalinformationand recommended settings. 1. ResettheSMBus registerstodefaultvalues: – Write01'htoaddress 0x00. 2. Setde-emphasisto-6dB enhance forallchannels(CH0–CH7): – Write88'htoaddress 0x11,0x18,0x1F,0x26,0x2E,0x35,0x3C, 0x43. 3. SetequalizationtoexternalpinlevelEQ[1:0]= 00 (~9dB at3 GHz) forallchannels(CH0–CH7):

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www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013 – Write30'htoaddress 0x0F,0x16,0x1D, 0x24,0x2C, 0x33,0x3A, 0x41. 4. SetVOD = 1.0Vforallchannels(CH0–CH7): – Write0F'htoaddress 0x10,0x17,0x1E,0x25,0x2D, 0x34,0x3B, 0x42. IDLE AND RATE DETECTION TO EXTERNAL PINS The functionsofIDLE and RATE detectiontoexternalpinsformonitoringcan be supportedinSMBus mode. The externalGPIO pinsof 19, 20, 46 and 47 willbe changed and theywillserveas outputsforIDLE and RATE detectsignals. The followingexternalpinsshouldbe settoautodetection: RATE = F (FLOAT) – autoRATE detectenabled TXIDLEA/B = F (FLOAT) – autoIDLE detectenabled Thereare4 GPIO pinsthatcan be configuredas outputswithreg_4E[0]. To disabletheexternalSMBus addresspins,so pin46 and 47 can be used as outputs: WRITE 01'H TO ADDRESS 0X4E. Care must be takentoensurethatonlythedesiredstatusblockisenabledand attachedtotheexternalpinas the statusblockscan be OR ’ed togetherinternally.Registerbitsreg_47[5:4]and bitsreg_4C[7:6]are used to enableeach ofthestatusblockoutputstotheexternalpins.The channelstatusblockscan be internallyOR ’ed togethertomonitormore thanone channelata time.Thisallowsmore informationtobe presentedon thestatus outputsand laterifdesired,a diagnosisof the channelidentitycan be made withadditionalSMBus writesto registerbitsreg_47[5:4]and bitsreg_4C[7:6]. Below areexamplestoconfigurethedeviceand bringtheinternalIDLE and RATE statustopins19,20,46,47. To monitortheIDLE detectwithtwo channelsORed (CH0 withCH2, CH1 withCH3, CH4 withCH6, CH5 with CH7): WRITE 32'H TO ADDRESS 0X47. The followingIDLE statusshouldbe observableon theexternalpins: pin19 – CH0 withCH2, pin20 – CH1 withCH3, pin46 – CH4 withCH6, pin47 – CH5 withCH7. Pin= HIGH (VDD) means IDLE isdetected(nosignalpresent). Pin= LOW (GND) means ACTIVE (datasignalpresent). To monitortheRATE detectwithtwo channelsORed (CH0 withCH2, CH1 withCH3, CH4 withCH6, CH5 with CH7): WRITE C0 'H TO ADDRESS 0X4C. The followingRATE statusshouldbe observableon theexternalpins: pin19 – CH0 withCH2, pin20 – CH1 withCH3, pin46 – CH4 withCH6, pin47 – CH5 withCH7. Pin= HIGH (VDD) means highdatarateisdetected(6Gbps). Pin= LOW (GND) means lowrateisdetected(3Gbps). Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com Table9. SMBus RegisterMap Address RegisterName Bit(s) Field Type Default Description 0x00 Reset 7:1 Reserved R/W 0x00 Setbitsto0.

0 Reset SMBus Reset

1:Resetregisterstodefaultvalue 0x01 PWDN Channels 7:0 PWDN CHx R/W 0x00 Power Down perChannel [7]:CHA_3 [6]:CHA_2 [5]:CHA_1 [4]:CHA_0 [3]:CHB_3 [2]:CHB_2 [1]:CHB_1 [0]:CHB_0 00'h= allchannelsenabled FF'h= allchannelsdisabled 0x02 PWDN Control 7:1 Reserved R/W 0x00 Setbitsto0.

0 OverridePWDN 0:AllowPWDN pincontrol

1:BlockPWDN pincontrol 0x08 PinControlOverride 7:5 Reserved R/W 0x00 Setbitsto0.

4 OverrideIDLE 0:AllowIDLE pincontrol

1:BlockIDLE pincontrol 3 Reserved Setbitto0.

2 OverrideRATE 0:AllowRATE pincontrol

1:BlockRATE pincontrol 1:0 Reserved Setbitsto0. 0x0E CH0 -CHB0 7:6 Reserved R/W 0x00 Setbitsto0. IDLE RATE Select 5 IDLE auto 0:AllowIDLE_selcontrolinBit4 1:AutomaticIDLE detect

4 IDLE select 0:OutputisON (SD isdisabled)

1:Outputismuted (electricalidle) 3:2 Reserved Setbitsto0.

1 RATE auto 0:AllowRATE_sel controlinBit0

1:AutomaticRATE detect 0 RATE select 0:2.5to3.2Gbps 1:5.0to6.4Gbps 0x0F CH0 -CHB0 7:6 Reserved R 0x0 Setbitsto0. EQ Control 5:0 CH0 IB0EQ R/W 0x20 IB0EQ Control-totalof24 levels (3gainstageswith8 settings) [5]:EnableEQ [4:3]:Gain StageControl [2:0]:BoostLevelControl Pin[EQ0 EQ1] = Register[EN][GST][BST]= Hex Value FF = 100000 = 20'h= Bypass (Default) 11 = 101010 = 2A'h 00 = 110000 = 30'h 0F = 110001 = 31'h 01 = 111000 = 38'h 1F = 110100 = 34'h 10 = 110101 = 35'h F0 = 111010 = 3A'h F1 = 111100 = 3C'h 0x10 CH0 -CHB0 7:6 Reserved R 0x00 Setbitto0. VOD Control 5:0 CH0 OB0 VOD R/W 0x03 OB0 VOD Control 03'h= 600 mV (Default) 07'h= 800 mV 0F'h= 1000 mV 1F'h= 1200 mV 3F'h= 1400 mV

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www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013 Table9. SMBus RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x11 CH0 -CHB0 7:0 CH0 OB0 DEM R/W 0x03 OB0 DEM Control DE Control [7]:DEM TYPE (Compatibility= 0 /Enhanced = [6:0]:DEM LevelControl Pin[DEM1 DEM0] = Register[TYPE][Level Control]= Hex Value 00 = 00000001 = 01'h= 0.0dB 01 = 00111000 = 38'h= −3.5dB 0F = 10001000 = 88'h= −6.0dB 01 = 10010000 = 90'h= −9.0dB 1F = 10100000 = A0'h= −12.0dB F0 = 10010000 = 90'h= −9.0dB F1 = 10100000 = A0'h= −12.0dB FF = 11000000 = C0'h= Reserved 0x12 CH0 -CHB0 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:0 IDLE threshold De-assert= [3:2],assert= [1:0] 00 = 110 mV, 70 mV (Default) 01 = 150 mV, 110 mV 10 = 170 mV, 130 mV 11 = 190 mV, 150 mV 0x15 CH1 -CHB1 7:6 Reserved R/W 0x00 Setbitsto0. IDLE RATE Select 5 IDLE auto 0:AllowIDLE_selcontrolinBit4 1:AutomaticIDLE detect 1:Outputismuted (electricalidle) 3:2 Reserved Setbitsto0. 1:AutomaticRATE detect 0 RATE select 0:2.5to3.2Gbps 1:5.0to6.4Gbps 0x16 CH1 -CHB1 7:6 Reserved R/W 0x20 Setbitsto0. EQ Control 5:0 CH1 IB1EQ IB1EQ Control-totalof24 levels (3gainstageswith8 settings) [5]:EnableEQ [4:3]:Gain StageControl [2:0]:BoostLevelControl Pin[EQ0 EQ1] = Register[EN][GST][BST]= Hex Value FF = 100000 = 20'h= Bypass (Default) 11 = 101010 = 2A'h 00 = 110000 = 30'h 0F = 110001 = 31'h 01 = 111000 = 38'h 1F = 110100 = 34'h 10 = 110101 = 35'h F0 = 111010 = 3A'h F1 = 111100 = 3C'h 0x17 CH1 -CHB1 7:6 Reserved R 0x00 Setbitto0. VOD Control 5:0 CH1 OB1 VOD R/W 0x03 OB1 VOD Control 03'h= 600 mV (Default) 07'h= 800 mV 0F'h= 1000 mV 1F'h= 1200 mV 3F'h= 1400 mV Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com Table9. SMBus RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x18 CH1 -CHB1 7:0 CH1 OB1 DEM R/W 0x03 OB1 DEM Control DE Control [7]:DEM TYPE (Compatibility= 0 /Enhanced = [6:0]:DEM LevelControl Pin[DEM1 DEM0] = Register[TYPE][Level Control]= Hex Value 00 = 00000001 = 01'h= 0.0dB 01 = 00111000 = 38'h= −3.5dB 0F = 10001000 = 88'h= −6.0dB 01 = 10010000 = 90'h= −9.0dB 1F = 10100000 = A0'h= −12.0dB F0 = 10010000 = 90'h= −9.0dB F1 = 10100000 = A0'h= −12.0dB FF = 11000000 = C0'h= Reserved 0x19 CH1 -CHB1 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:0 IDLE threshold De-assert= [3:2],assert= [1:0] 00 = 110 mV, 70 mV (Default) 01 = 150 mV, 110 mV 10 = 170 mV, 130 mV 11 = 190 mV, 150 mV 0x1C CH2 -CHB2 7:6 Reserved R/W 0x00 Setbitsto0. IDLE RATE Select 5 IDLE auto 0:AllowIDLE_selcontrolinBit4 1:AutomaticIDLE detect 1:Outputismuted (electricalidle) 3:2 Reserved Setbitsto0. 1:AutomaticRATE detect 0 RATE select 0:2.5to3.2Gbps 1:5.0to6.4Gbps 0x1D CH2 -CHB2 7:6 Reserved R/W 0x20 Setbitsto0. EQ Control 5:0 CH2 IB2EQ IB2EQ Control-totalof24 levels (3gainstageswith8 settings) [5]:EnableEQ [4:3]:Gain StageControl [2:0]:BoostLevelControl Pin[EQ0 EQ1] = Register[EN][GST][BST]= Hex Value FF = 100000 = 20'h= Bypass (Default) 11 = 101010 = 2A'h 00 = 110000 = 30'h 0F = 110001 = 31'h 01 = 111000 = 38'h 1F = 110100 = 34'h 10 = 110101 = 35'h F0 = 111010 = 3A'h F1 = 111100 = 3C'h 0x1E CH2 -CHB2 7:6 Reserved R 0x00 Setbitto0. VOD Control 5:0 CH2 OB2 VOD R/W 0x03 OB2 VOD Control 03'h= 600 mV (Default) 07'h= 800 mV 0F'h= 1000 mV 1F'h= 1200 mV 3F'h= 1400 mV

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www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013 Table9. SMBus RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x1F CH2 -CHB2 7:0 CH2 OB2 DEM R/W 0x03 OB2 DEM Control DE Control [7]:DEM TYPE (Compatibility= 0 /Enhanced = [6:0]:DEM LevelControl Pin[DEM1 DEM0] = Register[TYPE][Level Control]= Hex Value 00 = 00000001 = 01'h= 0.0dB 01 = 00111000 = 38'h= −3.5dB 0F = 10001000 = 88'h= −6.0dB 01 = 10010000 = 90'h= −9.0dB 1F = 10100000 = A0'h= −12.0dB F0 = 10010000 = 90'h= −9.0dB F1 = 10100000 = A0'h= −12.0dB FF = 11000000 = C0'h= Reserved 0x20 CH2 -CHB2 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:0 IDLE threshold De-assert= [3:2],assert= [1:0] 00 = 110 mV, 70 mV (Default) 01 = 150 mV, 110 mV 10 = 170 mV, 130 mV 11 = 190 mV, 150 mV 0x23 CH3 -CHB3 7:6 Reserved R/W 0x00 Setbitsto0. IDLE RATE Select 5 IDLE auto 0:AllowIDLE_selcontrolinBit4 1:AutomaticIDLE detect 1:Outputismuted (electricalidle) 3:2 Reserved Setbitsto0. 1:AutomaticRATE detect 0 RATE select 0:2.5to3.2Gbps 1:5.0to6.4Gbps 0x24 CH3 -CHB3 7:6 Reserved R/W 0x20 Setbitsto0. EQ Control 5:0 CH3 IB3EQ IB3EQ Control-totalof24 levels (3gainstageswith8 settings) [5]:EnableEQ [4:3]:Gain StageControl [2:0]:BoostLevelControl Pin[EQ0 EQ1] = Register[EN][GST][BST]= Hex Value FF = 100000 = 20'h= Bypass (Default) 11 = 101010 = 2A'h 00 = 110000 = 30'h 0F = 110001 = 31'h 01 = 111000 = 38'h 1F = 110100 = 34'h 10 = 110101 = 35'h F0 = 111010 = 3A'h F1 = 111100 = 3C'h 0x25 CH3 -CHB3 7:6 Reserved R 0x00 Setbitto0. VOD Control 5:0 CH3 OB3 VOD R/W 0x03 OB3 VOD Control 03'h= 600 mV (Default) 07'h= 800 mV 0F'h= 1000 mV 1F'h= 1200 mV 3F'h= 1400 mV Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com Table9. SMBus RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x26 CH3 -CHB3 7:0 CH3 OB3 DEM R/W 0x03 OB3 DEM Control DE Control [7]:DEM TYPE (Compatibility= 0 /Enhanced = [6:0]:DEM LevelControl Pin[DEM1 DEM0] = Register[TYPE][Level Control]= Hex Value 00 = 00000001 = 01'h= 0.0dB 01 = 00111000 = 38'h= −3.5dB 0F = 10001000 = 88'h= −6.0dB 01 = 10010000 = 90'h= −9.0dB 1F = 10100000 = A0'h= −12.0dB F0 = 10010000 = 90'h= −9.0dB F1 = 10100000 = A0'h= −12.0dB FF = 11000000 = C0'h= Reserved 0x27 CH3 -CHB3 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:0 IDLE threshold De-assert= [3:2],assert= [1:0] 00 = 110 mV, 70 mV (Default) 01 = 150 mV, 110 mV 10 = 170 mV, 130 mV 11 = 190 mV, 150 mV 0x2B CH4 -CHA0 7:6 Reserved R/W 0x00 Setbitsto0. IDLE RATE Select 5 IDLE auto 0:AllowIDLE_selcontrolinBit4 1:AutomaticIDLE detect 1:Outputismuted (electricalidle) 3:2 Reserved Setbitsto0. 1:AutomaticRATE detect 0 RATE select 0:2.5to3.2Gbps 1:5.0to6.4Gbps 0x2C CH4 -CHA0 7:6 Reserved R/W 0x20 Setbitsto0. EQ Control 5:0 CH4 IA0EQ IA0EQ Control-totalof24 levels (3gainstageswith8 settings) [5]:EnableEQ [4:3]:Gain StageControl [2:0]:BoostLevelControl Pin[EQ0 EQ1] = Register[EN][GST][BST]= Hex Value FF = 100000 = 20'h= Bypass (Default) 11 = 101010 = 2A'h 00 = 110000 = 30'h 0F = 110001 = 31'h 01 = 111000 = 38'h 1F = 110100 = 34'h 10 = 110101 = 35'h F0 = 111010 = 3A'h F1 = 111100 = 3C'h 0x2D CH4 -CHA0 7:6 Reserved R 0x00 Setbitto0. VOD Control 5:0 CH4 OA0 VOD R/W 0x03 OA0 VOD Control 03'h= 600 mV (Default) 07'h= 800 mV 0F'h= 1000 mV 1F'h= 1200 mV 3F'h= 1400 mV

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www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013 Table9. SMBus RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x2E CH4 -CHA0 7:0 CH4 OA0 DEM R/W 0x03 OA0 DEM Control DE Control [7]:DEM TYPE (Compatibility= 0 /Enhanced = [6:0]:DEM LevelControl Pin[DEM1 DEM0] = Register[TYPE][Level Control]= Hex Value 00 = 00000001 = 01'h= 0.0dB 01 = 00111000 = 38'h= −3.5dB 0F = 10001000 = 88'h= −6.0dB 01 = 10010000 = 90'h= −9.0dB 1F = 10100000 = A0'h= −12.0dB F0 = 10010000 = 90'h= −9.0dB F1 = 10100000 = A0'h= −12.0dB FF = 11000000 = C0'h= Reserved 0x2F CH4 -CHA0 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:0 IDLE threshold De-assert= [3:2],assert= [1:0] 00 = 110 mV, 70 mV (Default) 01 = 150 mV, 110 mV 10 = 170 mV, 130 mV 11 = 190 mV, 150 mV 0x32 CH5 -CHA1 7:6 Reserved R/W 0x00 Setbitsto0. IDLE RATE Select 5 IDLE auto 0:AllowIDLE_selcontrolinBit4 1:AutomaticIDLE detect 1:Outputismuted (electricalidle) 3:2 Reserved Setbitsto0. 1:AutomaticRATE detect 0 RATE select 0:2.5to3.2Gbps 1:5.0to6.4Gbps 0x33 CH5 -CHA1 7:6 Reserved R/W 0x20 Setbitsto0. EQ Control 5:0 CH5 IA1EQ IA1EQ Control-totalof24 levels (3gainstageswith8 settings) [5]:EnableEQ [4:3]:Gain StageControl [2:0]:BoostLevelControl Pin[EQ0 EQ1] = Register[EN][GST][BST]= Hex Value FF = 100000 = 20'h= Bypass (Default) 11 = 101010 = 2A'h 00 = 110000 = 30'h 0F = 110001 = 31'h 01 = 111000 = 38'h 1F = 110100 = 34'h 10 = 110101 = 35'h F0 = 111010 = 3A'h F1 = 111100 = 3C'h 0x34 CH5 -CHA1 7:6 Reserved R 0x00 Setbitto0. VOD Control 5:0 CH5 OA1 VOD R/W 0x03 OA1 VOD Control 03'h= 600 mV (Default) 07'h= 800 mV 0F'h= 1000 mV 1F'h= 1200 mV 3F'h= 1400 mV Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com Table9. SMBus RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x35 CH5 -CHA1 7:0 CH5 OA1 DEM R/W 0x03 OA1 DEM Control DE Control [7]:DEM TYPE (Compatibility= 0 /Enhanced = [6:0]:DEM LevelControl Pin[DEM1 DEM0] = Register[TYPE][Level Control]= Hex Value 00 = 00000001 = 01'h= 0.0dB 01 = 00111000 = 38'h= −3.5dB 0F = 10001000 = 88'h= −6.0dB 01 = 10010000 = 90'h= −9.0dB 1F = 10100000 = A0'h= −12.0dB F0 = 10010000 = 90'h= −9.0dB F1 = 10100000 = A0'h= −12.0dB FF = 11000000 = C0'h= Reserved 0x36 CH5 -CHA1 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:0 IDLE threshold De-assert= [3:2],assert= [1:0] 00 = 110 mV, 70 mV (Default) 01 = 150 mV, 110 mV 10 = 170 mV, 130 mV 11 = 190 mV, 150 mV 0x39 CH6 -CHA2 7:6 Reserved R/W 0x00 Setbitsto0. IDLE RATE Select 5 IDLE auto 0:AllowIDLE_selcontrolinBit4 1:AutomaticIDLE detect 1:Outputismuted (electricalidle) 3:2 Reserved Setbitsto0. 1:AutomaticRATE detect 0 RATE select 0:2.5to3.2Gbps 1:5.0to6.4Gbps 0x3A CH6 -CHA2 7:6 Reserved R/W 0x20 Setbitsto0. EQ Control 5:0 CH6 IA2EQ IA2EQ Control-totalof24 levels (3gainstageswith8 settings) [5]:EnableEQ [4:3]:Gain StageControl [2:0]:BoostLevelControl Pin[EQ0 EQ1] = Register[EN][GST][BST]= Hex Value FF = 100000 = 20'h= Bypass (Default) 11 = 101010 = 2A'h 00 = 110000 = 30'h 0F = 110001 = 31'h 01 = 111000 = 38'h 1F = 110100 = 34'h 10 = 110101 = 35'h F0 = 111010 = 3A'h F1 = 111100 = 3C'h 0x3B CH6 -CHA2 7:6 Reserved R 0x00 Setbitto0. VOD Control 5:0 CH6 OA2 VOD R/W 0x03 OA2 VOD Control 03'h= 600 mV (Default) 07'h= 800 mV 0F'h= 1000 mV 1F'h= 1200 mV 3F'h= 1400 mV

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www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013 Table9. SMBus RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x3C CH6 -CHA2 7:0 CH6 OA2 DEM R/W 0x03 OA2 DEM Control DE Control [7]:DEM TYPE (Compatibility= 0 /Enhanced = [6:0]:DEM LevelControl Pin[DEM1 DEM0] = Register[TYPE][Level Control]= Hex Value 00 = 00000001 = 01'h= 0.0dB 01 = 00111000 = 38'h= −3.5dB 0F = 10001000 = 88'h= −6.0dB 01 = 10010000 = 90'h= −9.0dB 1F = 10100000 = A0'h= −12.0dB F0 = 10010000 = 90'h= −9.0dB F1 = 10100000 = A0'h= −12.0dB FF = 11000000 = C0'h= Reserved 0x3D CH6 -CHA2 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:0 IDLE threshold De-assert= [3:2],assert= [1:0] 00 = 110 mV, 70 mV (Default) 01 = 150 mV, 110 mV 10 = 170 mV, 130 mV 11 = 190 mV, 150 mV 0x40 CH7 -CHA3 7:6 Reserved R/W 0x00 Setbitsto0. IDLE RATE Select 5 IDLE auto 0:AllowIDLE_selcontrolinBit4 1:AutomaticIDLE detect 1:Outputismuted (electricalidle) 3:2 Reserved Setbitsto0. 1:AutomaticRATE detect 0 RATE select 0:2.5to3.2Gbps 1:5.0to6.4Gbps 0x41 CH7 -CHA3 7:6 Reserved R/W 0x20 Setbitsto0. EQ Control 5:0 CH7 IA3EQ IA3EQ Control-totalof24 levels (3gainstageswith8 settings) [5]:EnableEQ [4:3]:Gain StageControl [2:0]:BoostLevelControl Pin[EQ0 EQ1] = Register[EN][GST][BST]= Hex Value FF = 100000 = 20'h= Bypass (Default) 11 = 101010 = 2A'h 00 = 110000 = 30'h 0F = 110001 = 31'h 01 = 111000 = 38'h 1F = 110100 = 34'h 10 = 110101 = 35'h F0 = 111010 = 3A'h F1 = 111100 = 3C'h 0x42 CH7 -CHA3 7:6 Reserved R 0x00 Setbitto0. VOD Control 5:0 CH7 OA3 VOD R/W 0x03 OA3 VOD Control 03'h= 600 mV (Default) 07'h= 800 mV 0F'h= 1000 mV 1F'h= 1200 mV 3F'h= 1400 mV Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com Table9. SMBus RegisterMap (continued) Address RegisterName Bit(s) Field Type Default Description 0x43 CH7 -CHA3 7:0 CH7 OA3 DEM R/W 0x03 OA3 DEM Control DE Control [7]:DEM TYPE (Compatibility= 0 /Enhanced = [6:0]:DEM LevelControl Pin[DEM1 DEM0] = Register[TYPE][Level Control]= Hex Value 00 = 00000001 = 01'h= 0.0dB 01 = 00111000 = 38'h= −3.5dB 0F = 10001000 = 88'h= −6.0dB 01 = 10010000 = 90'h= −9.0dB 1F = 10100000 = A0'h= −12.0dB F0 = 10010000 = 90'h= −9.0dB F1 = 10100000 = A0'h= −12.0dB FF = 11000000 = C0'h= Reserved 0x44 CH7 -CHA3 7:4 Reserved R/W 0x00 Setbitsto0. IDLE Threshold 3:0 IDLE threshold De-assert= [3:2],assert= [1:0] 00 = 110 mV, 70 mV (Default) 01 = 150 mV, 110 mV 10 = 170 mV, 130 mV 11 = 190 mV, 150 mV 0x47 EN 7:6 Reserved R/W 0x02 Setbitsto0. DigitalTestPointIDLE 5 CH2, CH3 CH6, CH7 0:DisabledIDLE TestPointforCH2, 3,6,7.Detect 1:EnableIDLE TestPointforCH2, 3,6,7. 4 CH0, CH1 CH4, CH5 0:DisabledIDLE TestPointforCH0, 1,4,5. 1:EnableIDLE TestPointforCH0, 1,4,5. 3:2 Reserved Setbitsto0. GlobalVOD Adjust 1:0 VOD Adjust 00 = −25% 01 = −12.5% 10 = 0% (Default) 11 = +12.5% 0x4C EN 7 CH2, CH3 CH6, CH7 R/W 0x00 0:DisabledRATE TestPointforCH2, 3,6,7. DigitalTestPoint 1:EnableRATE TestPointforCH2, 3,6,7. RATE Detect 6 CH0, CH1 CH4, CH5 0:DisabledRATE TestPointforCH0, 1,4,5. 1:EnableRATE TestPointforCH0, 1,4,5. 5:0 Reserved Setbitsto0. 0x4E DigitalTest 7:1 Reserved R/W 0x00 Setbitsto0.

0 BlockAD[3:0]pins 1:ConfigureGPIO pin46,47,53,54 tobe

outputs.

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www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013

APPLICATION INFORMATION

The DS64BR401 isa highperformancecircuitcapableof deliveringexcellentperformance.Carefulattention must be paidtothedetailsassociatedwithhigh-speeddesignas wellas providinga cleanpower supply.Refer totheLVDS Owner'sManual formore detailedinformationon highspeed designtipstoaddresssignalintegrity designissues. PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS The CML inputsand LPDS outputsmust have a controlleddifferentialimpedance of 100Ω. Itispreferableto routedifferentiallinesexclusivelyon one layerof the board,particularlyforthe inputtraces.The use of vias should be avoided ifpossible.Ifviasmust be used, they should be used sparinglyand must be placed symmetricallyforeach sideofa givendifferentialpair.Route thedifferentialsignalsaway fromothersignalsand noise sources on the printedcircuitboard.See AN-1187(SNOA401 ) foradditionalinformationon WQFN packages. The graphicshown below depictsa typicalmicrostriptraceroutingdesignof the top and bottom layers.This shouldbe used as a referenceto achievethe optimalsystem performance.Impedance discontinuitiesat the differentialviacan be minimizedoreliminatedby increasingtheswellaroundeach viahole.To furtherimprove the signalquality,a ground via placed closeto the signalvia fora low inductancereturncurrentpath is recommended. When theviastructureisassociatedwithstriplinetraceand a thickboard,furtheroptimization such as back drillingisoftenused to reduce the high frequencyeffectsof viastubson the signalpath.To minimizecross-talkcoupling,itisrecommended to have >3X gap spacingbetween the differentialpairs.For example,ifthetracewidthis5 milswith5 milsspacing– 100Ω differentialimpedance (closelycoupled).The gap spacingbetween thedifferentialpairsshouldbe >15 mils. POWER SUPPLY BYPASSING Two approachesarerecommended toensurethattheDS64BR401 isprovidedwithan adequatepower supply. First,thesupply(VDD) and ground(GND) pinsshouldbe connectedtopower planesroutedon adjacentlayers oftheprintedcircuitboard.The layerthicknessofthedielectricshouldbe minimizedso thattheVDD and GND planes createa low inductancesupply with distributedcapacitance.Second, carefulattentionto supply bypassingthroughthe properuse of bypass capacitorsisrequired.A 0.01 μF bypass capacitorshouldbe connectedtoeach VDD pinsuch thatthecapacitorisplacedas closeas possibletotheDS64BR401. Smaller body size capacitorscan help facilitateproper component placement.Additionally,three capacitorswith capacitanceintherange of2.2μF to10 μF shouldbe incorporatedinthepower supplybypassingdesignas well.These capacitorscan be eithertantalumoran ultra-lowESR ceramic. Figure8. TypicalPCB Trace Routing Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:DS64BR401

VTX = 1.0Vp-p, PRBS7 TP0 TP1 Coax Coax Scope Instrument DS64BR401EVKminiSAS4x Cable miniSAS4x Cable SMA adaptor SMA adaptor DS64BR401 SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE EYE-DIAGRAM CHARACTERISTIC Figure9.TestSetup Connection Diagram Figure10.TP0: Input— After5m 26–AWG Cable at6 Gbps Figure11.TP1: Output — After1m 28–AWG Cable at6 Gbps Figure12.TP0: Input— After1m 28–AWG cableat6 Gbps Figure13.TP1: Output — After5m 26–AWG Cable at6 Gbps

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www.ti.com SNLS304G –JUNE 2009–REVISED APRIL 2013

REVISION HISTORY

www.ti.com 15-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples DS64BR401SQ/NOPB ACTIVE WQFN NJY 54 2000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -10 to 85 DS64BR401 SQ DS64BR401SQE/NOPB ACTIVE WQFN NJY 54 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -10 to 85 DS64BR401 SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS64BR401SQ/NOPB WQFN NJY 54 2000 367.0 367.0 38.0 DS64BR401SQE/NOPB WQFN NJY 54 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 54X 0.3 0.2 3.51±0.1 50X 0.5 54X 0.5 0.3

0.8 MAX

8.5 7.5±0.1 2X 4 A 10.1 9.9 B 5.6 5.4 0.3 0.2 0.5 0.3 (0.1) 4214993/A 07/2013 WQFNNJY0054A WQFN PIN 1 INDEX AREA SEATING PLANE 18 28 19 27 54 46

0.1 C A B

0.05 C (OPTIONAL) PIN 1 ID DETAIL SEE TERMINAL NOTES: 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 2.000 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT (3.51)

0.07 MIN

0.07 MAX

54X (0.6) 54X (0.25) (9.8) (5.3) ( ) TYP VIA 0.2 50X (0.5) (1.16) (1) TYP (7.5) (1.17) TYP 4214993/A 07/2013 WQFNNJY0054A WQFN SYMM SEE DETAILS 19 27 4654 SYMM LAND PATTERN EXAMPLE SCALE:8X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING METAL SOLDER MASK DEFINED METAL SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (1.17) TYP (5.3) 54X (0.6) 54X (0.25) 12X (1.51) (9.8) (0.855) TYP 12X (0.97) 50X (0.5) 4214993/A 07/2013 WQFNNJY0054A WQFN NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM TYP METAL SOLDERPASTE EXAMPLE BASED ON 0.125mm THICK STENCIL EXPOSED PAD 67% PRINTED SOLDER COVERAGE BY AREA SCALE:10X 19 27 4654 SYMM

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Summary

Quad Bi-Directional Transceiver with Equalization and De-Emphasis

Description

Quad Bi-Directional Transceiver with Equalization and De-Emphasis

Source title DS64BR401SQ/NOPB Datasheet(PDF) - Texas Instruments

Read DS64BR401SQ/NOPB online.

DS64BR401_13 TI1 | Alldatasheet

Document overview

Technical content

2 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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ELECTRICAL CHARACTERISTICS

0.1 UI(4)

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0 Thisstateisforlossymedia,dedicatedIdlethresholddetectcircuitdisabled,

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16 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

0 Reset SMBus Reset

0 OverridePWDN 0:AllowPWDN pincontrol

4 OverrideIDLE 0:AllowIDLE pincontrol

2 OverrideRATE 0:AllowRATE pincontrol

4 IDLE select 0:OutputisON (SD isdisabled)

1 RATE auto 0:AllowRATE_sel controlinBit0

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0 BlockAD[3:0]pins 1:ConfigureGPIO pin46,47,53,54 tobe

26 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

APPLICATION INFORMATION

28 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

REVISION HISTORY

0.8 MAX

0.1 C A B

0.07 MIN

0.07 MAX

DS64BR401SQ/NOPB specifications and overview.

More parts from the same family.