DS560DF810 TI | Alldatasheet
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Technical content
DS560DF810 56 Gbps Multi-Rate 8-Channel Retimer with Crosspoint
1 Features
- -channel multi-protocol retimer with integrated signal conditioning
- All channels lock independently to both PAM4 and NRZ data rates from 19.6 to 28.9 GBd (including div-by-2 and div-by-4 sub-rates)
- Suitable for up to CEI-56G, Ethernet™ (400 GbE), fibre channel (64GFC), InfiniBand™ (HDR), and CPRI/eCPRI PCB, copper cable, and optical
applications
- Automatic lane rate switching for CDR lock up to five different combinations of baud rates and modulation types
- Low latency: <2000 ps (typical) at 26.5625 GBd
- Continuously adaptive time linear equalizer (CTLE), RX feed-forward equalizer (FFE), and decision feedback equalizer (DFE) to support 30+ dB channel loss at 13.28 GHz
- Integrated 2×2 crosspoint
- Adjustable 4-tap TX FFE filter
- Gearbox mode support (NRZ/PAM4 bit mux/de- mux, NRZ/PAM4 serializer/deserializer)
- On-chip eye opening monitor (EOM), PRBS generator, and PRBS checker for debug
- Dual 1.8-V and 1.2-V supplies
- –40°C to +85°C operating temperature range
- 8.00 mm × 13.00 mm BGA package with integrated AC coupling capacitors
2 Applications
- Active electrical cables (AEC) (QSFP-DD, OSFP)
- Front-port C2M attachment unit interface (AUI) jitter cleaning
- Backplane (KR) and midplane C2C attachment unit interface (AUI) reach extension
- Speed doubling (gearbox) with NRZ-to-PAM4 aggregation and de-aggregation
3 Description
The DS560DF810 is an eight-channel multi-rate retimer with integrated signal conditioning. It extends the reach and robustness of long, lossy, crosstalk- impaired high-speed serial links. Each channel in the DS560DF810 independently locks to symbol rates (PAM4 and NRZ) in a continuous range from 19.6 to 28.9 GBd or to any supported sub-rate. The integrated CDR function is an excellent choice for front-port optical module applications to reset the jitter budget and retime the high-speed serial data. These features allow for individual lane forward error correction (FEC) pass-through. In addition, the DS560DF810 supports automatic lane rate switching for CDR lock up to five different combinations of baud rates and modulation types without host intervention. The advanced equalization features of the DS560DF810 include a continuously adaptive continuous-time linear equalizer (CTLE), RX feed- forward equalizer (FFE), decision feedback equalizer (DFE), and a programmable, low-jitter 4-tap TX feed- forward equalizer (FFE) filter. These features enable reach extension for lossy interconnects such as direct-attach copper (DAC) cables and backplanes with multiple connectors and crosstalk.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) DS560DF810 ALU (fcBGA, 135) 13 mm × 8 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. VDD1P2 ADDR0 ADDR1 SDC READ_EN_N ALL_DONE_N SDA GND Float for I2C Target mode, or connect to next device’s READ_EN_N for I2C Controller mode I2C Target mode EN_SMB Address straps (pull-up, pull-down, or float) 1 k To system I2C VDD_1V8 or 3.3VCAL_CLK_IN CAL_CLK_OUT To next retimer’s CAL_CLK_IN INT_N To system controller VDD1P8 F (2x) 0.1 F (4x) VDD_1V2 RESET_N 1 F (1x) 0.1 F (2x) VDD_1V8
25 MHz
0.1 F VDD_1V8 RX0N TX0N RX0P TX0P TX1N TX1P RX1N RX1P Aggregator / De-aggregator CDR CDR RX6N TX6N RX6P TX6P TX7N TX7P RX7N RX7P Aggregator / De-aggregator CDR CDR Simplified Schematic DS560DF810 SNLS709B – DECEMBER 2021 – REVISED JUNE 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
7 Mechanical, Packaging, and Orderable Information....4
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2022) to Revision B (June 2023) Page Changes from Revision * (October 2021) to Revision A (December 2022) Page DS560DF810 SNLS709B – DECEMBER 2021 – REVISED JUNE 2023 www.ti.com
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Product Folder Links: DS560DF810
5 Description (continued)
The DS560DF810 is equipped with a bit mux and de-mux gearbox for simple NRZ-to-PAM4 or PAM4-to-NRZ conversion between host and module. The gearbox is capable of aggregating a pair of NRZ inputs up to 28.9 GBd into one 28.9 GBd PAM4 output as well as de-aggregating a single 28.9 GBd PAM4 input into a pair of 28.9 GBd NRZ outputs. The DS560DF810 implements a full 2×2 crosspoint between each pair of adjacent channels after the CDR to enable fast and flexible lane switching for PCB routing flexibility, 2-to-1 multiplexing and 1-to-2 de-multiplexing for failover redundancy, and 1-to-2 fanout for diagnostic monitoring. In addition, integrated physical AC coupling capacitors (TX and RX) eliminate the need for external capacitors on the PCB. These features reduce PCB routing complexity and bill of material (BOM) cost. Diagnostic capabilities include a non-destructive PAM4/NRZ vertical eye height monitor, a 2D PAM4/NRZ eye opening monitor (EOM), PRBS pattern generator with error injector module, PRBS error checker, and on-die temperature sensor. These features help to gauge the margin of the link and can be used to monitor the health of the system over time. The DS560DF810 can be configured either through I 2C or through an external EEPROM. Up to 16 devices can share a single EEPROM. www.ti.com DS560DF810 SNLS709B – DECEMBER 2021 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DS560DF810
6 Device and Documentation Support
6.1 Documentation Support
6.1.1 Related Documentation
For related documentation, see the following:
- Texas Instruments, DS560DFXX0 Programmer's Guide
- Texas Instruments, DS560DF810EVM User's Guide
- Texas Instruments, Implementation of TI 56Gbps PAM4 Retimers in Direct Attach Copper Cable Applications
6.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
6.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
6.4 Trademarks
Ethernet™ is a trademark of Fuji Xerox Co., Ltd. InfiniBand™ is a trademark of InfiniBand Trade Association. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
6.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
6.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. DS560DF810 SNLS709B – DECEMBER 2021 – REVISED JUNE 2023 www.ti.com
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www.ti.com 2-Jun-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS560DF810ALUR Active Production FCCSP (ALU) | 135 1000 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 DS560DF8E0 DS560DF810ALUR.B Active Production FCCSP (ALU) | 135 1000 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 DS560DF8E0 DS560DF810ALUT Active Production FCCSP (ALU) | 135 250 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 DS560DF8E0 DS560DF810ALUT.B Active Production FCCSP (ALU) | 135 250 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 DS560DF8E0 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS560DF810ALUR FCCSP ALU 135 1000 336.6 336.6 41.3 DS560DF810ALUT FCCSP ALU 135 250 336.6 336.6 41.3 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE 8.15 7.85 13.15 12.85
1.55 MAX
0.405 0.325 135X 0.51 0.41
11.2 TYP
6.4 TYP
0.8 TYP
(0.8) (0.9) (0.58) FCBGA - 1.55 mm max heightALU0135A PLASTIC BALL GRID ARRAY 4225902/C 03/2022 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER 0.15 C 0.2 C SEATING PLANE 0.35 C
0.2 C A B
0.08 C SYMM SYMM J H G F E D C B A SCALE 1.500 AB C
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
(0.8) TYP (0.8) TYP 135X ( 0.4) ( 0.4) METAL EDGE ( 0.4) SOLDER MASK OPENING FCBGA - 1.55 mm max heightALU0135A PLASTIC BALL GRID ARRAY 4225902/C 03/2022 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 8X SYMM SYMM J H G F E D C B A EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL SOLDER MASK DETAILS NOT TO SCALE NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (0.8) TYP (0.8) TYP 135X ( 0.4) FCBGA - 1.55 mm max heightALU0135A PLASTIC BALL GRID ARRAY 4225902/C 03/2022 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 8X SYMM SYMM J H G F E D C B A
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