DS5003

DS5003 MAXIM | Alldatasheet

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Technical content

Features

♦ 8051-Compatible Microprocessor for Secure/Sensitive Applications Access 32kB, 64kB, or 128kB of Nonvolatile SRAM for Program and/or Data Storage

128 Bytes of RAM

128 Bytes of Indirect Scratchpad RAM

In-System Programming Through On-Chip Serial Port Can Modify Its Own Program or Data Memory in the End System ♦ Firmware Security Features Memory Stored in Encrypted Form Encryption Using On-Chip 64-Bit Key Automatic True Random-Key Generator Self-Destruct Input (SDI) Top Coating Prevents Microprobing Protects Memory Contents from Piracy ♦ Crash-Proof Operation Maintains All Nonvolatile Resources for Over

10 Years (at Room Temperature) in the

Early Warning Power-Fail Interrupt Watchdog Timer DS5003 Secure Microprocessor Chip Rev 0; 3/08 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Pin Configuration appears at end of data sheet.

Ordering Information

+Denotes a lead-free/RoHS-compliant package. PART TEMP RANGE INTERNAL MICRO PROBE SHIELD PIN- PACKAGE DS5003FPM-16+ 0 °C to +70°C Yes 80 MQFP

Secure Microprocessor Chip ABSOLUTE MAXIMUM RATINGS DC CHARACTERISTICS (VCC = 5V ±10%, TA = 0°C to +70°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on Any Pin Voltage Range on VCC Relative J-STD-020 Specification. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Voltage V CC (Note 1) V CCMIN 5.5 V Minimum Operating Voltage V CCMIN 0°C to +70°C (Note 1) 4.00 4.12 4.25 V Power-Fail Warning Voltage V PFW 0°C to +70°C (Note 1) 4.25 4.37 4.50 V Lithium Supply Voltage V LI (Note 1) 2.5 4.0 V Operating Current at 16MHz I CC (Note 2) 36 mA Idle-Mode Current at 12MHz I IDLE 0°C to +70°C (Note 3) 7.0 mA Stop-Mode Current I STOP (Note 4) 80 μA Pin Capacitance C IN (Note 5) 10 pF Output Supply Voltage (VCCO) V CCO1 (Notes 1, 2) VCC - 0.45 V Output Supply Battery-Backed Mode (VCCO, CE1–CE4, PE1, PE2) VCCO2 0°C to +70°C (Notes 1, 6) VLI - 0.65 V Output Supply Current (Note 7) I CCO1 V CCO = VCC - 0.45V 75 mA Lithium-Backed Quiescent Current (Note 8) ILI 0°C to +70°C 5 75 nA BAT = 3.0V (0°C to +70°C) (Note 1) 4.00 4.25 Reset Trip Point in Stop Mode BAT = 3.3V (0°C to +70°C) (Note 1) 4.40 4.65 V Input Low Voltage V IL (Note 1) -0.3 +0.8 V Input High Voltage V IH1 (Note 1) 2.0 VCC + 0.3 V Input High Voltage (RST, XTAL1, PROG) VIH2 (Note 1) 3.5 VCC + 0.3 V Output Low Voltage at IOL = 1.6mA (Ports 1, 2, 3, PF) VOL1 (Notes 1, 9) 0.15 0.45 V *Storage temperature is defined as the temperature of the device when VCC = 0V and VLI = 0V. In this state, the contents of SRAM are not battery backed and are undefined. Note: The DS5003 adheres to all AC and DC electrical specifications published for the DS5002FP.

Secure Microprocessor Chip AC CHARACTERISTICS—SDI PIN (VCC = 0V to 5V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.5V < VCC < 5.5V 1.3 SDI Pulse Reject (Note 11) t SPR VCC = 0V, VBAT = 2.9V 4 μs 4.5V < VCC < 5.5V 10 SDI Pulse Accept (Note 11) t SPA VCC = 0V, VBAT = 2.9V 50 μs DC CHARACTERISTICS (continued) (VCC = 5V ±10%, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Low Voltage at IOL = 3.2mA (P0.0–P0.7, ALE, BA0–BA14, BD0–BD7, R/ W, CE1N, CE1–CE4, PE1–PE4, VRST) VOL2 (Note 1) 0.15 0.45 V Output High Voltage at IOH = -80μA (Ports 1, 2, 3) VOH1 (Note 1) 2.4 4.8 V Output High Voltage at IOH = -400μA (P0.0–P0.7, ALE, BA0–BA14, BD0–BD7, R/ W, CE1N, CE1–CE4, PE1–PE4, VRST) VOH2 (Note 1) 2.4 4.8 V Input Low Current, VIN = 0.45V (Ports 1, 2, 3) IIL -50 μA Transition Current 1 to 0, VIN = 2.0V (Ports 1, 2, 3) ITL -500 μA SDI Input Low Voltage V ILS (Note 1) 0.4 V SDI Input High Voltage V IHS (Notes 1, 10) 2.0 V CCO V SDI Pulldown Resistor R SDI 25 60 k Input Leakage (P0.0–P0.7, MSEL) IIL 0.45 < V IN < VCC +10 μA RST Pulldown Resistor R RE 0°C to +70°C 40 150 k VRST Pullup Resistor R VR 4.7 k PROG Pullup Resistor R PR 40 k

Secure Microprocessor Chip AC CHARACTERISTICS—EXPANDED BUS-MODE TIMING SPECIFICATIONS (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figures 1, 2) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Oscillator Freq uency 1/t CLK 1.0 16.0 MHz ALE Pulse Width t ALPW 2t CLK - 40 ns Address Valid to ALE Low t AVALL t CLK - 40 ns Address Hold After ALE Low t AVAAV t CLK - 35 ns RD Pulse Width t RDPW 6t CLK - 100 ns WR Pulse Width t WRPW 6t CLK - 100 ns 12MHz 5t CLK - 165 RD Low to Valid Data In t RDLDV 16MHz 5t CLK - 105 ns Data Hold After RD High t RDHDV 0 ns Data Float After RD High t RDHDZ 2t CLK - 70 ns 12MHz 8t CLK - 150 ALE Low to Valid Data In t ALLVD 16MHz 8t CLK - 90 ns 12MHz 9t CLK - 165 Valid Address to Valid Data In t AVDV 16MHz 9t CLK - 105 ns ALE Low to RD or WR Low t ALLRDL 3t CLK - 50 3t CLK + 50 ns Address Valid to RD or WR Low t AVRDL 4t CLK - 130 ns Data Valid to WR Going Low t DVWRL t CLK - 60 ns 12MHz 7t CLK - 150 Data Valid to WR High t DVWRH 16MHz 7t CLK - 90 ns Data Valid After WR High t WRHDV t CLK - 50 ns RD Low to Address Float t RDLAZ 0 ns RD or WR High to ALE High t RDHALH t CLK - 40 t CLK + 50 ns AC CHARACTERISTICS—EXTERNAL CLOCK DRIVE (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 3) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS 12MHz 20 External Clock High Time t CLKHPW 16MHz 15 ns 12MHz 20 External Clock Low Time t CLKLPW 16MHz 15 ns 12MHz 20 External Clock Rise Time t CLKR 16MHz 15 ns 12MHz 20 External Clock Fall Time t CLKF 16MHz 15 ns

Secure Microprocessor Chip AC CHARACTERISTICS—POWER-CYCLE TIME (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 4) PARAMETER SYMBOL MIN MAX UNITS Slew Rate from V CCMIN to VLI t F 130 μs Crystal Startup Time t CSU (Note 12) Power-On Reset Delay t POR 21,504 t CLK AC CHARACTERISTICS—SERIAL PORT TIMING (MODE 0) (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 5) PARAMETER SYMBOL MIN MAX UNITS Serial Port Clock Cycle Time t SPCLK 12t CLK μs Output Data Setup to Rising Clock Edge t DOCH 10t CLK - 133 ns Output Data Hold After Rising Clock Edge t CHDO 2t CLK - 117 ns Clock Rising Edge to Input Data Valid t CHDV 10t CLK - 133 ns Input Data Hold After Rising Clock Edge t CHDIV 0 ns AC CHARACTERISTICS—BYTE-WIDE ADDRESS/DATA BUS TIMING (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 6) PARAMETER SYMBOL MIN MAX UNITS Delay to Byte-Wide Address Valid from CE1, CE2, or CE1N Low During Op Code Fetch tCE1LPA 30 ns Pulse Width of CE1–CE4, PE1–PE4, or CE1N t CEPW 4t CLK - 35 ns Byte-Wide Address Hold After CE1, CE2, or CE1N High During Op Code Fetch tCE1HPA 2t CLK - 20 ns Byte-Wide Data Setup to CE1, CE2, or CE1N High During Op Code Fetch tOVCE1H 1t CLK + 40 ns Byte-Wide Data Hold After CE1, CE2, or CE1N High During Op Code Fetch tCE1HOV 0 ns Byte-Wide Address Hold After CE1–CE4, PE1–PE4, or CE1N High During MOVX tCEHDA 4t CLK - 30 ns Delay from Byte-Wide Address Valid CE1–CE4, PE1–PE4, or CE1N Low During MOVX tCELDA 4t CLK - 35 ns Byte-Wide Data Setup to CE1–CE4, PE1–PE4, or CE1N High During MOVX (Read) tDACEH 1t CLK + 40 ns Byte-Wide Data Hold After CE1–CE4, PE1–PE4, or CE1N High During MOVX (Read) tCEHDV 0 ns Byte-Wide Address Valid to R/ W Active During MOVX (Write) tAVRWL 3t CLK - 35 ns

Secure Microprocessor Chip AC CHARACTERISTICS—BYTE-WIDE ADDRESS/DATA BUS TIMING (continued) (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 6) PARAMETER SYMBOL MIN MAX UNITS Delay from R/ W Low to Valid Data Out During MOVX (Write) tRWLDV 20 ns Valid Data Out Hold Time from CE1–CE4, PE1–PE4, or CE1N High tCEHDV 1t CLK - 15 ns Valid Data Out Hold Time from R/ W High t RWHDV 0 ns Write Pulse Width (R/ W Low Time) t RWLPW 6t CLK - 20 ns RPC AC CHARACTERISTICS—DBB READ (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 7) PARAMETER SYMBOL MIN MAX UNITS CS, A0 Setup to RD t AR 0 ns CS, A0 Hold After RD t RA 0 ns RD Pulse Width t RR 160 ns CS, A0 to Data Out Delay t AD 130 ns RD to Data Out Delay t RD 0 130 ns RD to Data Float Delay t RDZ 85 ns RPC AC CHARACTERISTICS—DBB WRITE (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 7) PARAMETER SYMBOL MIN MAX UNITS CS, A0 Setup to WR t AW 0 ns CS Hold After WR t WA 0 ns A0 Hold After WR t WA 20 ns WR Pulse Width t WW 160 ns Data Setup to WR t DW 130 ns Data Hold After WR t WD 20 ns AC CHARACTERISTICS—DMA (VCC = 5V ±10%, TA = 0°C to +70°C.) PARAMETER SYMBOL MIN MAX UNITS DACK to WR or RD t ACC 0 ns RD or WR to DACK t CAC 0 ns DACK to Data Valid t ACD 0 130 ns RD or WR to DRQ Cleared t CRQ 110 ns

Note 1: All voltages are referenced to ground. XTAL2 disconnected; RST = Port 0 = VCC, MSEL = VSS. disconnected; Port 0 = VCC, RST = MSEL = VSS. Note 6: VCCO2 is measured with VCC < VLI and a maximum load of 10µA on VCCO. Note 7: ICCO1 is the maximum average operating current that can be drawn from VCCO in normal operation. ≤ 4.0; VCC ≤ VBAT; VSDI should be ≤ VILS for IBAT max. Note 9: PF pin operation is specified with VBAT ≥ 3.0V. Note 10: VIHS minimum is 2.0V or VCCO, whichever is lower. not guaranteed unless it is longer than tSPA. crystal vendor for a worst-case specification on this time. Figure 1. Expanded Data Memory Read Cycle

Figure 4. Power-Cycle Timing

Figure 7. RPC Timing Mode

Secure Microprocessor Chip Pin Description PIN NAME FUNCTION POWER PINS

13 V CC Power Supply, +5V

12 V CCO

VCC Output. This is switched between V CC and VLI by internal circuits based on the level of V CC. When power is above the lithium input, power is drawn from V CC. The lithium cell remains isolated from a load. When V CC is below VLI, VCCO switches to the V LI source. VCCO should be connected to the V CC pin of an SRAM.

54 V LI

Lithium Voltage Input. Connect to a lithium cell greater than V LIMIN and no greater than VLIMAX as shown in the electrical specifications. Nominal value is +3V.

52 GND Logic Ground

11 P0.0/AD0 9 P0.1/AD1 7 P0.2/AD2 5 P0.3/AD3 1 P0.4/AD4 79 P0.5/AD5 77 P0.6/AD6 75 P0.7/AD7 General-Purpose I/O Port 0. This port is open drain and cannot drive a logic 1. It requires external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in this mode, it does not require pullups. 15 P1.0 17 P1.1 19 P1.2 21 P1.3 25 P1.4 27 P1.5 29 P1.6 31 P1.7 General-Purpose I/O Port 1 49 P2.0/A8 50 P2.1/A9 51 P2.2/A10 56 P2.3/A11 58 P2.4/A12 60 P2.5/A13 64 P2.6/A14 66 P2.7/A15 General-Purpose I/O Port 2. Also serves as the MSB of the expanded address bus. 36 P3.0/RXD General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on-board UART. This pin should not be connected directly to a PC COM port. 38 P3.1/TXD General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on-board UART. This pin should not be connected directly to a PC COM port. 39 P3.2/ INT0 General-Purpose I/O Port Pin 3.2. Also serves as the active-low external interrupt 0. 40 P3.3/ INT1 General-Purpose I/O Port Pin 3.3. Also serves as the active-low external interrupt 1. 41 P3.4/T0 General-Purpose I/O Port Pin 3.4. Also serves as the timer 0 input. 44 P3.5/T1 General-Purpose I/O Port Pin 3.5. Also serves as the timer 1 input. 45 P3.6/ WR General-Purpose I/O Port Pin 3.6. Also serves as the write strobe for expanded bus operation. 46 P3.7/ RD General-Purpose I/O Port Pin 3.7. Also serves as the read strobe for expanded bus operation.

Secure Microprocessor Chip Pin Description (continued) PIN NAME FUNCTION BYTE-WIDE BUS INTERFACE PINS

37 BA0

35 BA1

33 BA2

30 BA3

28 BA4

26 BA5

24 BA6

20 BA7

6 BA8

4 BA9

76 BA10

80 BA11

18 BA12

8 BA13

16 BA14

Byte-Wide Address Bus Bits 14–0. This bus is combined with the nonmultiplexed data bus (BD7–BD0) to access external SRAM. Decoding is performed using CE1–CE4. Therefore, BA15 is not actually needed. Read/write access is controlled by R/ W. BA14–BA0 connect directly to an 8kB, 32kB, or 128kB SRAM. If an 8kB SRAM is used, BA13 and BA14 are unconnected. If a 128kB SRAM is used, the microcontroller converts CE2 and CE3 to serve as A16 and A15, respectively.

55 BD0

57 BD1

59 BD2

61 BD3

65 BD4

67 BD5

69 BD6

71 BD7

Byte-Wide Data Bus Bits 7–0. This 8-bit bidirectional bus is combined with the nonmultiplexed address bus (BA14–BA0) to access external SRAM. Decoding is performed on CE1 and CE2. Read/write access is controlled by R/ W. D7–D0 connect directly to an SRAM and optionally to a real-time clock or other peripheral. 70 ALE Address Latch Enable. Used to demultiplex the multiplexed expanded address/data bus on port 0. This pin is normally connected to the clock input on a ’373 type transparent latch.

10 R/ W

Read/Write (Active Low). This signal provides the write enable to the SRAMs on the byte-wide bus. It is controlled by the memory map and partition. The blocks selected as program (ROM) are write protected.

74 CE1

Active-Low Chip-Enable 1. This is the primary decoded chip enable for memory access on the byte-wide bus. It connects to the chip-enable input of one SRAM. CE1 is lithium-backed. It remains in a logic-high inactive state when V CC falls below V LI. 72 CE1N Nonbattery-Backed Version of CE1. It is not generally useful because the DS5003 cannot be used with EPROM due to its encryption.

2 CE2

Active-Low Chip-Enable 2. This chip enable is provided to access a second 32kB block of memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, the microcontroller converts CE2 into A16 for a 128kB x 8 SRAM. CE2 is lithium-backed and remains at a logic-high when VCC falls below V LI.

63 CE3

Active-Low Chip-Enable 3. This chip enable is provided to access a third 32kB block of memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, the microcontroller converts CE3 into A15 for a 128kB x 8 SRAM. CE3 is lithium backed and remains at a logic-high when VCC falls below V LI.

Secure Microprocessor Chip Pin Description (continued) PIN NAME FUNCTION

62 CE4

Active-Low Chip-Enable 4. This chip enable is provided to access a fourth 32kB block of memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is unused. CE4 is lithium-backed and remains at a logic-high when V CC falls below V LI.

78 PE1

Active-Low Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when the PES bit is set to logic 1. Commonly used to chip enable a byte-wide real-time clock such as the DS1283. PE1 is lithium backed and remains at a logic-high when V CC falls below VLI. Connect PE1 to battery-backed circuitry only.

3 PE2

Active-Low Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when the PES bit is set to logic 1. PE2 is lithium backed and remains at a logic-high when V CC falls below V LI. Connect PE2 to battery-backed circuitry only.

22 PE3

Active-Low Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when the PES bit is set to a logic 1. PE3 is not lithium backed and can be connected to any type of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to maintain the chip enable in an inactive state when V CC < VLI.

23 PE4

Active-Low Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when the PES bit is set to logic 1. PE4 is not lithium backed and can be connected to any type of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to maintain the chip enable in an inactive state when V CC < VLI.

14 MSEL

Memory Select. This signal controls the memory size selection. When MSEL = +5V, the DS5003 expects to use 32kB x 8 SRAMs. When MSEL = 0V, the DS5003 expects to use a 128kB x 8 SRAM. MSEL must be connected regardless of partition, mode, etc. CLOCK PINS 47, 48 XTAL2, XTAL1 Crystal Connections. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output. RESET, STATUS, AND SELF-DESTRUCT PINS

34 RST

Active-High Reset Input. A logic 1 applied to this pin activates a reset state. This pin is pulled down internally so this pin can be left unconnected if not used. An RC power-on reset circuit is not needed and is not recommended.

32 PROG

Invokes the Bootstrap Loader on Falling Edge. This signal should be debounced so that only one edge is detected. If connected to ground, the microcontroller enters bootstrap loading on power-up. This signal is pulled up internally.

42 VRST

Reset State Active Due to Low VCC. This I/O pin (open drain with internal pullup) indicates that the power supply (VCC) has fallen below the V CCMIN level and the microcontroller is in a reset state. When this occurs, the DS5003 drives this pin to logic 0. Because the microcontroller is lithium backed, this signal is guaranteed even when V CC = 0V. Because it is an I/O pin, it also forces a reset if pulled low externally. This allows multiple parts to synchronize their power- down resets. 43 PF Lithium Backup Active. This output goes to a logic 0 to indicate that the microcontroller has switched to lithium backup. This corresponds to V CC < VLI. Because the microcontroller is lithium backed, this signal is guaranteed even when V CC = 0V. The normal application of this signal is to control lithium-powered current to isolate battery-backed functions from nonbattery- backed functions.

53 SDI

Self-Destruct Input. An active high on this pin causes an unlock procedure. This results in the destruction of vector SRAM, encryption keys, and the loss of power from V CCO. This pin should be grounded if not used. MISCELLANEOUS PINS 68, 73 N.C. No Connection

The DS5003 implements a security system that loads and executes application software in encrypted form. Up to 128kB of standard SRAM (64kB program + 64kB data) can be accessed by its byte-wide bus. This SRAM is converted by the DS5003 into lithium-backed nonvolatile storage for program and data. Data can be maintained for up to 10 years at room temperature with a very small lithium cell. As a result, the contents of the SRAM and the execution of the software appear unintel- ligible to the outside observer. The encryption algorithm uses an internally stored and protected key. Any attempt to discover the key value results in its erasure, rendering the encrypted contents of the SRAM useless. The secure microprocessor chip provides a strong soft- ware-encryption algorithm that incorporates elements of DES encryption. The encryption is based on a 64-bit key word, and the key can only be loaded from an on- chip true random-number generator. As a result, the user never knows the true key value. A self-destruct input (SDI) pin is provided to interface to external tam- per-detection circuitry. With or without the presence of V CC, activation of the SDI pin has the same effect as resetting the security lock: immediate erasure of the key word and the 48-byte vector SRAM area. In addition, an optional top coating of the die prevents access of infor- mation using microprobing techniques. When implemented as a part of an overall secure sys- tem design, a system based on the DS5003 can typi- cally provide a level of security that requires more time and resources to defeat than necessary for unautho- rized individuals who have reason to try. Figure 8 is a block diagram illustrating the internal architecture of the DS5003. The DS5003 operates in an identical fashion to the DS5002FP, except where noted in text. Secure Operation Overview The DS5003 incorporates encryption of the activity on its byte-wide address/data bus to prevent unauthorized access to the program and data information contained in the external SRAM. Loading an application program in this manner is performed by the bootstrap loader using the general sequence described as follows: 1) Activate bootstrap loader by asserting the PROG pin low for at least 48 clocks. 2) Clear security lock. 3) Set memory map configuration. These settings are identical to those used for DS5002FP-based designs. 4) Load application software. 5) Set security lock. 6) Exit loader by taking the PROG pin high again. Loading of application software into the program/data SRAM is performed while the DS5003 is in its bootstrap load mode. Loading is only possible when the security lock is clear. If the security lock was previously set, it must be cleared by issuing the U command from the bootstrap loader. Clearing the security lock instantly clears the previous key word and the contents of the vector SRAM. In addition, the bootstrap ROM writes zeros into the first 32kB of external SRAM. The user’s application software is loaded into user-sup- plied external SRAM by the L command in “scrambled” form through on-chip encryptor circuits. Each external SRAM address is an encrypted representation of an on- chip logical address. Thus, the sequential instructions of an ordinary program or data table are stored nonse- quentially in SRAM memory. The contents of the pro- gram/data SRAM are also encrypted. Each byte in SRAM is encrypted by a key- and address-dependent encryptor circuit such that identical bytes are stored as different values in different memory locations. The encryption of the program/data SRAM is depen- dent on an on-chip 64-bit key word. The key is automat- ically generated by the ROM firmware just prior to the time that the application software is loaded, and is retained as nonvolatile information in the absence of V CC by the lithium-backup circuits. After the application software loading is complete, the key is protected by setting the on-chip security lock, which is also retained as nonvolatile information in the absence of V CC. Any attempt to tamper with the key word and, thereby, gain access to the true program/data SRAM contents results in the erasure of the key word as well as the SRAM contents. During execution of the application software, logical addresses on the DS5003 that are generated from the program counter or data pointer registers are encrypt- ed before they are presented on the byte-wide address bus. Op codes and data are read back and decrypted before they are operated on by the CPU. Similarly, data values written to the external NV SRAM storage during program execution are encrypted before they are pre- sented on the byte-wide data bus during the write oper- ation. This encryption/decryption process is performed in real time such that no execution time is lost, so the operation of the encryptor circuitry is transparent to the application software. The DS5003’s security features are always enabled. DS5003 Secure Microprocessor Chip

Figure 8. Block Diagram

When the application software is executed, the DS5003’s internal CPU operates as normal. Logical addresses are calculated for op code fetch cycles and also data read and write operations. The DS5003 can perform address encryption on logical addresses as they are generated internally during the normal course of program execution. In a similar fashion, data is manipulated by the CPU in its true representation. However, data is also encrypted when it is written to the external program/data SRAM, and is restored to its original value when it is read back. When an application program is stored in the previously described format, it is virtually impossible to disassem- ble op codes or to convert data back into its true repre- sentation. Address encryption has the effect that the op codes and data are not stored in the contiguous form in which they were assembled, but rather in seemingly random locations in memory. This effect makes it virtu- ally impossible to determine the normal flow of the pro- gram. As an added protection measure, the address encryptor also generates dummy read-access cycles whenever time is available during program execution. Dummy Read Cycles Like the DS5002FP, the DS5003 generates a dummy read-access cycle to nonsequential addresses in exter- nal SRAM memory whenever time is available during program execution. This action further complicates the task of determining the normal flow of program execu- tion. During these pseudorandom dummy cycles, the SRAM is read to all appearances, but the data is not used internally. Through the use of a repeatable exchange of dummy and true read cycles, it is impossi- ble to distinguish a dummy cycle from a real one. Encryption Algorithm The DS5003 incorporates a proprietary hardware algo- rithm that performs the scrambling of address and data on the byte-wide bus to the SRAM. Improvements include the following:

• 64-bit encryption key (protected by the security lock function).
• Incorporation of DES-like operations to provide a greater degree of nonlinearity.
• Customizable encryption. Encryption Key As previously described, the on-chip 64-bit encryption key is the basis of both the address and data encryptor circuits. When the loader is given certain commands, the key is generated from an on-chip hardware ran- dom-number generator. This action is performed just prior to actually loading the code into the external SRAM. This scheme prevents characterization of the encryption algorithm by continuously loading new, known keys. It also frees the user from the burden of protecting the key selection process. The random-number generator circuit uses the asyn- chronous frequency differences of two internal ring oscillators and the processor master clock (determined by XTAL1 and XTAL2). As a result, a true random num- ber is produced. Vector RAM A 48-byte vector RAM area is incorporated on-chip, and is used to contain the reset and interrupt vector code in the DS5003. It is included in the architecture to help ensure the security of the application program. If reset and interrupt vector locations were accessed from the external nonvolatile program/data RAM during the execution of the program, it would be possible to determine the encrypted value of known addresses. This could be done by forcing an interrupt or reset con- dition and observing the resulting addresses on the byte-wide address/data bus. For example, it is known that when a hardware reset is applied, the logical pro- gram address is forced to location 0000h and code is executed starting from this location. It would then be possible to determine the encrypted value (or physical address) of the logical address value 0000h by observ- ing the address presented to the external SRAM follow- ing a hardware reset. Interrupt vector address relationships could be determined in a similar fashion. By using the on-chip vector RAM to contain the inter- rupt and reset vectors, it is impossible to observe such relationships. The vector RAM eliminates the unlikely possibility that an application program could be deci- phered by observing vector address relationships. Note that the dummy accesses mentioned are conducted while fetching from vector RAM. The vector RAM is automatically loaded with the user’s reset and interrupt vectors from the Intel hex file during bootstrap loading. Security Lock Once the application program has been loaded into the DS5003’s external and vector RAM, the security lock can be enabled by issuing the Z command in the boot- strap loader. While the security lock is set, no further access to program/data information is possible by the on-chip ROM. Access is prevented by both the boot- strap loader firmware and the DS5003 encryptor cir- cuits. Access to the SRAM can only be regained by clearing the security lock by the U command in the bootstrap Secure Microprocessor Chip

the loader creates and loads a new random key. resulting in the loss of data in external SRAM. through special processing of the microcontroller die. saved as a potential word for the 64-bit encryption key. ty lock bit through the U command. C Return CRC-16 of the program/data SRAM. G Get data from P0, P1, P2, and P3. P Put data into P0, P1, P2, and P3. R Read status of SFRs (MCON, RPCTL, MSL). T Trace (echo) incoming Intel hex code. Table 1. Serial Bootstrap Loader

Figure 12. Memory Map with PES = 1

13 VCC

54 VLI

32 VCC

16 GND

22 CS1

2 A16

31 A15

Figure 13. Connection to 128kB x 8 SRAM

The DS5003 monitors V CC to provide power-fail reset, early warning power-fail interrupt, and switchover to lithium backup. It uses an internal bandgap reference in determining the switch points. These are called V PFW, VCCMIN, and V LI, respectively. When V CC drops below V PFW, the DS5003 performs an interrupt and vectors to location 2Bh if the power-fail warning was enabled. Full processor operation continues regard- less. When power falls further to V CCMIN, the DS5003 invokes a reset state. No further code execution is per- formed unless power rises back above V CCMIN . All decoded chip enables and the R/ W signal go to an inactive (logic 1) state. V CC is still the power source at this time. When V CC drops further to below V LI, internal circuitry switches to the lithium cell for power. The majority of internal circuits are disabled and the remain- ing nonvolatile states are retained. Any devices con- nected to V CCO are powered by the lithium cell at this time. V CCO is at the lithium battery voltage minus approximately 0.45V (less a diode drop), depending on the load. Low-power SRAMs should be used for this reason. When using the DS5003, the user must select the appropriate battery to match the SRAM data-reten- tion current and the desired backup lifetime. Note that the lithium cell is only loaded when V CC < V LI. The Secure Microcontroller User’s Guide has more informa- tion on this topic. The trip points V CCMIN and VPFW are listed in the electrical specifications. DS5003 Secure Microprocessor Chip DS5003 BD7–BD0 BA14–BA0 2CE2 74CE1 10R/W +5V +5V +3V LITHIUM PORT 0 PORT 1 PORT 2 PORT 3

28 VCC

14 GND

A14–A0 D7–D0 A14–A0 D7–D0 Figure 14. Connection to 64kB x 8 SRAM

Package Information

(For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

80 MQFP — 56-G4005-001

Secure Microprocessor Chip Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. BA11 P0.5/AD5 PE1 P0.6/AD6 BA10 P0.7/AD7 CE1 N.C. CE1N BD7 ALE 64 P2.6/A14 CE3 CE4 BD3 P2.5/A13 BD2 P2.4/A12 BD1 P2.3/A11 BD0 VLI SDI GND P2.2/A10 P2.1/A9 P2.0/A8 XTAL1 XTAL2 P3.7/RD P3.6/WR P3.5/T1 PF VRST P3.4/T0 P0.4/AD4 CE2 PE2 BA9 P0.3/AD3 BA8 P0.2/AD2 BA13 P0.1/AD1 R/W P0.0/AD0 VCCO VCC MSEL P1.0 BA14 P1.1 BA12 P1.2 BA7 P1.3 PE3 PE4 BA6 BD6 N.C. BD5 P2.7/A15 BD4 P1.4 BA5 P1.5 BA4 P1.6 BA3 P1.7 PROG BA2 RST BA1 P3.0/RXD BA0 P3.1/TXD P3.2/INT0 P3.3/INT1 MQFP DS5003 TOP VIEW Pin Configuration