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Technical content
Features
♦ Frequency Margining: ±5% ♦ Nominal Clock Output Frequencies: 125MHz, 133.33MHz, and 200MHz ♦ Jitter < 0.9ps RMS from 12kHz to 20MHz ♦ LVPECL or LVDS Output ♦ 3.3V Operating Voltage ♦ Operating Temperature Range: -40°C to +85°C ♦ Supply Current: < 100mA at 3.3V ♦ Excellent Power-Supply Noise Rejection ♦ 5mm x 3.2mm Ceramic LCCC Package ♦ Output Enable/Disable DS4M125/DS4M133/DS4M200 3.3V Margining Clock Oscillator with LVPECL/LVDS Output
Ordering Information
0.01μF0.1μF 100Ω OE MS GND VCC OUTP OUTN LVPECL OPTION 0.01μF0.1μF 50Ω 50Ω PECL_BIAS AT VCC - 2.0V Typical Operating Circuit Rev 0; 12/07 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART TEMP RANGE PIN-PACKAGE DS4M125P+33 -40 °C to +85°C 10 LCCC DS4M125D+33 -40 °C to +85°C 10 LCCC DS4M133P+33 -40 °C to +85°C 10 LCCC DS4M133D+33 -40 °C to +85°C 10 LCCC DS4M200P+33 -40 °C to +85°C 10 LCCC DS4M200D+33 -40 °C to +85°C 10 LCCC +Denotes a lead(Pb)-free package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes. Pin Configuration and Selector Guide appear at end of data sheet.
3.3V Margining Clock Oscillator with LVPECL/LVDS Output ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Soldering Temperature IPC/JEDEC J-STD-020 Specification. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Voltage Range V CC (Note 1) 3.135 3.3 3.465 V ICC_D LVDS, output loaded or unloaded 52 75 ICC_PU LVPECL, output unloaded 49 70 Operating Current ICC_PI LVPECL, output loaded 74 100 mA Inactive Current I CC_OEZ V OE = VIL 52 85 mA OUTPUT FREQUENCY SPECIFICATIONS DS4M125 MS = 0, OE = 1 125 DS4M133 MS = 0, OE = 1 133.33 Frequency DS4M200 fO MS = 0, OE = 1 200 MHz Frequency Stability fTOTAL/fO Over temperature range, aging, load, supply, and initial tolerance (Note 3) -50 +50 ppm Frequency Stability Over Temperature fTEMP/f V CC = 3.3V -35 +35 ppm Initial Tolerance fINITIAL/fV V CC = 3.3V, TA = +25 °C ±20 ppm Frequency Change Due to VCC fVCC/f V CC = 3.3V ±5% -3 +3 ppm/V Frequency Change Due to Load Variation fLOAD/fO ±10% variation in termination resistance ±1 ppm Aging (15 Years) fAGING -7 +7 ppm Phase Jitter J RMS Integrated phase RMS; 12kHz to 80MHz, VCC = 3.3V, TA = +25 °C < 0.9 ps Accumulated Deterministic Jitter Due to Reference Spurs No margin 155.52MHz output 0.6 ps 10kHz 12.9 100kHz (Note 4) 26.3 200kHz (Note 4) 20.1 Accumulated Deterministic Jitter Due to Power-Supply Noise 1MHz (Note 4) 6.4 ps Startup Time t STRT 1.0 ms Frequency Switch Time t SWITCH 0.5 ms Input-Voltage High (OE) V IH (Note 5) 0.7 x VCC V CC V
3.3V Margining Clock Oscillator with LVPECL/LVDS Output ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input-Voltage Low (OE) V IL (Note 5) 0 0.3 x VCC V Input-Leakage High (OE) I LEAKH OE voltage = VCC -5 +5 μA Input-Leakage Low (OE) I LEAKL OE voltage = GND -20 -50 μA Input-Leakage High (MS) I LEAKH MS voltage = VCC 20 50 μA Input-Leakage Low (MS) I LEAKL MS voltage = GND -5 +5 μA Input Voltage: High Level (MS) V IH (Note 5) 0.75 x VCC + 0.15V V CC V Input Voltage: Mid Level (MS) V IM (Note 5) 0.25 x VCC + 0.15V 0.75 x VCC - 0.15V V Input Voltage: Low Level (MS) V IL (Note 5) 0 0.25 x VCC - 0.15V V LVDS Output High Voltage V OH 100 differential load (Notes 2, 5) 1.475 V Output Low Voltage V OL 100 differential load (Notes 2, 5) 0.925 V Differential Output Voltage |VOD| 100 differential load 250 425 mV Change in VOD for Complementary States |VOD| 100 differential load 25 mV Offset Output Voltage V OS 100 differential load (Note 2) 1.125 1.275 V Change in VOS for Complementary States |VOS| 100 differential load 150 mV Differential Output Impedance R OLVDS 80 140 LVSSLVDSO OUTN or OUTP shorted to ground and measure the current in the shorting path 40 Output Current LLVDSO OUTN and OUTP shorted together and measure the change in I CC 6.5 mA Output Rise Time (Differential) t RLVDSO 20% to 80% 175 ps Output Fall Time (Differential) t FLVDSO 80% to 20% 175 ps Duty Cycle D CYCLE_LVDS 45 55 % Propagation Delay from OE Going LOW to Logical 1 at OUTP tPA1 (Figure 2) 200 ns Propagation Delay from OE Going HIGH to Output Active tP1A (Figure 2) 200 ns
3.3V Margining Clock Oscillator with LVPECL/LVDS Output ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVPECL Output High Voltage (Note 2) V OH Output connected to 50 at PECL_BIAS at VCC - 2.0V VCC - 1.085 VCC - 0.88 V Output Low Voltage (Note 2) V OL Output connected to 50 at PECL_BIAS at VCC - 2.0V VCC - 1.825 VCC - 1.62 V Differential Voltage V DIFF_PECL Output connected to 50 at PECL_BIAS at VCC - 2.0V 0.595 0.710 V Rise Time t R-PECL 20% to 80% 200 ps Fall Time t F-PECL 80% to 20% 200 ps Duty Cycle D CYCLE_PECL 45 55 % Propagation Delay from OE Going LOW to Output Three-Stated tPAZ (Figure 3) 200 ns Propagation Delay from OE Going HIGH to Output Active tPZA (Figure 3) 200 ns Note 1: Limits at -40°C are guaranteed by design and are not production tested. Typical values are at +25°C and 3.3V, unless otherwise noted. Note 2: AC parameters are guaranteed by design and characterization and are not production tested. Note 3: Frequency stability is calculated as: ΔfTOTAL = ΔfINITIAL + ΔfTEMP + (ΔfVCC x 0.165) + ΔfLOAD + ΔfAGING. Note 4: Supply induced jitter is measured with a 50mVP-P sine wave forced on VCC. Deterministic jitter is calculated by measuring the power of the resulting tone seen on a spectrum analyzer. Note 5: Voltage referenced to ground. SINGLE-SIDEBAND PHASE NOISE AT f O = fNOM (dBc/Hz)fM = 125MHz 133.33MHz 200MHz 10Hz -70 -75 -70 100Hz -100 -105 -100 1kHz -118 -121 -115 10kHz -118 -122 -117 100kHz -124 -126 -122 1MHz -142 -141 -138 10MHz -150 -150 -150 20MHz -150 -150 -150 SINGLE-SIDEBAND PHASE NOISE AT fO = fNOM
3.3V Margining Clock Oscillator with LVPECL/LVDS Output Pin Description PIN NAME FUNCTION 1 OE Active-High Output Enable. Has an internal pullup 100k resistor. 2 MS Margin Select. Three-level input with a 100k pulldown resistor.
3 GND Ground
4 OUTP Positive Output for LVPECL or LVDS
5 OUTN Negative Output for LVPECL or LVDS
6 VCC Supply Voltage
7–10 N.C. No Connection. Must be floated. — EP Exposed Paddle. The exposed pad must be used for thermal relief. This pad must be connected to ground. FREQUENCY vs. TEMPERATURE DS4M125/DS4M133/DS4M200 toc01 TEMPERATURE (°C) fOUT DEVIATION (ppm) 8060-20 0 20 40 -13 -10 -15 -40 fO + 5% fO - 5% fO CURRENT vs. TEMPERATURE DS4M125/DS4M133/DS4M200 toc02 TEMPERATURE (°C) ICC (mA) 8060-20 0 20 40 -40 Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.)
3.3V Margining Clock Oscillator with LVPECL/LVDS Output Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 © 2007 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. Selector Guide PART FREQUENCY (NOM) (MHz) OUTPUT TYPE TOP MARK DS4M125P+33 125 LVPECL MEP DS4M125D+33 125 LVDS MED DS4M133P+33 133.33 LVPECL MFP DS4M133D+33 133.33 LVDS MFD DS4M200P+33 200 LVPECL MJP DS4M200D+33 200 LVDS MJD +Denotes a lead-free package. The lead finish is JESD97 cate- gory e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes. A + appears anywhere on the top mark. Chip Information SUBSTRATE CONNECTED TO GROUND PROCESS: BiPOLAR SiGe THETA-JA (°C/W) TOP VIEW OE MS N.C. N.C. N.C. N.C. GND VCC OUTN OUTP DS4M125/ DS4M133/ DS4M200 *EP *EXPOSED PAD Pin Configuration Thermal Information
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.