DS4830A

DS4830A MAXIM | Alldatasheet

Document overview

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Technical content

The DS4830A is a low-power, 16-bit microcontroller with a unique peripheral set supporting optical applications that require high-resolution conversion of many analog sig - nals and digital signal processing (DSP) of those signals, high-speed data communication to an external host, and ultra-low power dissipation. A wide variety of optical trans- ceiver controller applications is supported without need of external circuitry, thereby minimizing cost and PCB area. Power dissipation and throughput are optimized through the use of a programmable round-robin analog-to-digital converter (ADC) and 10-bit fast comparator, which oper - ate completely independently of the core and significantly relieve core overhead. A dual multiply/accumulate (MAC) is included to minimize interrupt service timing/design complexity. Ten 16-bit PWM channels are included to pro- vide an unprecedented level of precision in digital power- control applications. The DS4830A provides a complete optical control, cali - bration, and monitor solution compatible with SFF-8472. Additional resources include a fast/accurate ADC, fast comparators with an internal comparison digital-to-analog converter (DAC), eight independent 12-bit DACs, an accurate internal temperature sensor, two fast sample/ holds with various programmable options, and a multi - protocol serial master/slave interface. An independent, 400kHz-compliant, slave I 2C interface with four configu - rable slave addresses facilitates communication to a host, in addition to password-protected in-system programming of the on-chip flash. Extensive design-in and applications support are available, including comprehensive user’s and programmer’s guides, complete reference designs with documented code, and in-depth application notes showing numerous code exam- ples in both C and assembly language. Firmware develop- ment is supported by third-party vendors.

Applications

• PON Diplexers and Triplexers: GPON, 10GEPON, XPON OLT, ONU
• Optical Transceivers: XFP, SFP, SFP+, QSFP+, CSFP, 40G, 100G Benefits and Features
• 16-Bit Low Power Microcontroller
• Slave Communication Interface: 400kHz without Clock Stretching I2C-Compatible 2-Wire or SPI
• Master Communication Interface: 400kHz I2C- Compatible 2-Wire, SPI, or Maxim 3-Wire Laser Driver
• Pin-Compatible with DS4830
• 32KWords Flash Program Memory
• 2KWords Data RAM
• 4KWords ROM Memory
• 32-Level Stack Memory
• 2.85V to 3.63V Operating Voltage Range
• 8 Independent 12-Bit Voltage DACs with 2.5V Internal Reference or External Reference
• 10 x 16-Bit PWM Channels
• Supports 4-Channel TECC H-Bridge Control
• Boost/Buck DC-DC Control
• 1MHz Switching Frequency
• 13-Bit ADC with 26-Input Mux
• 40ksps
• Individual Channel Averaging Option
• Two Independent Sample/Holds with Individual Channel Averaging Option
• 1V Full Scale
• 300ns Sample Time
• Fast Temperature Measurement with Averaging Option
• Internal Temperature Sensor, ±2°C
• 10-Bit Fast Comparator with 16 Input Mux
• 31 GPIO Pins
• Internal 20MHz Oscillator
• Up to 133MHz External Clock for PWM and Timers
• Two 16-Bit Timers and One Programmable Watchdog Timer
• Maskable Interrupt Sources
• Fast Hardware CRC-8 for Packet Error Checking (PEC)
• I2C and JTAG Bootloader
• Four Software Interrupts
• Supply Voltage Monitor (SVM) and Brownout Monitor
• JTAG Port with In-System Debug and Programming
• Low Power Consumption (16mA) with All Analog Active
• 5mm x 5mm, 40-Pin TQFN Package Ordering Information appears at end of data sheet. DS4830A Optical Microcontroller 19-6870; Rev 1; 1/17

All Other Pins to GND except Continuous Power Dissipation (TA = +70°C) *Subject to not exceeding +3.97V. Recommended Operating Conditions (TA = -40ºC to +85ºC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VDD Operating Voltage VDD (Note 2) 2.85 3.63 V Input Logic-High VIH 0.7 x VDD VDD + 0.3 V Input Logic-Low VIL -0.3 0.3 x VDD V Package Code T4055+2 Outline Number 21-0140 Land Pattern Number 90-0016 DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 2 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Package Information

40 TQFN

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current ICPU CPU mode, all analog disabled (Notes 3, 4) 7.25 mA IFASTCOMP 2.5 ISAMPLEHOLDS Both sample/hold 1.5 IADC 2.5 IDACS Per channel (Note 5) 0.7 Brownout Voltage VBO Monitors VDD (Note 2) 2.62 V Brownout Hysteresis VBOH Monitors VDD (Note 2) 110 mV 1.8V Regulator Initial Voltage VREG18 (Note 2) 1.71 1.8 1.89 V 2.74V Regulator Initial Voltage VREG270 (Note 2) 2.68 2.74 2.80 V Clock Frequencies fOSC- PERIPHERAL TA = +25°C (Note 6) 20 MHz fMOSC-CORE TA = +25°C (Note 6) 10 Clock Error fERR TA = -40°C to +85°C 5 % External Clock Input fXCLK 20 133 MHz Voltage Range: GP[15:0], SHEN, DACPW[7:0], REFINA, REFINB VRANGE (Note 2) -0.3 VDD + 0.3 V Output Logic-Low: All Pins VOL1 IOL = 4mA (Note 2) 0.4 V Output Logic-High: All Pins Except GP2, GP3, SCL, SDA VOH1 IOH = -4mA (Note 2) VDD - 0.5 V Pullup Current: All Pins Except GP2, GP3, SCL, SDA IPU1 VPIN = 0V 55 µA GPIO Drive Strength, Extra Strong Outputs: GP0, GP1, MCS, PWM8, PWM9 RHISt 9 22 Ω RLOSt 8 22 GPIO Drive Strength, Strong Outputs: MSDI, DACPW3, DACPW6 RHIA 17 32 Ω RLOA 12 32 GPIO Drive Strength, Excluding Strong GPIO Outputs RHIB 27 46 Ω RLOB 31 52 DAC DAC Resolution DACR 12 Bits DAC Internal Reference Accuracy DACREFACC (Note 5) -1.25 +1.25 % DAC Internal Reference Power-Up Speed tDACPUP 99% settled 10 µs Reference Input Full-Scale Range (REFINA, REFINB) REFFS 1 2.5 V DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 3

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC Operating Current IDACS Per channel See the DC Electrical Characteristics mA DAC Integral Nonlinearity DACINL (Note 5) 5 LSB DAC Differential Nonlinearity DACDNL Not production tested (Notes 5, 7) ±1 LSB DAC Offset VOFFSET-DAC At code “0” 0 18 mV DAC Source Load Regulation IDAC-SOURCE 0 to full-scale output, VDD = 3.3V 3 mV/mA DAC Sink Capability and Sink Load Regulation RDAC-SINK 0 to 0.5V output, limited by output buffer impedance 500 Ω IDAC-SINK 0.5V to full-scale output 5 mV/mA DAC Settling Time tDAC Output load capacitance between 33pF to 270pF, from 10% to 90% 10 µs FAST COMPARATOR Fast Comparator Resolution FCR 10 Bits Fast Comparator Internal Reference Accuracy FCREFTC ±0.2 % Fast Comparator Operating Current IFASTCOMP See the DC Electrical Characteristics mA Fast Comparator Full Scale VFS-COMP TA = +25°C 2.42 V Fast Comparator Integral Nonlinearity INL Differential mode, 2.2nF capacitor at input (Note 7) ±2 LSB Fast Comparator Differential Nonlinearity DNL Differential mode, 2.2nF capacitor at input (Note 8) ±0.5 LSB Fast Comparator Offset VOFFSET- COMP ±2 LSB Fast Comparator Input Impedance RIN-COMP 15 MΩ Fast Comparator Input Capacitance CIN-COMP 4 pF Fast Comparator Sample Rate fCOMP 625 ksps ADC ADC Resolution ADCR VFS ≥ 1.2V (Note 9) 13 Bits ADC Internal Reference Accuracy ADCREFACC -0.85 +0.85 % Reference Output Accuracy REFOUT 10kΩ < REFOUT load, CMAX= 2.2nF 1.214 1.225 1.236 V ADC Operating Current IADC See the DC Electrical Characteristics mA ADC Full-Scale 1 VFS-ADC1 Factory calibrated 1.2 V ADC Full-Scale 2 VFS-ADC2 Factory calibrated 0.6 V ADC Full-Scale 3 VFS-ADC3 Factory calibrated 2.4 V DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 4

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ADC Full-Scale 4 VFS-ADC4 Factory calibrated 6.55 V ADC Integral Nonlinearity ADCINL 13-bit, TA = +25°C, VDD = 3.3V, VFS-ADC3 (Note 10) ±3 LSB ADC Differential Nonlinearity ADCDNL VFS ≥ 1.2V ±0.5 LSB ADC Sample-Sample Deviation ADC full scale set to VFS-ADC3 ±2 LSB ADC Offset VOFFSET-ADC 13-bit, VFS ≥ 1.2V -8 +1 +8 LSB ADC[15:0] Input Resistance RIN-ADC 15 MΩ ADC Sample Rate fSAMPLE (Note 11) 40 ksps ADC Temperature Conversion Time tTEMP With default ADC clock 41 µs Internal Temperature Measurement Error TINTERR (Note 12) ±2 °C SAMPLE/HOLD Sample/Hold Input Range VSHP ADC-SHN[1:0] = GND 1 V Sample/Hold Capacitance CSH ADC-SHP[1:0] to ADC-SHN[1:0] 5 pF Sample Input Leakage ISHLKG ADC-SHP[1:0] and ADC-SHN[1:0] 1.2 µA Sample Time ts ADC-SHP[1:0] and ADC-SHN[1:0] connected to 50Ω voltage source 300 ns Sample Conversion Complete th (Note 13) 320 µs Sample Offset VSH-OFF Measured at 10mV -10 -1.6 7 mV Sample Error ERRSH VADC-SHP_ to VADC-SHN_ = 300mV, ts = 300ns, driven with 50Ω voltage source -4 +4 % Sample Discharge Strength RDIS ADC-SHP[1:0] or ADC-SHN[1:0] to GND 50 Ω FLASH MEMORY Flash Erase Time (Note 14) tME Mass erase 25 ms tPE Page erase 25 Flash Programming Time per Word tPROG (Notes 14, 15) 75 µs Flash Programming Temperature TFLASH -40 +85 °C Flash Endurance nFLASH TA = +50°C (Note 7) 20,000 Write Cycles Data Retention tRET TA = +50°C (Note 7) 100 Years DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 5

(VDD = 2.85V to 3.63V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I2C COMPATIBLE INTERFACE (See Figure 1) SCL/MSCL Clock Frequency fSCL Timeout not enabled 400 kHz SCL Bootloader Clock Frequency fSCL:BOOT 100 kHz Bus Free Time Between a STOP and START Condition tBUF 1.3 µs Hold Time (Repeated) START Condition tHD:STA (Note 16) 0.6 µs Low Period of SCL/MSCL Clock tLOW 1.3 µs High Period of SCL/MSCL Clock tHIGH 0.6 µs Setup Time for a (Repeated) START Condition tSU:STA 0.6 µs Data Hold Time (Note 17) tHD:DAT Receive 0 ns Transmit 300 Data Setup Time tSU:DAT 100 ns SCL/MSCL, SDA/MSDA Capacitive Loading CB (Note 18) 400 pF Rise Time of Both SDA and SCL Signals tR (Note 18) 20 + 0.1CB 300 ns Fall Time of Both SDA and SCL Signals tF (Note 18) 20 + 0.1CB 300 ns Setup Time for STOP Condition tSU:STO 0.6 µs Spike Pulse Width That Can Be Suppressed by Input Filter tSP (Note 19) 50 ns SCL/MSCL and SDA/MSDA Input Capacitance CBIN 5 pF SMBusTimeout tSMBUS 30 ms JTAG INTERFACE (See Figure 2) JTAG Logic Reference VREF VDD/2 V TCK High Time tTH 0.5 µs TCK Low Time tTL 0.5 µs TCK Low to TDO Output tTLQ 0.125 µs TMS, TDI Input Setup to TCK High tDVTH 0.25 µs TMS, TDI Input Hold after TCK High tTHDX 0.25 µs DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 6

(VDD = 2.85V to 3.63V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3-WIRE DIGITAL INTERFACE (See Figure 3) MSCL Clock Frequency fSCLOUT 1000 kHz MSCL Duty Cycle t3WDC 50 % MSDIO Setup Time tDS 100 ns MSDIO Hold Time tDH 100 ns MCS Pulse-Width Low tCSW 500 ns MCS Leading Time Before the First MSCL Edge tL 500 ns MCS Trailing Time After the Last MSCL Edge tT 500 ns MSDIO, MSCL Load CB3W Total bus capacitance on one line 10 pF SPI DIGITAL INTERFACE SPECIFICATION (See Figure 4 and Figure 5) SPI Master Operating Frequency 1/tMSPICK (Note 14) 5 MHz SPI Slave Operating Frequency 1/tSSPICK (Note 14) 2.5 MHz SPI I/O Rise/Fall Time tSPI_RF CL = 15pF, pullup = 560Ω 25 ns MSPICK Output Pulse-Width High/Low tMCH, tMCL tMSPICK/2 - tSPI_RF ns MSPIDO Output Hold After MSPICK Sample Edge tMOH tMSPICK/2 - tSPI_RF ns MSPIDO Output Valid to MSPICK Sample Edge (MSPIDO Setup) tMOV tMSPICK/2 - tSPI_RF ns MSPIDI Input Valid to MSPICK Sample Edge (MSPIDI Setup) tMIS 2tSPI_RF ns MSPIDI Input to MSPICK Sample Edge Rise/Fall Hold tMIH 0 ns MSPICK Inactive to MSPIDO Inactive tMLH tMSPICK/2 - tSPI_RF ns SSPICK Input Pulse-Width High/ Low tSCH, tSCL tSSPICK/2 ns SSPICS Active to First Shift Edge tSSE tSPI_RF ns SSPIDI Input to SSPICK Sample Edge Rise/Fall Setup tSIS tSPI_RF ns DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 7

Note 1: Limits are 100% production test at T A = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Note 2: All voltages referenced to GND. Currents entering the IC are specified positive and currents exiting the IC are negative. Note 3: Maximum current assuming 100% CPU duty cycle. Note 4: The value does not include current in GPIO, SCL, SDA, MSDIO, MSDI, MSCL, REFINA, and REFINB. Note 5: Using 2.5V internal reference. Note 6: There is one internal oscillator. The oscillator (peripheral clock) goes through a 2:1 divider to create the core clock. Note 7: Guaranteed by design. Note 8: Tested at worse-case positions. Note 9: Default or slower ADC clock settings. Note 10: Computed using end-point best fit and histogram method. Note 11: ADC conversions are delayed up to 1.6µs if the fast comparator is sampling the selected ADC channel. This can cause a slight decrease in the ADC sampling rate. Note 12: Temperature readings averaged 64 times. Note 13: Time from valid sample to ADC data available (without any averaging). Note 14: Minimum and maximum timings depend upon f MOSC-CORE error. Note 15: Programming does not include overhead associated with the utility ROM interface. Note 16: fSCL must meet the minimum clock low time plus the rise/fall times. Note 17: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the V IH:MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 18: CB—total capacitance of one bus line in pF. Note 19: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant. (VDD = 2.85V to 3.63V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SSPIDI Input from SSPICK Sample Edge Transition Hold tSIH tSPI_RF ns SSPIDO Output Valid After SSPICK Shift Edge Transition tSOV 2tSPI_RF ns SSPICS Inactive tSSH tSSPICK + tSPI_RF ns SSPICK Inactive to SSPICS Rising tSD tSPI_RF ns SSPIDO Output Disabled After SSPICS Edge Rise tSLH 2tSSPICK + 2tSPI_RF ns DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 8

Figure 5. SPI Slave Communications Timing Diagram

(TA = +25°C, unless otherwise noted.) 7.05 7.1 7.15 7.2 7.25 7.3 IDD CPU (mA) VDD (V) IDD CPU vs. VDD toc01 TA = +25oC 5.65 5.7 5.75 5.8 5.85 5.9 5.95 6.05 6.1 IDD DAC (mA) VDD (V) IDDDAC vs. VDD toc02 TA = +25oC 2.7 2.725 2.75 2.775 2.8 2.825 2.85 IDD ADC(mA) VDD (V) IDD ADC vs. VDD toc03 TA = +25oC 2.3 2.33 2.36 2.39 2.42 2.45 2.48 IDD FASTCOMP(mA) VDD (V) IDD FASTCOMP vs. VDD toc04 TA = +25oC 2.3 2.33 2.36 2.39 2.42 2.45 2.48 IDD FASTCOMP(mA) VDD (V) IDD FASTCOMP vs. VDD toc04 TA = +25oC -2.5 -1.5 -0.5 0.5 ADC INL (LSB) INPUT VOLTAGE (V) ADC INL vs. INPUT VOLTAGE toc06 TA = +25oC DS4830A Optical Microcontroller Maxim Integrated │ 12 www.maximintegrated.com Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.) -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0 1023 2046 3069 4092 DAC DNL(LSB) DAC SETTING (COUNT) DAC DNL vs. DAC SETTING toc07 No Load, VDD = 3.3V, TA = +25oC 0 1023 2046 3069 4092 DAC INL(LSB) DAC SETTING DAC INL vs. DAC SETTING toc08 No Load, 3.3V, TA = +25oC -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 0 127 254 381 508 635 762 889 1016 FAST COMP DNL (LSB) FAST COMP SETTING FAST COMP DNL vs. FAST COMP SETTING toc09 3.3V, TA = +25oC -1.4 -1.2 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0 127 254 381 508 635 762 889 1016 FAST COMP INL (LSB) FAST COMP SETTING FAST COMP INL vs. FAST COMP SETTING toc10 3.3V, TA = +25oC DS4830A Optical Microcontroller Maxim Integrated │ 13 www.maximintegrated.com Typical Operating Characteristics (continued)

(5mm x 5mm) TOP VIEW SCL GP0 REG274 GP1 VDD RST MCS MSDI MSDIO VDD PWM9 PWM8 SHEN GP15 DACPW2 45 67 27282930 26 24 23 22 DACPW3 DACPW4 GP11 GP10 REG18 GP9 SDA MSCL 37DACPW5 GP8 DACPW6 REFINB DACPW7 GP7 GP6 GP5 EP+ DACPW1 GP12DACPW0

20 GP13

STRUCTURE(S) OUTPUT STRUCTURE POWER-ON STATE SELECTABLE FUNCTIONS (FIRST COLUMN IS DEFAULT FUNCTION) PORT

1 RST Digital None High

Impedance RST — — — —

2 SCL Digital Open Drain High

SSPICK — — —

3 SDA Digital Open Drain High

SSPIDI — — —

4 GP0 ADC/Digital Input Push-Pull,

Extra Strong 55µA Pullup ADC-S0 ADC- D0P PWM- ALT0 — P2.0 5 REG274 VREG None 2.74V Only function is for bypass capacitors for 2.74V internal regulator —

6 GP1 ADC/Digital Input Push-Pull,

Extra Strong 55µA Pullup ADC-S1 ADC- D0N PWM- ALT1 REFOUT P2.1

7 VDD

Voltage Supply, ADC Input None VDD ADC-VDD — — — —

8 GP2 SH Input, ADC Input None High

D1P — —

9 GP3 SH Input, ADC Input None High

D1N — — DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 14 Pin Description Pin Configuration

STRUCTURE(S) OUTPUT STRUCTURE POWER-ON STATE SELECTABLE FUNCTIONS (FIRST COLUMN IS DEFAULT FUNCTION) PORT

10 GP4 ADC/Digital Input Push-Pull 55µA Pullup JTAG TCK ADC-S4 ADC-

D2P — P6.0

11 GP5 ADC/Digital Input Push-Pull 55µA Pullup JTAG TDI ADC-S5 ADC-

D2N — P6.1

12 GP6 ADC/Digital Input Push-Pull 55µA Pullup ADC-S6 ADC-

SSPIDO P2.2

13 GP7 ADC/Digital Input Push-Pull 55µA Pullup ADC-S7 ADC-

SSPICS P2.3

14 GP8 ADC/Digital Input Push-Pull 55µA Pullup ADC-S8 ADC-

D4P — — P2.4

15 GP9 ADC/Digital Input Push-Pull 55µA Pullup ADC-S9 ADC-

D4N — — P2.5 16 REG18 VREG None 1.8V Pin for 1.8V regulator bypass capacitor —

17 GP10 ADC/Digital Input Push-Pull 55µA Pullup JTAG TMS ADC-

D5P — P6.2

18 GP11 ADC/Digital Input Push-Pull 55µA Pullup JTAG TDO ADC-

D5N — P6.3

19 GP12 SH Input, ADC/Digital

Input Push-Pull 55µA Pullup ADC-S12 ADC- SHP1 ADC- D6P — P0.0

20 GP13 SH Input, ADC/Digital

Input Push-Pull 55µA Pullup ADC-S13 ADC- SHN1 ADC- D6N — P0.1

21 GP14 ADC/Digital Input Push-Pull 55µA Pullup ADC-S14 ADC-

D7P SHEN1 — P0.2

22 GP15 ADC/Digital Input Push-Pull 55µA Pullup ADC-S15 ADC-

D7N — — P0.3 23 SHEN Digital Push-Pull 55µA Pullup SHEN0 — — — P6.4

24 MSDIO Digital Push-Pull 55µA Pullup 3-Wire Data

ALT4 P1.0

25 MSDI Digital Push-Pull,

Strong 55µA Pullup — — SPI MSPIDI PWM- ALT5 P1.3

26 MSCL Digital Push-Pull 55µA Pullup 3-Wire Clock

ALT6 P1.1

27 MCS Digital Push-Pull,

Extra Strong 55µA Pullup 3-Wire Chip Select MCS — SPI MSPICS PWM- ALT7 P1.2

28 VDD Voltage Supply None VDD ADC-VDD — — — —

29 PWM9 Digital Push-Pull,

Extra Strong 55µA Pullup PWM9 — — — P0.7

30 PWM8 Digital Push-Pull,

Extra Strong 55µA Pullup PWM8 — — — P0.6

31 REFINA Reference,

ADC/Digital Input Push-Pull 55µA Pullup ADC- REFINA — — — P2.6 DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 15 Pin Description (continued)

Note: Bypass VDD, REG274, and REG18 each with 1µF X5R and 10nF capacitors to ground. All input-only pins and open-drain out - puts are high impedance after V DD exceeds VBO and prior to code execution. Except for pins having DAC functions, pins configured as GPIO have a weak internal pullup at power-up. See the Selectable Functions table for more information. PIN NAME INPUT STRUCTURE(S) OUTPUT STRUCTURE POWER-ON STATE SELECTABLE FUNCTIONS (FIRST COLUMN IS DEFAULT FUNCTION) PORT

32 DACPW0 Digital Push-Pull High

DAC0, FS = REFINA or Internal Reference PWM0 — — P0.4

33 DACPW1 Digital Push-Pull High

DAC1, FS = REFINA or Internal Reference PWM1 — — P0.5

34 DACPW2 Digital Push-Pull High

DAC2, FS = REFINA or Internal Reference PWM2 CLKIN — P6.5

35 DACPW3 Digital Push-Pull,

DAC3, FS = REFINA or Internal Reference PWM3 — — P1.5

36 DACPW4 Digital Push-Pull High

DAC4, FS = REFINB or Internal Reference PWM4 I2C MSDA- ALT — P1.6

37 DACPW5 Digital Push-Pull High

DAC5, FS = REFINB or Internal Reference PWM5 I2C MSCL- ALT — P1.7

38 DACPW6 Digital Push-Pull,

DAC6, FS = REFINB or Internal Reference PWM6 — — P6.6

39 REFINB Reference, ADC/

Digital Input Push-Pull 55µA Pullup ADC- REFINB — — — P1.4

40 DACPW7 Digital Push-Pull High

DAC7, FS = REFINB or Internal Reference PWM7 — — P2.7 — EP Exposed Pad (Connect to GND) — GND — — — — — DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 16 Pin Description (continued)

ADC-D[7:0][P/N] Differential Inputs to ADC. Also used for sample/hold inputs. ADC-REFIN[A/B] REFINA and REFINB Monitor Inputs to ADC ADC-S[15:0] Single-Ended Inputs to ADC ADC-SH[P/N][1:0] Sample/Hold Inputs 1 and 0 ADC-VDD VDD Monitor Input to ADC DAC[7:0] Voltage DAC Outputs MSCL, MCS, MSDIO Maxim Proprietary 3-Wire Interface: MSCL (3-Wire Master Clock), MCS (Chip Select), MSDIO (3- Wire Data). Used to control the Maxim family of high-speed laser drivers. MSCL, MSDA I2C Master Interface: MSCL (I2C Master Clock), MSDA (I2C Master Data) MSCL-ALT, MSDA-ALT I2C Master Interface: MSCL-ALT (I2C Master Clock), MSDA (I2C Master Data) MSPICK, MSPICS, MSPIDI, MSPIDO SPI Master Interface: MSPICK (SPI Master Clock), MSPICS (Chip Select), MSPIDI (Master Data In), MSPIDO (Master Data Out) PWM[9:0] PWM Outputs PWM-ALT[9:0] PWM Alternate Outputs RST Used by JTAG and as Active-Low Reset for Device SCL, SDA I2C Slave Interface: SCL (I2C Slave Clock), SDA (I2C Slave Data). These also function as a password-protected programming interface. SHEN[1:0] Sample/Hold Trigger Inputs SSPICK, SSPICS, SSPIDI, SSPIDO SPI Slave Interface: SSPICK (Clock), SSPICS (Chip Select), SSPIDI (Data In), SSPIDO (Data Out). In SPI slave mode, the I2C slave interface is disabled. TCK, TDI, TDO, TMS JTAG Interface Pins. Also includes RST. REFOUT ADC Internal Reference Output DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 17 Selectable Functions

1.225V VREF 1.8V REGULATOR 2.74V REGULATOR 20MHz OSCILLATOR GP PORT2 GP PORT1 GP PORT0 GP PORT6 8K x 8 ROM I2C BOOTLOADER POR WATCHDOG 64K x 8 FLASH 4K x 8 SRAM 32 x 16 LEVEL STACK 16-BIT CPU AT 10MHz 24-CHANNEL SEQUENCER WITH AVERAGING CS SAMPLE AND HOLD 16-CHANNEL 625ksps SEQUENCER PROGRAMMABLE INTERRUPTS HIGH/LOW THRESHOLD COMPARISON I2C 400kHz MASTER SPI MASTER I2C 400kHz SLAVE SPI SLAVE 3W MASTER COMMUNICATION

18 SINGLE-ENDED/

8 DIFFERENTIAL INPUTS

VDD, DAC INTERNAL REF DS4830A ADC 40ksps 13-BIT 2 x HARDWARE 16-BIT MULTIPLIER AND 48-BIT ACCUMULATOR 10 x PWMs16-BIT 31 x GPIO 8 x DACs 12-BIT VOLTAGE INTERNAL REF DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 18 Block Diagram

The following is an introduction to the primary features of the DS4830A optical microcontroller. More detailed descriptions of the device features can be found in the DS4830A User’s Guide. Core Architecture The device employs a low-power, low-cost, high-perfor - mance, 16-bit RISC microcontroller with on-chip flash memory. It is structured on an advanced, 16 accumulator- based, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle without pipelining, since the instruction contains both the op code and data. The highly efficient core is supported by 16 accumulators and a 32-level hardware stack, enabling fast subroutine calling and task switching. Data can be quickly and efficiently manipulated with three internal data pointers. Multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. The data pointers can auto - matically increment or decrement following an operation, eliminating the need for software intervention. Module Information Top-level instruction decoding is extremely simple and based on transfers to and from registers. The registers are organized into functional modules, which are in turn divided into the system register and peripheral register groups. Peripherals and other features are accessed through peripheral registers. These registers reside in modules 0–5. The following provides information about the specific module that each peripheral resides in: Module 0: Timer 1, GPIO Ports 0, 1, and 2 Module 1: I2C Master, GPIO Port 6, Supply Voltage Monitor Module 2: I2C Slave Module 3: Timer 2, MAC-Related Registers, Software Interrupt and General-Purpose Registers Module 4: ADC, Sample/Hold, Internal Temperature, 3-Wire Master, SPI Slave, DAC Module 5: Quick Trips, SPI Master, PWM Instruction Set The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory loca - tions. The instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. Special-function registers control the peripherals and are subdivided into register modules. Memory Organization The device incorporates several memory areas:

• 32KWords of flash memory for application program and constant data storage
• 2KWords of SRAM
• 4KWords of utility ROM contain a debugger and pro - gram loader
• 32-level stack memory for storage of program return addresses and application use The memory is implemented with separate address spaces for program memory, data memory and register space which also allows ROM, application code, and data memory into a single contiguous memory map. The device allows data memory to be mapped into program space, permitting code execution from data memory. In addition program memory may be mapped into data space, permitting code constants to be accessed as data memory. Figure 6 shows the DS4830A’s memory map when executing from program memory space. Refer to the DS4830A User’s Guide for memory map information when executing from data or ROM space. The incorporation of flash memory allows field upgrade of the firmware. Flash memory can be password protected with a 16-word key, denying access to program memory by unauthorized individuals. Utility ROM The utility ROM is a 4KWord block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines that can be called from application software, which include the following:
• In-system programming (bootstrap loader) over JTAG or I2C-compatible interfaces
• Callable routines for in-application flash programming Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of application code, or to one of the special routines mentioned. Routines within the utility ROM are firmware-accessible and can be called as subroutines by the application software. More information on the utility ROM contents is contained in the DS4830A User’s Guide. DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 19

Figure 6. Memory Map When Program Is Executing from Flash Memory found in the DS4830A User’s Guide. the PUSH, POP, and POPI instructions. tions retrieve the value at SP and then decrement SP.

Figure 7. In-System Programming tected to prevent unauthorized access to code memory. grammed over the JTAG or I 2C compatible interfaces. software updates are required. ers, interrupt vectors and control, and stack pointer. and the functionality is broken up into discrete modules. described in detail in the DS4830A User’s Guide. FOLLOWED BY RESET OF DEVICE.

Figure 8. System Timing (tSU:MOSC), clocking the device as shown in Figure 8. maintained during execution of all resets except POR. POR whenever a rising voltage on VDD climbs above VBO.

• All registers and circuits enter their reset state.
• The POR flag (WDCN.7) is set to indicate the source of the reset.
• Code execution begins at location 8000h when the reset condition is released. Brownout Detect/Reset The device features a brownout detect/reset function. Whenever the power monitor detects a brown-out condi - tion (when VDD < VBO), it immediately issues a reset and stays in that state as long as V DD remains below V BO. Once V DD voltage rises above V BO, the device waits for tSU:MOSC before returning to normal operation, also referred to as CPU state. If a brownout occurs during this tSU:MOSC, the device again goes back to the brownout state. Otherwise, it enters into CPU state. In CPU state, the brownout detector is also enabled. On power-up, the device always enters brownout state first and then follows the above sequence. The reset issued by brownout is same as POR. Any action per - formed after POR also happens on brownout reset. All the registers that are cleared on POR are also cleared on brownout reset. External Reset Asserting the RST pin low causes the device to enter the reset state. Execution resumes at location 8000h after RST is released. Watchdog Timer Reset The watchdog timer provides a mechanism to reset the processor in the case of undesirable code execution. The watchdog timer is a hardware timer designed to be peri - odically reset by the application software. If the software operates correctly, the timer is reset before it reaches its maximum count. However, if undesirable code execution prevents a reset of the watchdog timer, the timer reaches its maximum count and resets the processor. The watchdog timer is controlled through 2 bits in the WDCN register (WDCN[5:4] : WD[1:0]). Its timeout period can be set to one of the four programmable intervals ranging from 2 12 to 2 21 system clock (MOSC) periods (0.410ms to 0.210s). The watchdog interrupt occurs at the end of this timeout period, which is 512 MOSC clock periods, or approximately 50µs, before the reset. The reset generated by the watchdog timer lasts for 4 system clock cycles, which is 0.4µs. Software can determine if a reset is caused by a watchdog timeout by checking the watchdog timer reset flag (WTRF) in the WDCN register. Execution resumes at location 8000h following a watch - dog timer reset. The watchdog reset has the same effect as the external reset as far as the reset values of all reg - isters are concerned. tSU:MOSC = ~1ms CORE CLOCK VDD VBO DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 22

The host can issue an I 2C command (BBh) to reset the communicating device. This reset has the same effect as the external reset as far as the reset values of all registers are concerned. Also, an internal system reset can occur when the in-system programming is done (ROD = 1). This reset has the same effect as the external reset as far as the reset values of all registers are concerned. Software Reset The device UROM provides option to soft reset through the application program. The application program can jump to UROM code, which generates the internal sys - tem reset. This reset has the same effect as the internal system reset. Further information regarding various resets can be found in the DS4830A User’s Guide. Programmable Timer The device features two general-purpose programmable timers. Various timing loops can be implemented using the timers. The timer can be used in two modes: free- running mode and compare mode. The functionality of the timers can be accessed through three SFRs for each of the general purpose timers. GTCN is the general control register, GTV is the timer value register and GTC is the timer compare register. The timer SFRs are accessed in Module 0 and 3. Detailed information regarding the timer block can be found in the DS4830A User’s Guide. Hardware Multiplier The hardware multiplier (a multiply-accumulate, or MAC module) is a very powerful tool, especially for applications that require heavy calculations. This multiplier is capable of executing the multiply, multiply-negate, multiply-accu - mulate, multiply-subtract operation for signed or unsigned operands in a single machine cycle. The MAC module uses 10 SFRs, mapped as register 0h–05h, 07h–09h and 0Eh in Module M3. System Interrupts Multiple interrupt sources are available to respond to internal and external events. The microcontroller archi - tecture uses a single interrupt vector (IV) and single inter- rupt-service routine (ISR) design. For maximum flexibility, interrupts can be enabled globally, individually, or by mod- ule. When an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at the local, module, or global level. Interrupt flags must be cleared within the firmware-interrupt routine to avoid repeated interrupts from the same source. Application software must ensure a delay between the write to the flag and the RETI instruction to allow time for the interrupt hardware to remove the internal interrupt condition. Asynchronous interrupt flags require a one-instruction delay and syn - chronous interrupt flags require a two-instruction delay. When an enabled interrupt is detected, execution jumps to a user-programmable interrupt vector location. The IV register defaults to 0000h on reset or power-up, so if it is not changed to a different address, application firmware must determine whether a jump to 0000h came from a RST or interrupt source. Once control has been transferred to the ISR, the inter - rupt identification register (IIR) can be used to determine which module was the source of the interrupt. In addition to IIR, MIIR registers are implemented to indicate which particular function under a peripheral module has caused the interrupt. The device contains six peripheral modules, M0 to M5. An MIIR register is implemented in modules M1, M4, and M5. The MIIRs are 16-bit read only registers and all of them default to all zero on system reset. Once the module that causes the interrupt is singled out, it can then be interrogated for the specific interrupt source and software can take appropriate action. Interrupts are evaluated by application code allowing the definition of a unique interrupt priority scheme for each application. Interrupt sources are available from the watchdog timer, the ADC (including sample/holds and internal tempera - ture), fast comparators, the programmable timers, SVM, the I 2C-compatible master and slave interface, 3-wire, master and slave SPI, software interrupts, as well as all GPIO pins. I/O Port The device allows for most inputs and outputs to func - tion as general purpose input and/or output pins. There are four ports: P0, P1, P2, and P6. Note that there is no port pin corresponding to P6.7. The 7th bit of port 6 is nonfunctional in all SFRs. Each pin is multiplexed with at least one special function, such as interrupts, ADC, DAC, PWM, or JTAG pins etc. The GPIO pins have Schmitt trigger receivers and full CMOS output drivers, and can support alternate functions. The ports can be accessed through SFRs (PO[0,1,2,6], EIES[0,1,2,6]) in Modules 0 and 1 and each pin can be individually configured. The pin is either high impedance or a weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 23

Figure 9. ADC Block Diagram block can be found in the DS4830A User’s Guide. vided. There are also two selectable external references. for a DAC, it should be used only for the DAC function. and PWM or switched between DAC and GPIO. ing the ADC in desired mode of operation. channels can be programmed to be sample/hold inputs. die temperature. The SFR registers control the ADC. 0.6V, 2.4V, and 6.55V full scale. DS4830A User’s Guide for different ADC clock settings. period determined by the ADC control register.

Figure 10. Burst Mode RSSI Monitoring depending on the SH_DUAL bit in the SHCN SFR. completion. Once set, SHnDAI can be cleared by software. to reduce ground offsets and noise. applications using current mirror, as shown Figure 10. temperature measurement resolution is 0.0625°C.

Fast Comparator/Quick Trips The device supports 10-bit quick trip comparison function- ality. The quick trips may be used to continuously monitor user defined channels in a round robin sequence. The quick trip controller allows the user to control the list of channels to monitor in the round-robin sequence. The quick trip (analog) performs two comparisons on any selected channel. 1) Comparison with a high threshold value. 2) Comparison with a low threshold value. Any comparison above the high threshold value or below the low threshold value causes a bit to set in the cor - responding register. This bit can be used to trigger an interrupt. The threshold values are stored in 32 internal register (16 for low threshold settings and 16 for high threshold settings). The quick trip controller provides user defined threshold values for the quick trips. Because the quick trips and the ADC use the same input pins, the con- troller ensures that no collision takes place. The quick-trip-related SFRs are accessed in Module 5. Refer to the quick trip section of the DS4830A User’s Guide for more information. I2C-Compatible Interface Modules The device provides two independent I 2C-compatible interfaces, one is a master and another is a slave. I2C-Compatible Master Interface The device features an internal I 2C-compatible master interface for communication with a wide variety of external I2C devices. The I2C-compatible master bus is a bidirec - tional bus using two bus lines, the serial data line (MSDA) and the serial clock line (MSCL). For the I 2C-compatible master, the device has ownership of the I 2C bus and drives the clock and generates the START and STOP signals. This allows the device to send data to a slave or receive data from a slave. The device has a configuration bit in the I2CCN_M regis - ter that allows the user to configure I2C master MSDA and MSCL pins to two different set of pins. PIN I2CCN_M.I2CM_ALT = 0 I2CCN_M.I2CM_ALT = 1 MSDA P1.0 P1.6 MSCL P1.1 P1.7 Details can be found in the I 2C master section of the DS4830A User’s Guide. I2C-Compatible Slave Interface The device also features an internal I2C-compatible slave interface for communication with a host. Furthermore, the device can be in system programmed (bootloaded) through the I2C-compatible slave interface. The two inter- face signals used by the I 2C slave interface are SCL and SDA. For the I 2C-compatible slave interface, the device relies on an externally generated clock to drive SCL and responds to data and commands only when requested by the I 2C master device. The I 2C-compatible slave inter - face is open-drain and requires external pull up resistors. The device supports four slave addresses. Each slave address has dedicated 8-byte transmit page and all slave addresses share common 8-byte receive FIFO. SMBus Timeout Both the I 2C-compatible slave interfaces can work in SMBus-compatible mode for communication with other SMBus devices. To achieve this, a 30ms timer has been implemented on the I 2C-compatible slave interface to make the interface SMBus-compatible. The purpose of this timer is to issue a timeout interrupt and thus the firm - ware can reset the I 2C-compatible slave interface when the SCL is held low for longer than 30ms. The timer only starts when none of the following conditions is true: 1) The I2C-compatible slave interface is in the idle state and there is no communication on the bus. 2) The I 2C-compatible slave interface is not working in SMBus-compatible mode. 3) The SCL logic level is high. 4) The I2C-compatible slave interface is disabled. When a timeout occurs, the timeout bit is set and an interrupt is generated, if enabled. The I 2C master related SFRs are accessed in Module 1. The I 2C slave related SFRs are accessed in Module 2. Details can be found in the I2C master and slave section of the DS4830A User’s Guide. DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 27

Serial Peripheral Interface Module The device supports master and slave SPI interfaces. The SPI provides an independent serial communication channel to communicate synchronously with peripheral devices in a multiple master or multiple slave system. The interface allows access to a four-wire, full-duplex serial bus, and can be operated in either master mode or slave mode. Collision detection is provided when two or more masters attempt a data transfer at the same time. The maximum data rate of the SPI is 1/4 the system reference clock frequency for slave mode and 1/2 the system clock frequency for master mode. The SPI uses the following four interface signals:

• Master In-Slave Out. This signal is an output from a slave device, SSPIDO, and an input to the master device, MSPIDI. It is used to serially transfer data from the slave to the master. Data is transferred most significant bit (MSB) first. The slave device places this pin in an input state with a weak pullup when it is not selected.
• Master Out-Slave In. This signal is an output from a master device, MSPIDO, and an input to the slave devices, SSPIDI. It is used to serially transfer data from the master to the slave. Data is transferred MSB first.
• SPI Clock. This serial clock is an output from the mas- ter device, MSPICK, and an input to the slave devices, SSPICK. It is used to synchronize the transfer of data between the master and the slave on the data bus.
• Slave Select. The slave-select signal is an input to enable the SPI module in slave mode, SSPICS, by a master device. The SPI module supports configuration of an active SSPICS state through the slave-active select. Normally, this signal has no function in master mode and its port pin can be used as a general-pur - pose I/O. However, the SSEL can optionally be used as mode fault detection in master mode. SPI Master Interface The master mode is used when the device’s SPI controls the data transmission rates and data format. The SPI is placed in master mode by setting the master mode bit (MSTM). Only an SPI master device can initiate a data transfer. Writing a data character to the SPI data buffer (SPIB), when in master mode, starts a data transfer. The SPI master immediately shifts out the data serially on MSPIDO, MSB first, while providing the serial clock on the MSPICK output. New data is simultaneously gated in on MSPIDI into the least significant bit (LSB) of the shift reg - ister. At the end of a transfer, the received data is loaded into the data buffer for reading, and the SPI transfer com- plete flag (SPIC) is set. If SPIC is set, an interrupt request is generated to the interrupt handler, if enabled. SPI Slave Interface Slave mode is used when the SPI is controlled by another peripheral device. The SPI is in slave mode when an inter- nal bit (MSTM) is cleared to logic 0. In slave mode, the SPI is dependent on the SPICK sourced from the master to control the data transfer. The SPICK input frequency should not be greater than the system clock frequency of the slave device divided by 4. The SPI master transfers data to a slave on the SSPIDI, MSB first, the selected slave device simultaneously transfers the contents of its shift register to the master on the SSPIDO, also MSB first. Data received from the master replaces data in the slave’s shift register at the completion of a transfer. Just like in the master mode, received data is loaded into the read buffer and the SPIC is set at the end of the transfer. Setting the SPIC flag may cause an interrupt if enabled. The SPI master-related SFRs are accessed in Module 5. The SPI slave-related SFRs are accessed in Module 4. Details can be found in the SPI section of the DS4830A User’s Guide. 3-Wire Interface Module The device controls 3-wire slave devices like the MAX3798 and MAX3799 over a proprietary 3-wire interface. The device acts as the 3-wire master, initiating communica - tion with and generating the clock for the 3-wire slave. It is a 3-pin interface consisting of MSDIO (a bidirectional data line), an MSCL clock signal, and an MCS chip-select output (active high). The 3-wire master-related SFRs are accessed in Module 4. Detailed information regarding the 3-wire interface block can be found in the DS4830A User’s Guide. DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 28

TOUTA25Ω 25Ω TOUTC VOUT SDA SCL CSEL MSDIO MSCL MCS 13-BIT ADC SLAVE I2C ALT MASTER I2C ROSA BIAS MONITOR MD DFB MAX3948 DS4830A MODE_DEF1 (SCL) MODE_DEF2 (SDA) VCCT VSEL TOUTA25Ω 25Ω TOUTC VOUT SDA SCL CSEL MD DFB MAX3948 VCCT VSEL TOUTA25Ω 25Ω TOUTC VOUT SDA SCL CSEL MD DFB MAX3948 VCCT VSEL TOUTA25Ω 25Ω TOUTC VOUT SDA SCL CSEL MD DFB MAX3948 VCC (+3.3V) RSSI MONITOR DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 30 Typical Application Circuit

+Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. PART TEMP RANGE PIN-PACKAGE DS4830AT+ -40°C to +85°C 40 TQFN-EP* DS4830AT+T -40°C to +85°C 40 TQFN-EP* DS4830A Optical Microcontroller www.maximintegrated.com Maxim Integrated │ 31

Ordering Information

0 12/13 Initial release — 1 1/17 Updated DAC Outputs section and Package Information table 2, 24 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. DS4830A Optical Microcontroller © 2017 Maxim Integrated Products, Inc. │ 32

Revision History

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.