DS4830

DS4830 MAXIM | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 29

Technical content

Features

S 16-BitMAXQ20Low-PowerMicrocontroller S EfficientC-LanguageProgramming S 36KWordsTotalProgramMemory  32KWordsFlashProgramMemory  4KWordsROMProgramMemory S 1KWordDataRAM S 8DACChannels  12-BitVoltageDACs  InternalorExternalReference S 10PWMChannels  Boost/BuckDC-DCControlwithSupportfor 7-Bitto12-BitResolutionand1MHzSwitching Frequency  Supports4-ChannelTECCH-BridgeControl S 10-BitFastComparatorwith16-InputMux  1.6µsperComparison S 13-BitA/DConverterwith18-InputMux(27ksps) S TemperatureMeasurementAnalogFront-End  InternalTemperatureSensor,±3NC  0.125NCResolution  SupportsTwoExternalTemperatureSensors  DifferentialRail-RailInputs S 31GPIOPins S MaskableInterruptSources S Internal20MHzOscillator,CPUCoreFrequency10MHz  4%Accuratefrom0NCto+50NC S Upto133MHzExternalClockforPWMandTimers S SlaveCommunicationInterface:SPI™or400kHz I2C-Compatible2-Wire S MasterCommunicationInterface:SPI,400kHzI2C- Compatible,orMaxim3-WireLaserDriver S I2CandJTAGBootloader S Two16-BitTimers S 3.0Vto3.6VOperatingVoltageRange S BrownoutMonitors S JTAGPortwithIn-SystemDebugandProgramming S LowPowerConsumption(16mA)withAllAnalog Active Typical Application Circuit appears at end of data sheet. 19-5934; Rev 0; 6/11 Ordering Information appears at end of data sheet. MAXQ is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/DS4830.related Forpricing,delivery,andorderinginformation,pleasecontactMaximDirectat1-888-629-4642, orvisitMaxim’swebsiteatwww.maxim-ic.com.

Maxim Integrated Products 2 DS4830 Optical Microcontroller All Other Pins to GND ABSOLUTEMAXIMUMRATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDEDOPERATINGCONDITIONS (TA = -40NC to +85NC, unless otherwise noted.) DCELECTRICALCHARACTERISTICS (VDD = 3V to 3.6V, T A = -40NC to +85NC, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25NC.) *Subject to not exceeding +3.63V. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VDD Operating Voltage VDD (Note 1) 3.0 3.6 V Input Logic-High VIH 0.7 x VDD VDD + 0.3 V Input Logic-Low VIL -0.3 0.3 x VDD V Input Logic-High: SCL, SDA, MCL, MSDA VI2C_IH (Note 1) 2.1 VDD + 0.3 V Input Logic-Low: SCL, SDA, MCL, MSDA VI2C_IL (Note 1) -0.5 +0.8 V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current ICPU CPU mode, all analog disabled (Notes 2, 3) 4.8 mA IFASTCOMP 2 ISAMPLEHOLDS Both sample/hold 1.5 IADC 2.8 IDACS Per channel (Note 4) 0.6 Brownout Voltage VBO Monitors VDD (Note 1) 2.7 V Brownout Hysteresis VBOH Monitors VDD (Note 1) 0.07 V 1.8V Regulator Initial Voltage VREG18 (Note 1) 1.71 1.8 1.89 V 2.85V Regulator Initial Voltage VREG285 (Note 1) 2.8 2.85 2.9 V

Maxim Integrated Products 3 DS4830 Optical Microcontroller DCELECTRICALCHARACTERISTICS(continued) (VDD = 3V to 3.6V, T A = -40NC to +85NC, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Clock Frequencies fOSC- PERIPHERAL TA = +25NC (Note 5) 20 MHz fMOSC-CORE TA = +25NC (Note 5) 10 Clock Error fERR TA = -40NC to +85NC ±5.5 % External Clock Input fXCLK 20 133 MHz Voltage Range: GP[15:0], SHEN, DACPW[7:0], REFINA, REFINB (Note 1) -0.3 VDD + 0.3 V Output Logic-Low: SCL, SDA, MDIO, MDI, MCL, MCS, REFINA, REFINB, All GPIO Pins VOL1 IOL = 4mA (Note 1) 0.4 V Output Logic-High: SDA, MDIO, MDI, MCL, MCS, REFINA, REFINB, All GPIO Pins Not Open Drain VOH1 IOH = -4mA (Note 1) VDD - 0.5 V Pullup Current: MDIO, MDI, MCL, MCS, All GPIO Pins IPU1 VPIN = 0V 26 55 78 FA GPIO Drive Strength, Extra Strong Outputs: GP0, GP1, MCS, PW8, PW9 RHISt 9 27.6 W RLOSt 8 25.2 GPIO Drive Strength, Strong Outputs: MDI, DACPW3, DACPW6 RHIA 17 32.4 W RLOA 12 26.4 GPIO Drive Strength, Excluding Strong GPIO Outputs RHIB 27 57 WRLOB 31 63

Maxim Integrated Products 4 DS4830 Optical Microcontroller DACDCELECTRICALCHARACTERISTICS FASTCOMPARATOR/QUICKTRIPSDCELECTRICALCHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC Resolution 12 Bits DAC Internal Reference Accuracy 2.5V internal reference -1.25 +1.25 % DAC Internal Reference Power-Up Speed 99% settled 10 Fs Reference Input Full-Scale Range (REFINA, REFINB) 1 2.5 V DAC Operating Current IDACS Per channel See the DC Electrical Characteristics DAC Integral Nonlinearity DACINL 12-bit at 2.5V reference 12 LSB DAC Differential Nonlinearity DACDNL 12-bit at 2.5V reference 1 LSB DAC Offset VOFFSET-DAC At code “0” 0 18 mV DAC Source Load Regulation IDAC-SOURCE 0 to full-scale output 8.6 mV/mA DAC Sink Capability and Sink Load Regulation RDAC-SINK 0 to 0.5V output, limited by output buffer impedance 500 I IDAC-SINK 0.5V to full-scale output 11.5 mV/mA DAC Settling Time tDAC 10 Fs PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Fast Comparator Resolution 8 Bits Fast Comparator Internal Reference Accuracy -1 +1 % Fast Comparator Operating Current IFASTCOMP See the DC Electrical Characteristics Fast Comparator Full Scale VFS-COMP 2.36 2.42 2.48 V Fast Comparator Integral Nonlinearity INL Differential mode, 2.2nF capacitor at input 2 LSB Fast Comparator Differential Nonlinearity DNL Differential mode, 2.2nF capacitor at input 1 LSB Fast Comparator Offset VOFFSET-COMP 2 LSB Fast Comparator Input Resistance RIN-COMP (Note 6) 15 MI Fast Comparator Input Capacitance CIN-COMP 4 pF Fast Comparator Sample Rate fCOMP 625 ksps

Maxim Integrated Products 5 DS4830 Optical Microcontroller ADCDCELECTRICALCHARACTERISTICS SAMPLE/HOLDDCELECTRICALCHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ADC Resolution 13 Bits ADC Internal Reference Accuracy -0.85 +0.85 % ADC Operating Current IADC See the DC Electrical Characteristics ADC Full-Scale 1 VFS-ADC1 1.2 V ADC Full-Scale 2 VFS-ADC2 0.6 V ADC Full-Scale 3 VFS-ADC3 2.4 V ADC Full-Scale 4 VFS-ADC4 3.6 V ADC Integral Nonlinearity ADCINL 13-bit 10 LSB ADC Differential Nonlinearity ADCDNL -8 +1 +8 LSB ADC Sample-Sample Deviation ADC full-scale set to VFS-ADC3 5 LSB ADC Offset VOFFSET-ADC 13-bit 2 LSB GP[15:0] Input Resistance RIN-ADC 15 MI ADC Sample Rate fSAMPLE (Note 7) 8 ksps ADC Temperature Conversion Time tTEMP 4.2 ms Internal Temperature Measurement Error (Note 8) -3.2 +3.2 NC Remote Temperature Measurement Error (DS4830 Error Only) (Note 8) -3.5 +3.5 NC PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Sample/Hold Input Range VSHP ADC-SHN[1:0] = GND 0 1 V Sample/Hold Capacitance CSH ADC-SHP[1:0] to ADC-SHN[1:0] 5 pF Sample Input Leakage ISHLKG ADC-SHP[1:0] and ADC-SHN[1:0] con- nected to GND 1.2 FA Sample Time ts ADC-SHP[1:0] and ADC-SHN[1:0] con- nected to 50I voltage source 300 ns Hold Time th 250 Fs Sample Offset VSH-OFF Measured at 10mV -10 -1.6 +7 mV Sample Error ERRSH VADC-SHP_ to VADC-SHN_ = 5mV, ts = 300ns, driven with 5kI voltage source -3 +3 % Sample Discharge Strength RDIS ADC-SHP[1:0] or ADC-SHN[1:0] to GND 900 1500 I

Maxim Integrated Products 6 DS4830 Optical Microcontroller FLASHMEMORYDCELECTRICALCHARACTERISTICS I2C-COMPATIBLEINTERFACEELECTRICALCHARACTERISTICS (VDD = 3.0V to 3.6V, T A = -40NC to +85NC, unless otherwise noted.) (See Figure 1.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Flash Erase Time tME Mass erase 22 24 40 ms tPE Page erase 22 24 40 Flash Programming Time per Word tPROG (Note 9) 69 74 79 µs Flash Programming Temperature -40 +85 NC Flash Endurance nFLASH TA = +50NC, guaranteed by design 20,000 Write Cycles Data Retention TA = +50NC, guaranteed by design 100 Years PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL/MSCL Clock Frequency fSCL Timeout not enabled 400 kHz SCL/MSCL Bootloader Clock Frequency fSCL:BOOT 100 kHz Bus Free Time Between a STOP and START Condition tBUF 1.3 Fs Hold Time (Repeated) START Condition tHD:STA (Note 10) 0.6 Fs Low Period of SCL/MSCL Clock tLOW 1.3 Fs High Period of SCL/MSCL Clock tHIGH 0.6 Fs Setup Time for a (Repeated) START Condition tSU:STA 0.6 Fs Data Hold Time tHD:DAT Receive 0 ns Transmit 300 Data Setup Time tSU:DAT (Notes 11, 12) 100 ns SCL/MSCL, SDA/MSDA Capacitive Loading CB (Note 13) 400 pF Rise Time of Both SDA/MSDA and SCL/MSCL Signals tR (Note 13) 20 + 0.1CB 300 ns Fall Time of Both SDA/MSDA and SCL/MSCL Signals tF (Note 13) 20 + 0.1CB 300 ns Setup Time for STOP Condition tSU:STO 0.6 Fs Spike Pulse Width That Can Be Suppressed by Input Filter tSP (Note 14) 0 50 ns SCL/MSCL and SDA/MSDA Input Capacitance CBIN 5 pF SMBusTimeout 30 ms

Maxim Integrated Products 7 DS4830 Optical Microcontroller 3-WIREDIGITALINTERFACESPECIFICATION (VDD = 3.0V to 3.6V, T A = -40NC to +85NC, unless otherwise noted.) (See Figure 2.) SPIDIGITALINTERFACESPECIFICATION (VDD = 3.0V to 3.6V, T A = -40NC to +85NC, unless otherwise noted.) (See Figure 3 and Figure 4.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MCL Clock Frequency fSCLOUT 833 kHz MCL Duty Cycle t3WDC 50 % MDIO Setup Time tDS 100 ns MDIO Hold Time tDH 100 ns MCS Pulse-Width Low tCSW 500 ns MCS Leading Time Before the First MCL Edge tL 500 ns MCS Trailing Time After the Last MCL Edge tT 500 ns MDIO, MCL Load CB3W Total bus capacitance on one line 10 pF PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SPI Master Operating Frequency 1/tMSPICK fSYS/2 MHz SPI Slave Operating Frequency 1/tSSPICK fSYS/4 MHz SPI I/O Rise/Fall Time tSPI_RF CL = 15pF, pullup = 560 I 25 ns MSPICK Output Pulse-Width High/Low tMCH, tMCL tMSPICK/2 - tSPI_RF ns MSPIDO Output Hold After MSPICK Sample Edge tMOH tMSPICK/2 - tSPI_RF ns MSPIDO Output Valid to MSPICK Sample Edge (MSPIDO Setup) tMOV tMSPICK/2 - tSPI_RF ns MSPIDI Input Valid to MSPICK Sample Edge (MSPIDI Setup) tMIS 2tSPI_RF ns MSPIDI Input to MSPICK Sample Edge Rise/Fall Hold tMIH 0 ns MSPICK Inactive to MSPIDO Inactive tMLH tMSPICK/2 - tSPI_RF ns SSPICK Input Pulse-Width High/ Low tSCH, tSCL tSCL/2 ns SSPICS Active to First Shift Edge tSSE tSPI_RF ns SSPIDI Input to SSPICK Sample Edge Rise/Fall Setup tSIS tSPI_RF ns SSPIDI Input from SSPICK Sample Edge Transition Hold tSIH tSPI_RF ns SSPIDO Output Valid After SSPICK Shift Edge Transition tSOV 2tSPI_RF ns

Maxim Integrated Products 8 DS4830 Optical Microcontroller SPIDIGITALINTERFACESPECIFICATION(continued) (VDD = 3.0V to 3.6V, T A = -40NC to +85NC, unless otherwise noted.) (See Figure 3 and Figure 4.) ELECTRICALCHARACTERISTICS:JTAGINTERFACE (VDD = 3.0V to 3.6V, T A = -40NC to +85NC, unless otherwise noted.) (Figure 5) Note1: All voltages are referenced to GND. Currents entering the IC are specified as positive, and currents exiting the IC are specified as negative. Note2: Maximum current assuming 100% CPU duty cycle. Note3: This value does not include current in GPIO, SCL, SDA, MDIO, MDI, MCL, REFINA, and REFINB. Note4: Depends on voltage on REFINA/B using internal reference. Note5: There is one internal oscillator. The oscillator (peripheral clock) goes through a 2:1 divider to create the core clock. Note6: Guaranteed by design. Note7: ADC conversions are delayed up to 1.6 Fs if the fast comparator is sampling the selected ADC channel. This can cause a slight decrease in the ADC sampling rate. Note8: Temperature readings average 64 times. Note9: Programming time does not include overhead associated with the utility ROM interface. Note10: fSCL must meet the minimum clock low time plus the rise/fall times. Note11: The maximum tHD:DAT need only be met if the device does not stretch the low period (t LOW) of the SCL signal. Note12: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the V IH:MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note13: CB—Total capacitance of one bus line in pF. Note14: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SSPICS Inactive tSSH tSSPICK + tSPI_RF ns SSPICK Inactive to SSPICS Rising tSD tSPI_RF ns SSPIDO Output Disabled After SSPICS Edge Rise tSLH 2tSSPICK 2tSPI_RF ns PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS JTAG Logic Reference VREF VDD/2 V TCK High Time tTH 0.5 Fs TCK Low Time tTL 0.5 Fs TCK Low to TDO Output tTLQ 0.125 Fs TMS, TDI Input Setup to TCK High tDVTH 0.25 Fs TMS, TDI Input Hold After TCK High tTHDX 0.25 Fs

Figure 5. JTAG Timing Diagram

Maxim Integrated Products 12 DS4830 Optical Microcontroller Pin Configuration Pin Description PIN NAME INPUT STRUCTURE(S) OUTPUT STRUCTURE POWER-ON STATE SELECTABLEFUNCTIONS (FIRSTCOLUMNISDEFAULTFUNCTION) PORT

1 RST Digital Open Drain High

Impedance RST — — — —

2 SCL Digital Open Drain High

SSPICK — — —

3 SDA Digital Open Drain High

SSPIDI — — —

4 GP0 ADC/Digital Input Push-Pull,

Extra Strong 55µA Pullup ADC-S0 ADC- D0P PW0 — P2.0 5 REG285 VREG None 2.85V Only function is for bypass capacitor for 2.5V internal regulator —

6 GP1 ADC/Digital Input Push-Pull,

Extra Strong 55µA Pullup ADC-S1 ADC- D0N PW1 — P2.1

7 VDD

Voltage Supply, ADC Input None VDD ADC-VDD — — — —

8 GP2 SH Input, ADC Input None High

D1P — — TQFN (5mm x 5mm) TOP VIEW SCL GP0 REG285 GP1 VDD RST MCS MDI MDIO VDD PW9 PW8 SHEN GP15 1 2 DACPW2 4 5 6 7 27282930 26 24 23 22 DACPW3 DACPW4 GP11 GP10 REG18 GP9 SDA MCL 37DACPW5 GP8 DACPW6 REFINB DACPW7 GP7 GP6 GP5 EP+ DACPW1 GP12DACPW0

20 GP13

Maxim Integrated Products 13 DS4830 Optical Microcontroller Pin Description (continued) PIN NAME INPUT STRUCTURE(S) OUTPUT STRUCTURE POWER-ON STATE SELECTABLEFUNCTIONS (FIRSTCOLUMNISDEFAULTFUNCTION) PORT

9 GP3 SH input, ADC Input None High

D1N — —

10 GP4 ADC/Digital Input Push-Pull 55µA Pullup JTAG TCK ADC-S4 ADC-

D2P — P6.0

11 GP5 ADC/Digital Input Push-Pull 55µA Pullup JTAG TDI ADC-S5 ADC-

D2N — P6.1

12 GP6 ADC/Digital Input Push-Pull 55µA Pullup ADC-S6 ADC-

SSPIDO P2.2

13 GP7 ADC/Digital Input Push-Pull 55µA Pullup ADC-S7 ADC-

SSPICS P2.3

14 GP8

ADC/Digital I/P, External Temp A+ I/P (ADC-TEXT_A) Push-Pull 55µA Pullup ADC-S8 ADC- D4P — — P2.4

15 GP9

ADC/Digital I/P, External Temp A- I/P (ADC-TEXT_A) Push-Pull 55µA Pullup ADC-S9 ADC- D4N — — P2.5

16 REG18 VREG, ADC Input

(ADC-1P8) None 1.8V Pin for 1.8V regulator bypass capacitor —

17 GP10

ADC/Digital I/P, External Temp A+ I/P (ADC-TEXT_B) Push-Pull 55µA Pullup JTAG TMS ADC- S10 ADC- D5P — P6.2

18 GP11

ADC/Digital I/P, External Temp A+ I/P (ADC-TEXT_B) Push-Pull 55µA Pullup JTAG TDO ADC- S11 ADC- D5N — P6.3

19 GP12 SH Input, ADC/Digital

Input Push-Pull 55µA Pullup ADC-S12 ADC- SHP1 ADC- D6P — P0.0

20 GP13 SH Input, ADC/Digital

Input Push-Pull 55µA Pullup ADC-S13 ADC- SHN1 ADC- D6N — P0.1

21 GP14 ADC/Digital Input Push-Pull 55µA Pullup ADC-S14 ADC-

D7P SHEN1 — P0.2

22 GP15 ADC/Digital Input Push-Pull 55µA Pullup ADC-S15 ADC-

D7N — — P0.3 23 SHEN Digital Push-Pull 55µA Pullup SHEN0 — — — P6.4

24 MDIO Digital Push-Pull 55µA Pullup 3-Wire Data

MSPIDO PW4 P1.0

25 MDI Digital Push-Pull,

Strong 55µA Pullup — — SPI MSPIDI PW5 P1.3

26 MCL Digital Push-Pull 55µA Pullup 3-Wire Clock

MSPICK PW6 P1.1

Maxim Integrated Products 14 DS4830 Optical Microcontroller Pin Description (continued) PIN NAME INPUT STRUCTURE(S) OUTPUT STRUCTURE POWER-ON STATE SELECTABLEFUNCTIONS (FIRSTCOLUMNISDEFAULTFUNCTION) PORT

27 MCS Digital Push-Pull,

Extra Strong 55µA Pullup 3-Wire Chip Select MCS — SPI MSPICS PW7 P1.2

28 VDD Voltage Supply None VDD ADC-VDD — — — —

29 PW9 Digital Push-Pull,

Extra Strong 55µA Pullup PW9 — — — P0.7

30 PW8 Digital Push-Pull,

Extra Strong 55µA Pullup PW8 — — — P0.6

31 REFINA Reference, ADC/Digital

Input (ADC_REFA) Push-Pull 55µA Pullup ADC- REFINA — — — P2.6

32 DACPW0 Digital Push-Pull 55µA Pullup

DAC0, FS = REFINA or Internal Reference PW0 — — P0.4

33 DACPW1 Digital Push-Pull 55µA Pullup

DAC1, FS = REFINA or Internal Reference PW1 — — P0.5

34 DACPW2 Digital Push-Pull 55µA Pullup

DAC2, FS = REFINA or Internal Reference PW2 CLKIN — P6.5

35 DACPW3 Digital Push-Pull,

Strong 55µA Pullup DAC3, FS = REFINA or Internal Reference PW3 — — P1.5

36 DACPW4 Digital Push-Pull 55µA Pullup

DAC4, FS = REFINB or Internal Reference PW4 — — P1.6

37 DACPW5 Digital Push-Pull 55µA Pullup

DAC5, FS = REFINB or Internal Reference PW5 — — P1.7

38 DACPW6 Digital Push-Pull,

Strong 55µA Pullup DAC6, FS = REFINB or Internal Reference PW6 — — P6.6

39 REFINB Reference, ADC/

Digital Input Push-Pull 55µA Pullup ADC- REFINB — — — P1.4

Maxim Integrated Products 15 DS4830 Optical Microcontroller Pin Description (continued) Note: Bypass VDD, REG285, and REG18 each with a 1µF X5R capacitor to ground. All input-only pins and open-drain outputs are high impedance after VDD exceeds VBO and prior to code execution. Pins configured as GPIO have a weak internal pullup. See the Selectable Functions table for more information. Selectable Functions PIN NAME INPUT STRUCTURE(S) OUTPUT STRUCTURE POWER-ON STATE SELECTABLEFUNCTIONS (FIRSTCOLUMNISDEFAULTFUNCTION) PORT

40 DACPW7 Digital Push-Pull 55µA Pullup

DAC7, FS = REFINB or Internal Reference PW7 — — P2.7 — EP Exposed Pad (Connect to GND) — GND — — — — — FUNCTIONNAME DESCRIPTION ADC-1P8 1.8V Regulator Monitor Input to ADC ADC-D[7:0][P/N] Differential Inputs to ADC. Also used for external temperature sensors. ADC-REFIN[A/B] REFINA and REFINB Monitor Inputs to ADC ADC-S[15:0] Single-Ended Inputs to ADC ADC-SH[P/N][1:0] Sample/Hold Inputs 1 and 0 ADC-VDD VDD Monitor Input to ADC DAC[7:0] Voltage DAC Outputs MCL, MCS, MDIO Maxim Proprietary 3-Wire Interface, MCL (Clock), MCS (Chip Select), MDIO (Data). Used to control the MAX3798 family of high-speed laser drivers. MSCL, MSDA I2C Master Interface: MSCL (I2C Master Slave), MSDA (I2C Master Data) MSPICK, MSPICS, MSPIDI, MSPIDO SPI Master Interface: MSPICK (Clock), MSPICS (Active-Low Chip Select), MSPIDI (Data In), MSPIDO (Data Out) PW[9:0] PWM Outputs RST Used by JTAG and as Active-Low Reset for Device SCL, SDA I2C Slave Interface: SCL (I2C Slave Clock), SDA (I2C Slave Data). These also function as a password-protected programming interface. SHEN[1:0] Sample/Hold Enable Inputs. Can also function as interrupts. SSPICK, SSPICS, SSPIDI, SSPIDO SPI Slave Interface: SSPICK (Clock), SSPICS (Active-Low Chip Select), SSPIDI (Data In), SSPIDO (Data Out). In SPI slave mode, the I2C slave interface is disabled. TCK, TDI, TDO, TMS JTAG Interface Pins. Also includes RST.

Maxim Integrated Products 16 DS4830 Optical Microcontroller Block Diagram CLOCK CONTROL, WATCHDOG TIMER, AND POWER MONITOR CKCN WDCN IC IC IP LOOP COUNTERS DATA POINTERS DPC MAXQ20 CORE SYSTEM MODULES/REGISTERS 4K x 16 UTILITY ROM FFFFh 8FFFh 8000h 7FFFh 0000h PROGRAM MEMORY SPACE LC[n] AP APC PSF 10MHz CPU CLOCK IMR IIR INTERRUPT LOGIC ADDRESS GENERATION DP[0], DP[1], FP = (BP+OFFS) 32K x 16 USER PROGRAM MEMORY ACCUMULATORS (16) BOOLEAN VARIABLE MANIPULATION INSTRUCTION DECODE (src, dst TRANSPORT DETERMINATION) 4K x 16 UTILITY ROM FFFFh 8FFFh 8000h 03FFh 0000h DATA MEMORY SPACE 1K x 16 SRAM SP STACK MEMORY 16 x 16 MASTER: I 2 C SPI 3-WIRE MDI MDIO MCL MCS SLAVE: I 2 C SPI SCL SDA SSPIDO SSPICS SHEN[1:0] GP[15:0] CLKIN REFIN[A/B] PW[9:0] DACPW[7:0] 16-BIT TIMERS x 2 20MHz OSC /2 CORE CLOCK MEMORY MANAGEMENT UNIT (MMU) RST 13-BIT ADC 10-BIT COMP D-PWM x 10 V DD ADC-D[7:0][P/N] PWM[9:0] ADC-S[15:0] INTERNAL TEMP REFIN[A/B] DAC[7:0] 12-BIT DAC x 8 V REF 2.5V ±1% UP TO 31 PORT PINS GPIO DS4830 C S x2DISCH ADC-SHP[1:0] ADC-SHN[1:0] SAMPLE/HOLD

Maxim Integrated Products 17 DS4830 Optical Microcontroller Detailed Description The following is an introduction to the primary features of the DS4830 system management microcontroller. More detailed descriptions of the device features can be found in the DS4830 User’s Guide. MAXQ20 Core Architecture The device employs a MAXQ20 low-power, low-cost, high-performance, CMOS, fully static, 16-bit RISC micro- controller with flash memory. It is structured on a highly advanced, 16 accumulator-based, 16-bit RISC archi - tecture. Fetch and execution operations are completed in one cycle without pipelining, since the instruction contains both the op code and data. The highly efficient core is supported by 16 accumulators and a 16-level hardware stack, enabling fast subroutine calling and task switching. Data can be quickly and efficiently manipulat - ed with three internal data pointers. Multiple data point - ers allow more than one function to access data memory without having to save and restore data pointers each time. The data pointers can automatically increment or decrement following an operation, eliminating the need for software intervention. Module Information The MAXQ20 architecture is designed to be modular and expandable. Top-level instruction decoding is extremely simple and based on transfers to and from registers. The registers are organized into functional modules, which are in turn divided into the system register and peripheral register groups. Peripherals and other features are accessed through peripheral registers. These registers reside in modules 0 to 5. The following provides information about the spe - cific module in which each peripheral resides:

• Module0: Timer and Counter 1, GPIO Ports 0, 1, and 2
• Module1: I2C Master, GPIO Port 6, SPIK Slave, Flash Memory Controls
• Module 2: I 2C Slave, Analog-to-Digital Converter (ADC), Sample/Hold, Temperature, 3-Wire Master
• Module3: Timer and Counter 2, MAC-Related Registers
• Module4: Digital-to-Analog Converter (DAC)
• Module5: Quick Trips, SPI Master, PWM Instruction Set The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory loca - tions. The instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. Special-function registers control the peripherals and are subdivided into register modules. Memory Organization The device incorporates several memory areas:
• 32KWords of flash memory for application program storage
• 1KWord of SRAM for storage of temporary variables
• 4KWords of utility ROM contain a debugger and pro - gram loader
• 16-level stack memory for storage of program return addresses and general-purpose use The memory is implemented using the Harvard archi - tecture, with separate address spaces for program memory, data memory, and register space. A pseudo- Von Neumann memory map is also used, placing ROM, application code, and data memory into a single contigu- ous memory map. The pseudo-Von Neumann memory map allows data memory to be mapped into program space, permitting code execution from data memory. In addition, program memory can be mapped into data space, permitting code constants to be accessed as data memory. Figure 6 shows the DS4830’s memory map when executing from program memory space. Refer to the DS4830 User’s Guide for memory map information when executing from data or ROM space. The incorporation of flash memory allows field upgrade of the firmware. Flash memory can be password protected with a 16-word key, denying access to program memory by unauthorized individuals. Utility ROM The utility ROM is a 4KWord block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines that can be called from application software, which includes the following:
• In-system programming (bootstrap loader) over JTAG or I2C-compatible interfaces
• In-circuit debug routines MAXQ is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc.

Figure 6. Memory Map

• Internal self-test routines
• Callable routines for in-application flash programming Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of application code, or to one of the special routines mentioned. Routines within the utility ROM are firmware-accessible and can be called as subroutines by the application software. More information on the utility ROM contents is contained in the DS4830 User’s Guide. Password Some applications require protection against unau - thorized viewing of program code memory. For these applications, access to in-system programming, in-appli- cation programming, or in-circuit debugging functions is prohibited until a password has been supplied. The password is defined as the 16 words of physical program memory at addresses 0010h–001Fh. A single password lock (PWL) bit is implemented in the device. When the PWL is set to 1 (power-on-reset default) and the contents of the memory at addresses 0010h–001Fh are any value other than all FFh or 00h, the password is required to access the utility ROM, includ - ing in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to 0, these utilities are fully accessible without the password. The password is automatically set to all ones following a mass erase. Detailed information regarding the password can be found in the DS4830 User’s Guide. SYSTEM REGISTERS PERIPHERAL REGISTERS DP 16 x 16 STACK 0Fh 00h FFFFh FFFFh FFFFh 8FFFh8FFFh8FFFh 7FFFh 0000h 0000h 0000h 4K x 16 UTILITY ROM 8K x 8 UTILITY ROM 4K x 16 UTILITY ROM 2K x 8 SRAM DATA 1K x 16 SRAM DATA 32K x 16 USER PROGRAM MEMORY 8000h 8000h 8000h 07FFh 03FFh DPC SP IP PFX A AP Fh 00h 0Fh 00h 1Fh Eh Dh Ch Bh PROGRAM MEMORY SPACE DATA MEMORY (BYTE MODE) DATA MEMORY (WORD MODE)

program return addresses and general-purpose use. tions retrieve the value at SP and then decrement SP. tected to prevent unauthorized access to code memory. grammed over the JTAG or I 2C compatible interfaces. software updates are required. Figure 7. In-System Programming FOLLOWED BY RESET OF DEVICE.

1ms, clocking the device. See Figure 8.

• All registers and circuits enter their reset state.
• The POR flag (WDCN.7) is set to indicate the source of the reset.
• Code execution begins at location 8000h when the reset condition is released. Brownout Detect/Reset The device features a brownout detect/reset function. Whenever the power monitor detects a brownout condi - tion (when VDD < VBO), it immediately issues a reset and stays in that state as long as V DD remains below V BO. Once V DD voltage rises above V BO, the device waits for tSU:MOSC before returning to normal operation, also referred to as CPU state. If a brownout occurs during tSU:MOSC, the device again goes back to the brownout state. Otherwise, it enters into CPU state. In CPU state, the brownout detector is also enabled. On power-up, the device always enters brownout state first and then follows the above sequence. The reset issued by brownout is the same as POR. Any action performed after POR also happens on brownout reset.

Figure 8. System Timing

Maxim Integrated Products 21 DS4830 Optical Microcontroller All the registers that are cleared on POR are also cleared on brownout reset. Watchdog Timer Reset The watchdog timer provides a mechanism to reset the processor in the case of undesirable code execution. The watchdog timer is a hardware timer designed to be peri - odically reset by the application software. If the software operates correctly, the timer is reset before it reaches its maximum count. However, if undesirable code execution prevents a reset of the watchdog timer, the timer reaches its maximum count and resets the processor. The watchdog timer is controlled through two bits in the WDCN register (WDCN[5:4]: WD[1:0]). Its timeout period can be set to one of the four programmable intervals ranging from 2 12 to 2 21 system clock (MOSC) periods (0.409ms to 0.210s). The watchdog interrupt occurs at the end of this timeout period, which is 512 MOSC clock periods, or approximately 50 Fs, before the reset. The reset generated by the watchdog timer lasts for four sys- tem clock cycles, which is 0.4Fs. Software can determine if a reset is caused by a watchdog timeout by checking the watchdog timer reset flag (WTRF) in the WDCN reg - ister. Execution resumes at location 8000h following a watchdog timer reset. External Reset Asserting RST low causes the device to enter the reset state. The external reset function is described in the DS4830 User’s Guide . Execution resumes at location 8000h after RST is released. The DAC and PWM outputs are unchanged during execution of external reset. Internal System Reset The host can issue an I 2C command (BBh) to reset the communicating device. This reset has the same effect as the external reset as far as the reset values of all registers are concerned. Also, an internal system reset can occur when the in-system programming is done (ROD = 1). Further details are available in the DS4830 User’s Guide. Programmable Timer/Counter The device features two general-purpose programmable timer/counters. Various timing loops can be implemented using the timers. Each general-purpose timer/counter uses three SFRs. GTCN is the general control register, GTV is the timer value register, and GTC is the timer compare register. The timer can be used in two modes: free-running mode and compare mode with interrupts. Both are described in detail in the DS4830 User’s Guide. The functionality of the timers can be accessed through three SFRs for each of the general-purpose timers. The timer and counter SFRs are accessed in module 0 and module 3. Detailed information regarding the timer/coun- ter block can be found in theDS4830 User’s Guide. Hardware Multiplier The hardware multiplier (multiply-accumulate, or MAC module) is a very powerful tool, especially for applica - tions that require heavy calculations. This multiplier can execute the multiply or multiply-negate, or multiply- accumulate or multiply-subtract operation for signed or unsigned operands in a single machine cycle. The MAC module uses eight SFRs, mapped as register 0h–05h and 08h–09h in module M3. System Interrupts Multiple interrupt sources are available to respond to internal and external events. The MAXQ20 architecture uses a single interrupt vector (IV) and single interrupt- service routine (ISR) design. For maximum flexibility, interrupts can be enabled globally, individually, or by module. When an interrupt condition occurs, its indi - vidual flag is set, even if the interrupt source is disabled at the local, module, or global level. Interrupt flags must be cleared within the firmware-interrupt routine to avoid repeated interrupts from the same source. Application software must ensure a delay between the write to the flag and the RETI instruction to allow time for the inter - rupt hardware to remove the internal interrupt condition. Asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a two- instruction delay. When an enabled interrupt is detected, execution jumps to a user-programmable interrupt vector location. The IV register defaults to 0000h on reset or power-up, so if it is not changed to a different address, application firmware must determine whether a jump to 0000h came from a RST or interrupt source.

Maxim Integrated Products 22 DS4830 Optical Microcontroller Once control has been transferred to the ISR, the inter - rupt identification register (IIR) can be used to deter - mine if a system register or peripheral register was the source of the interrupt. In addition to IIR, MIIR registers are implemented to indicate which particular function under a peripheral module has caused the interrupt. The device contains six peripheral modules, M0 to M5. An MIIR register is implemented in modules M0, M1, and M2. The MIIRs are 16-bit read-only registers and all of them default to all zeros on system reset. Once the module that causes the interrupt is singled out, it can then be interrogated for the specific interrupt source and software can take appropriate action. Interrupts are evaluated by application code allowing the definition of a unique interrupt priority scheme for each application. Interrupt sources are available from the watchdog timer, the ADC (including sample/holds), fast comparators, the programmable timer/counter, the I 2C-compatible master and slave interface, 3-wire, master and slave SPI, and all GPIO pins. I/O Port The device allows for most inputs and outputs to function as general-purpose input and/or output pins. There are four ports: P0, P1, P2, and P6. Note that there is no port corresponding to P6.7. The 7th bit of port 6 is nonfunc - tional in all SFRs. Each pin is multiplexed with at least one special function, such as interrupts, timer/counter I/O pins, or JTAG pins, etc. The GPIO pins have Schmitt trigger receivers and full CMOS output drivers and can support alternate functions. The ports can be accessed through SFRs (PO[0,1,2,6], EIES[0,1,2,6]) in modules 0 and 1, and each pin can be individually configured. The pin is either high impedance or a weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. In addition, each pin can function as external interrupt with individual enable, flag and active edge selection, when programmed as input. The I/O port SFRs are accessed in module 0 and 1. Detailed information regarding the GPIO block can be found in the DS4830 User’s Guide. DAC Outputs The device provides eight 12-bit DAC outputs with multi - ple reference options. An internal 2.5V reference is pro - vided. There are also two selectable external references. REFINA can be selected as the full-scale reference for DAC0 to DAC3. REFINB can be selected as the full-scale reference for DAC4 to DAC7. The DAC outputs are volt - age buffered. Each DAC can be individually disabled and put into a low-power power-down mode using DACCFG. An external reset does not affect the DAC outputs. The DAC SFRs are accessed in module 4. Detailed information regarding the DAC block can be found in the DS4830 User’s Guide. PWM Outputs The device provides 10 independently configurable PWM outputs. The PWM outputs are configured using three SFRs: PWMCN, PWMDATA, and PWNSYNC. Using PWMCN and PWMDATA, individual PWM channels can be programmed for unique duty cycles (DCYCn), con - figurations (PWMCFGn), and delays (PWMDLYn), where n represents the PWM channel number. The PWM clock can be obtained from the core clock, peripheral clock, or an external clock, depending on CLK_SEL bits programmed in individual PWMCFGn reg - isters. The PWMCFGn register also enables/disables the corresponding PWM output and selects the PWM polar - ity. The user can set the duty cycle and the frequency of each PWM output individually by configuring the cor - responding DCYCn register and the PWMCFGn register. The device allows 4-bit or 32-bit pulse spreading options for each PWM channel. The PWM outputs can be con - figured to be output on an alternate location using the configuration register. PWMDLY is a 12-bit register used for providing starting delay on different PWM channels, and can be used to create multiphase PWM operation. Different channels can be synchronized using the PWMSYNC register. Doing so effectively brings the channels in phase by restarting the channels that are to be synchronized. An external reset does not affect the PWM outputs. The PWM SFRs are accessed in module 5. Detailed information regarding the PWM block can be found in the DS4830 User’s Guide.

ing the ADC in desired mode of operation. channels can be programmed to be sample/hold inputs. die temperature. The SFR registers control the ADC. additional four core clocks used for data processing. by the ADC control register. sample/hold conversions if enabled in the SHCN register. depending on the SH_DUAL bit in the SHCN SFR. tor, charge injection nulling switches, and a buffer. pins can be used to reduce ground offsets and noise. Figure 9. ADC Block Diagram

Maxim Integrated Products 24 DS4830 Optical Microcontroller Temperature Measurement The device provides an internal temperature sensor for die temperature monitoring and two external remote temperature-sensing channels. In external temperature mode, current is forced into an external diode that is con- nected between user-specified channel pins. The diode temperature is obtained by measuring the diode voltages at multiple bias currents. These temperature channels can be enabled independ - ently by setting the appropriate bit locations in the TEMPCN register. Whenever a temperature conversion is complete, the corresponding flag (INTDAI for internal conversion, EX0DAI and EX1DAI for external conversion) is set. These can be configured to cause an interrupt, and can be cleared by software. The temperature meas - urement resolution is 0.0625NC. The device can use all the three modes explained above simultaneously by using a time-slicing mechanism per - formed by the internal controller. The ADC-related SFRs are accessed in module 1 and module 2. For details about this and the three blocks, refer to the ADC section of the DS4830 User’s Guide. Fast Comparator/Quick Trips The device supports 10-bit quick-trip comparison func - tionality. The quick trips are required to continuously monitor 5 to 14 channels in a round-robin sequence. The quick- trip controller allows the user control of the list of channels to monitor. Each mode has a corresponding choice of list of channels for the round robin. In any mode of quick-trip operation, the quick trip (ana - log) performs two comparisons on any selected channel. 1) Comparison with a high-threshold value. 2) Comparison with a low-threshold value. Any comparison above the high-threshold value or below the low-threshold value causes a bit to set in the cor - responding register. This bit can be used to trigger an interrupt. The threshold values are stored in 32 internal register (16 for low-threshold settings and 16 for high- threshold settings). The quick-trip controller provides the appropriate sequence of clock and threshold values for the quick trips. Because the quick trips and the ADC use the same input pins, the controller ensures that no colli - sion takes place. The quick-trip-related SFRs are accessed in module 5. Refer to the quick trip section of the DS4830 User’s Guide for more information. I2C-Compatible Interface Modules The device provides two independent I 2C-compatible interfaces: one is a master and the other is a slave. I2C-Compatible Master Interface The device features an internal I 2C-compatible master interface for communication with a wide variety of exter - nal I 2C devices. The I 2C-compatible master bus is a bidirectional bus using two bus lines: the serial-data line (MSDA) and the serial-clock line (MSCL). For the I 2C- compatible master, the device has ownership of the I 2C bus and drives the clock and generates the START and STOP signals. This allows the device to send data to a slave or receive data from a slave. When the I 2C-compatible master interface is disabled, MSDA and MSCL can be used as GPIO pins P1.0 and P1.1, respectively, and accessed through PO1/PI1/PD1. I2C-Compatible Slave Interface The device also features an internal I2C-compatible slave interface for communication with a host. Furthermore, the device can be in-system programmed (bootloaded) through the I2C-compatible slave interface. The two inter-The two inter- face signals used by the I2C slave interface are SCL and SDA. For the I 2C-compatible slave interface, the device relies on an externally generated clock to drive SCL and responds to data and commands only when requested by the I2C master device. The I2C-compatible slave inter- face is open drain and requires external pullup resistors. SMBus Timeout Both the I2C-compatible master and slave interfaces can work in SMBus K-compatible mode for communication with other SMBus devices. To achieve this, a 30ms timer has been implemented on the I2C-compatible slave inter- face to make the interface SMBus compatible. The pur - pose of this timer is to issue a timeout interrupt and thus the firmware can reset the I2C-compatible slave interface when the SCL is held low for longer than 30ms. The timer only starts when none of the following conditions is true: 1) The I2C-compatible slave interface is in the idle state and there is no communications on the bus. 2) The I2C-compatible slave interface is not working in SMBus-compatible mode. SMBus is a trademark of Intel Corp.

Maxim Integrated Products 25 DS4830 Optical Microcontroller 3) The SCL logic level is high. 4) The I2C-compatible slave interface is disabled. When a timeout occurs, the timeout bit is set and an inter- rupt is generated, if enabled. The I2C master-related SFRs are accessed in module 1. The I 2C slave-related SFRs are accessed in module 2. Details can be found in the I 2C section of the DS4830 User’s Guide. Serial Peripheral Interface Module The device supports master and slave SPI interfaces. The SPI provides an independent serial communication channel to communicate synchronously with peripheral devices in a multiple master or multiple slave system. The interface allows access to a four-wire, full-duplex serial bus, and can be operated in either master mode or slave mode. Collision detection is provided when two or more masters attempt a data transfer at the same time. The maximum data rate of the SPI is 1/4 the system reference clock frequency for slave mode. The four interface signals used by the SPI are as follows:

• Master In-Slave Out. This signal is an output from a slave device, SSPIDO, and an input to the master device, MSPIDI. It is used to serially transfer data from the slave to the master. Data is transferred most significant bit (MSB) first. The slave device places this pin in an input state with a weak pullup when it is not selected.
• Master Out-Slave In. This signal is an output from a master device, MSPIDO, and an input to the slave devices, SSPIDI. It is used to serially transfer data from the master to the slave. Data is transferred MSB first.
• SPI Clock. This serial clock is an output from the mas- ter device, MSPICK, and an input to the slave devices, SSPICK. It is used to synchronize the transfer of data between the master and the slave on the data bus.
• Active-Low Slave Select. The slave-select signal is an input to enable the SPI module in slave mode, SSPICS, by a master device. The SPI module sup - ports configuration of an active SSPICS state through the slave-active select. Normally, this signal has no function in master mode and its port pin can be used as a general-purpose I/O. However, the SSEL can optionally be used as a mode fault detection in master mode. SPI Master Interface The master mode is used when the device’s SPI controls the data transmission rates and data format. The SPI is placed in master mode by setting the master mode bit (MSTM). Only an SPI master device can initiate a data transfer. Writing a data character to the SPI data buffer (SPIB), when in master mode, starts a data transfer. The SPI master immediately shifts out the data serially on MSPIDO, MSB first, while providing the serial clock on the MSPICK output. New data is simultaneously gated in on MSPIDI into the least significant bit (LSB) of the shift register. At the end of a transfer, the received data is loaded into the data buffer for reading, and the SPI trans- fer complete flag (SPIC) is set. If SPIC is set, an interrupt request is generated to the interrupt handler. SPI Slave Interface Slave mode is used when the SPI is controlled by another peripheral device. The SPI is in slave mode when an internal bit (MSTM) is cleared to logic 0. In slave mode the SPI is dependent on the SSPICK sourced from the master to control the data transfer. The SSPICK input frequency should not be greater than the system clock frequency of the slave device divided by 4. The SPI mas- ter transfers data to a slave on SSPIDI, MSB first, and the selected slave device simultaneously transfers the contents of its shift register to the master on SSPIDO, also MSB first. Data received from the master replaces data in the slave’s shift register at the completion of a transfer. Just like in the master mode, received data is loaded into the read buffer, and the SPI transfer complete flag is set at the end of the transfer. The setting of the transfer com- plete flag can cause an interrupt if enabled. The SPI master-related SFRs are accessed in module 5. The SPI slave-related SFRs are accessed in module 1. Details can be found in the SPI section of the DS4830 User’s Guide. 3-Wire Interface Module The DS4830 controls devices like the MAX3798/MAX3799 over a proprietary 3-wire interface. The DS4830 acts as the 3-wire master, initiating communication with and generating the clock for the MAX3798/MAX3799. It is a 3-pin interface consisting of MDIO (a bidirectional data line), an MCL clock signal, and a MCS chip-select output (active high). The 3-wire master-related SFRs are accessed in mod - ule 2. Detailed information regarding the 3-wire interface block can be found in the DS4830 User’s Guide.

Maxim Integrated Products 27 DS4830 Optical Microcontroller

Ordering Information

+Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad.

Package Information

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PART TEMPRANGE PIN-PACKAGE DS4830T+ -40NC to +85NC 40 TQFN-EP* PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERNNO.

40 TQFN-EP T4055+2 21-0140 90-0002

Maxim Integrated Products 28 DS4830 Optical Microcontroller Typical Application Circuit VCCT VSEL TOUTA25I 25I TOUTC VOUT SDA SCL CSEL SDA SCL CSEL 13-BIT ADC SLAVE I2C BIAS MONITOR MD DFB MAX3948 DS4830 MODE_DEF1 (SCL) MODE_DEF2 (SDA) VCCT VSEL TOUTA25I 25I TOUTC VOUT SDA SCL CSEL MD DFB MAX3948 VCCT VSEL TOUTA25I 25I TOUTC VOUT SDA SCL CSEL MD DFB MAX3948 VCCT VSEL TOUTA25I 25I TOUTC VOUT SDA SCL CSEL MD DFB MAX3948 V CC (+3.3V) RSSI MONITOR

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 29 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

0 6/11 Initial release —