DS4625 MAXIM | Alldatasheet

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Technical content

Features

♦ Standard Clock Output Frequencies: 100MHz, 125MHz, 150MHz, 156.25MHz, and 200MHz ♦ Phase Jitter < 0.7ps RMS (typical) from 12kHz to 20MHz ♦ LVPECL Output ♦ +3.3V ±10% Operating Voltage ♦ -40°C to +70°C Temperature Range ♦ Excellent Power-Supply Noise Rejection ♦ 5.0mm x 3.2mm Ceramic LCCC Package ♦ Output Enable/Disable DS4625 3.3V Dual-Output LVPECL Clock Oscillator Ordering Information/Selector Guide 19-4558; Rev 0; 4/09 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. +Denotes a lead(Pb)-free/RoHS-compliant package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes. *Standard frequency options. Contact the factory at Custom.Oscillators@maxim-ic.com for custom frequencies. PART TEMP RANGE FREQUENCY (OP1:ON1) (MHz) (fC)* FREQUENCY (OP2:ON2) (MHz) (fC)* PIN-PACKAGE TOP MARK DS4625P+100/150 -40°C to +70°C 100.000 150.000 10 LCCC 6AC DS4625P+125/125 -40°C to +70°C 125.000 125.000 10 LCCC 6BB DS4625P+125/156 -40°C to +70°C 125.000 156.250 10 LCCC 6BD DS4625P+150/150 -40°C to +70°C 150.000 150.000 10 LCCC 6CC DS4625P+150/200 -40°C to +70°C 150.000 200.000 10 LCCC 6CE Pin Configuration and Typical Application Circuit appear at end of data sheet. InfiniBand is a trademark and service mark of the InfiniBand Trade Association. PCIe is a registered trademark of PCI-SIG Corp.

3.3V Dual-Output LVPECL Clock Oscillator ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (All voltages referenced to ground unless otherwise noted.) θ IPC/JEDEC J-STD-020 Specification. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Voltage Range V CC 2.97 3.3 3.63 V Input-Voltage High (OE) V IH 0.7 x VCC V CC V Input-Voltage Low (OE) V IL 0 0.3 x VCC V

ELECTRICAL CHARACTERISTICS

(VCC = +2.97V to +3.63V, TA = -40°C to +70°C, typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ICC_PU LVPECL, output unloaded 65 90 mA ICC_PL LVPECL, output loaded 120 140 mA Operating Current ICC_OEZ V OE = VIL 80 115 mA fOUT1Output Frequency fOUT2 VOE = VIH f C MHz Startup Time t START (Note 4) 1.0 ms Frequency Stability fTOTAL/fC Temperature, aging, load, supply, and initial tolerance (Note 5) -50 +50 ppm Frequency Stability Over Temperature with Initial Tolerance fTEMP/fC V CC = +3.3V -35 +35 ppm Initial Tolerance fINITIAL/fC VCC = +3.3V, TA = +25°C ±20 ppm Frequency Change Due to VCC fVCC V CC = +3.3V ±10%, T A = +25°C -3 +3 ppm/V Frequency Change Due to Load Variation fLOAD/fC ±10% variation in termination resistance ±1 ppm Aging (15 Years) fAGING/fC -7 +7 ppm OE Pullup Resistance R PU T A = +25°C 70 100 130 k Note 1: Package thermal resistances were obtained using a two-layer board. For detailed information on package thermal consider- ations, refer to www.maxim-ic.com/thermal-tutorial.

3.3V Dual-Output LVPECL Clock Oscillator Note 2: Limits at -40°C are guaranteed by design and are not production tested. Note 3: AC parameters are guaranteed by design and not production tested. Note 4: Startup time is from VCC = VCCMIN until PLL locks to the crystal oscillator output. Note 5: Frequency stability is calculated as: ΔfTOTAL = ΔfTEMP + ΔfVCC x (3.3 x 10%) + ΔfLOAD + ΔfAGING. Note 6: Supply-induced jitter is the deterministic jitter as measured on a LeCroy SDA11000 measured with a 50mVP-P sine wave forced on VCC. SINGLE-SIDEBAND PHASE NOISE SSB PHASE NOISE (dBc/Hz) (TYPICAL, +25°C, +3.3V) OFFSET f C = 100MHz f C = 125MHz f C = 150MHz f C = 156.25MHz f C = 200MHz UNITS 100Hz -71 -85 -84 -79 -85 1kHz -116 -117 -116 -115 -113 10kHz -119 -118 -116 -117 -113 100kHz -126 -125 -122 -123 -120 1MHz -143 -142 -141 -140 -139 10MHz -151 -149 -149 -148 -149 20MHz -151 -150 -149 -149 -150 dBc/Hz ELECTRICAL CHARACTERISTICS (continued) (VCC = +2.97V to +3.63V, TA = -40°C to +70°C, typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V OH Output connected to 50 at PECL_BIAS at VCC - 2.0V VCC - 1.085 VCC - 0.88 V Output Low Voltage V OL Output connected to 50 at PECL_BIAS at VCC - 2.0V VCC - 1.825 VCC - 1.62 V Differential Output Voltage |V OD| Output connected to 50 at PECL_BIAS at VCC - 2.0V 0.595 0.710 V Output Rise Time t R 20% to 80% 200 ps Output Fall Time t F 80% to 20% 200 ps Duty Cycle D CYCLE 45 55 % Propagation Delay from OE Going Low to Output High Impedance tPAZ (See Figure 2) 100 ns Propagation Delay from OE Going High to Output Active tPZA (See Figure 2) 100 ns Jitter J RMS Integrated phase RMS, 12kHz to 20MHz, VCC = +3.3V, TA = +25°C 0.7 ps Accumulated Deterministic Jitter Due to Reference Spurs 125.00MHz output, V CC = +3.3V, TA = +25°C 0.1 ps 10kHz 12.9 ps 100kHz 26.3 ps 200kHz 20.1 ps Accumulated Deterministic Jitter Due to Power-Supply Noise (P-P) (Note 6) 1MHz 6.4 ps

3.3V Dual-Output LVPECL Clock Oscillator Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) fC DEVIATION vs. TEMPERATURE DS4625 toc01 TEMPERATURE (°C) DEVIATION (ppm) 6040200-20 -40 -30 -20 -10 -50 -40 fC DEVIATION vs. VCC DS4625 toc02 VCC (V) DEVIATION (ppm) 0.5 1.0 1.5 2.0 2.5 3.0 3.0 ICC vs. VCC DS4625 toc03 VCC (V) CURRENT (mA) 100 110 120 130 140 3.0 3.6 ICC_PU ICC_PL ONE OUTPUT LOADED Pin Description PIN NAME FUNCTION 1 OE Active-High Output Enable. Has an internal pullup resistor (R PU). 2, 3 GND Ground

4 OP1 Positive Output 1 for LVPECL

5 ON1 Negative Output 1 for LVPECL

6 V CC Supply Voltage Input

A1, A2 N.C. No Internal Connection. Must be connected to ground. A3 OP2 Positive Output 2 for LVPECL A4 ON2 Negative Output 2 for LVPECL — EP Exposed Pad. The exposed pad must be used for thermal relief. This pad must be connected to ground.

3.3V Dual-Output LVPECL Clock Oscillator Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. Detailed Description The DS4625 is a dual-output, low-jitter clock oscillator that produces frequency output pair combinations as shown in the Ordering Information/Selector Guide table. The phase relationship between the outputs is not guar- anteed. The device combines an AT-cut, fundamental- mode crystal, an oscillator, and a low-noise PLL in a 5.0mm x 3.2mm surface-mount LCCC package. The DS4625 provides dual LVPECL clock output dri- vers. The output drivers can be enabled and disabled through the OE pin. The OE pin is an active-high CMOS input that has an internal pullup resistor. When OE is high, both output pairs are enabled. Chip Information PROCESS: Bipolar SiGe

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. TOP VIEW OE GND N.C. N.C. A1 A2 A3 A4 OP2 ON2 GND VCC ON1 OP1 DS4625 *EP *EXPOSED PAD Pin Configuration PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

10 LCCC L1053+H2 21-0389

0.01μF0.1μF 50Ω 50Ω PECL_BIAS AT VCC - 2.0V OP2 ON2 50Ω 50Ω PECL_BIAS AT VCC - 2.0V DS4625 Typical Application Circuit