DS4550 MAXIM | Alldatasheet

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Technical content

The DS4550 is a 9-bit, nonvolatile (NV) I/O expander with 64 bytes of NV user memory controlled by either an I2C-compatible serial interface or JTAG port. The DS4550 offers a digitally programmable alternative to hardware jumpers and mechanical switches that are being used to control digital logic nodes. Each I/O pin is independently configurable. The outputs are open-drain with selectable pullups. Each output has the ability to sink up to 16mA, and since the device is NV, it powers up in the desired state allowing it to control digital logic inputs immediately on powerup without having to wait for the host CPU to initiate control.

Applications

  • RAM-Based FPGA Bank Switching for Multiple Profiles
  • Selecting Between Boot Flash
  • Setting ASIC Configurations/Profiles
  • Servers
  • Network Storage
  • Routers
  • Telecom Equipment
  • PC Peripherals Benefits and Features
  • Programmable Replacement for Mechanical Jumpers and Switches
  • Nine NV Inputs/Outputs
  • 64-Byte NV User Memory (EEPROM)
  • I2C-Compatible Serial Interface and JTAG
  • Up to 8 Devices can be Multidropped on the Same I2C Bus
  • Open-Drain Outputs with Configurable Pullups
  • Outputs Capable of Sinking 16mA
  • Low Power Consumption
  • Wide Operating Voltage Range: 2.7V to 5.5V
  • Operating Temperature Range: -40°C to +85°C 19-8356; Rev 1; 7/17 Add “/T&R” for tape and reel orders. PART TEMP RANGE PIN-PACKAGE DS4550E -40°C to +85°C 20 TSSOP GND I/O_8 I/O_7 I/O_6I/O_3 I/O_2 I/O_1 I/O_0 TOP VIEW I/O_5 TDO TDITCK I/O_4 SCL SDAV CC TMS TSSOP DS4550 VCC FPGA CLOCK GENERATOR CPU SPEED SELECT GND 0.1µF V CC 4.7k I2C INTERFACE JTAG INTERFACE DS4550 SCL SDA TCK TMS TDI TDO I/O_0 I/O_1 I/O_2 I/O_3 I/O_4 I/O_5 I/O_6 I/O_7 I/O_8 DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory

Ordering Information

Pin Configuration Typical Operating Circuit

Voltage on VCC, SDA, and SCL Pins Voltage on A0, A1, A2, TCK, TMS, TDI, and I/O_n [n = 0 to 8] not to exceed +6.0V. Specification (TA = -40°C to +85°C) (VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC (Note 1) +2.7 +5.5 V Input Logic 1 VIH 0.7 x VCC VCC + 0.3 V Input Logic 0 VIL -0.3 0.3 x VCC V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Standby Current ISTBY (Note 2) 2 10 µA Input Leakage IL -1.0 +1.0 µA Input Current each I/O pin II/O 0.4 < VI/O < 0.9 x VCC -1.0 +1.0 µA Low-Level Output Voltage (SDA) VOL SDA 3mA sink current 0.4 V 6mA sink current 0.6 I/O Pins Low-Level Output Voltage VOL I/O 16mA sink current 0.4 V Low-Level Output Voltage (TDO) VOL TDO 4mA sink current 0.4 V High-Level Output Voltage (TDO) VOH TDO 1mA source current 2.4 V I/O Pin Pullup Resistors RPU 4.0 5.5 7.5 kΩ TMS, TDI Pullup Resistors RJPU 7.5 10 12.5 kΩ I/O Capacitance CI/O (Note 3) 10 pF Power-On Reset Voltage VPOR 1.6 V www.maximintegrated.com Maxim Integrated │ 2 DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions

(VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Timing referenced to V IL(MAX) and VIH(MIN).) (VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency fSCL (Note 4) 0 400 kHz Bus Free Time Between Stop and Start Conditions tBUF 1.3 µs Hold Time (Repeated) Start Condition tHD:STA (Note 5) 0.6 µs Low Period of SCL tLOW 1.3 µs High Period of SCL tHIGH 0.6 µs Data Hold Time tHD:DAT 0 0.9 µs Data Setup Time tSU:DAT 100 ns Start Setup Time tSU:STA 0.6 µs SDA and SCL Rise Time tR (Note 6) 20 + 0.1CB 300 ns SDA and SCL Fall Time tF (Note 6) 20 + 0.1CB 300 ns Stop Setup Time tSU:STO 0.6 µs SDA and SCL Capacitive Loading CB (Note 6) 400 pF EEPROM Write Time tWR I2C EEPROM write (Note 7) 10 20 ms PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TCK Clock Period t1 1000 ns TCK Clock High/Low Time t2, t3 (Note 8) 50 500 ns TCK to TDI, TMS Setup Time t4 15 ns TCK to TDI, TMS Hold Time t5 10 ns TCK to TDO Delay t6 50 ns TCK to TDO High-Z Delay t7 50 ns EEPROM Write Time tWR JTAG EEPROM write (Note 9) 10 20 ms www.maximintegrated.com Maxim Integrated │ 3 DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory

Note 1: All voltages referenced to ground. Note 2: I STBY is specified with SDA = SCL = TMS = TDI = V CC, outputs floating, and inputs connected to V CC or GND. Note 3: Guaranteed by design. Note 4: Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I 2C standard mode timing. Note 5: After this period, the first clock pulse is generated. Note 6: C B—total capacitance of one bus line in picofarads. EEPROM write time begins after a stop condition occurs. Note 8: TCK can be stopped either high or low. Figure 1. JTAG Timing Diagram

(VCC = +5.0V, TA = +25°C; TDI, TDO, TMS pins are no connects, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE DS4550 toc02 TEMPERATURE (C) SUPPLY CURRENT (A) 806040200-20 0.5 1.5 2.5 -40 VCC = SDA = SCL = 5.5V = TCK VCC = SDA = SCL = 2.7V = TCK I/O0-I/O7 CONTROL BITS = 0 I/O0-I/O7 PULLUPS DISABLED SUPPLY CURRENT vs. SCL FREQUENCY DS4550 toc03 SCL FREQUENCY (kHz) SUPPLY CURRENT (A) 300200100 0 400 VCC = SDA = TCK = 5.0V VCC = SDA = TCK = 2.7V SUPPLY CURRENT vs. TCK FREQUENCY DS4550 toc04 TCK FREQUENCY (kHz) SUPPLY CURRENT (A) 1750150012501000750500250 0 2000 VCC = 5.0V VCC = 2.7V SDA = SCL = VCC I/O OUTPUT VOLTAGE vs. SUPPLY VOLTAGE DS4550 toc05 SUPPLY VOLTAGE (V) I/O OUTPUT VOLTAGE (V) 54321 PULLUPS ENABLED PULLDOWNS DISABLED HIGH IMPEDANCE EEPROM RECALL AT VPOR SUPPLY CURRENT vs. SUPPLY VOLTAGE DS4550 toc01 SUPPLY VOLTAGE (V) SUPPLY CURRENT (A) 54.543.53 0.5 1.5 2.5 5.5 I/O0-I/O7 CONTROL BITS = 0 I/O0-I/O7 PULLUPS DISABLED V CC = SDA = SCL = TCK Maxim Integrated │ 5 www.maximintegrated.com DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Typical Operating Characteristics

1 I/O_0 Input/Output 0. Bidirectional I/O pin. 2 I/O_1 Input/Output 1. Bidirectional I/O pin. 3 I/O_2 Input/Output 2. Bidirectional I/O pin. 4 I/O_3 Input/Output 3. Bidirectional I/O pin. 5 I/O_4 Input/Output 4 . Bidirectional I/O pin. 6 A0 I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. 7 A1 I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. 8 TCK JTAG Test Clock. This signal is used to shift data into TDI on the rising edge and out of TDO on the falling edge. 9 TMS JTAG Test Mode Select. This pin is sampled on the rising edge of TCK and used to place the TAP into the various defined JTAG states. This pin has an internal pullup resistor.

10 VCC Power Supply Voltage

11 SDA I2C Serial Data Open-Drain Input/Output

12 SCL I2C Serial Clock Input

13 TDI JTAG Test Data Input. Test instructions and data are clocked into this pin on the rising edge of TCK. This pin has an internal pullup resistor. 14 TDO JTAG Test Data Output . Test instructions and data are clocked out of this pin on the falling edge of TCK. If not used, this pin should be left open circuit. 15 A2 I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. 16 I/O_5 Input/Output 5 . Bidirectional I/O pin. 17 I/O_6 Input/Output 6. Bidirectional I/O pin. 18 I/O_7 Input/Output 7. Bidirectional I/O pin. 19 I/O_8 Input/Output 8. Bidirectional I/O pin.

20 GND Ground

www.maximintegrated.com Maxim Integrated │ 6 DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Pin Description

The DS4550 contains nine bidirectional, NV, input/output (I/O) pins, and a 64-byte EEPROM user memory. The I/O pins and user memory are accessible through either the I2C compatible serial bus or the JTAG interface. Programmable NV I/O Pins Each programmable I/O pin consists of an input and an open-collector output with a selectable internal pullup resistor. To enable the pullups for each I/O pin, write to the Pullup Enable Registers (F0h and F1h). To pull the output low or place the pulldown transistor into a high- impedance state, write to the I/O Control Registers (F2h and F3h). To read the voltage levels present on the I/O pins, read the I/O Status Registers (F8h and F9h). To determine the status of the output register, read the I/O Control Registers and the Pullup Resistor Registers. The I/O Control Registers and the Pullup Enable Registers are all SRAM-shadowed EEPROM registers. It is possible to disable the EEPROM writes of the registers using the SEE bit in the Configuration Register. This reduces the time required to write to the register and increases the amount of times the I/O pins can be adjusted before the EEPROM is worn out. I2C INTERFACE VCC SDA SCL TMS TDI TDO TCK GND BSC BSC BSC BSC BSC EEPROM

64 BYTES

PULLUP ENABLE (F0h-F1h) I/O CONTROL (F2h-F3h) I/O STATUS (F8h-F9h) BOUNDARY SCAN CELL (BSC) JTAG CONTROL PORT VCC VCCI/O CELL (x9) RPU I/O_n [n = 0 TO 8] VCC RJPU RJPU BSC BSC BSC DS4550 www.maximintegrated.com Maxim Integrated │ 7 DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Block Diagram

EEPROM, SRAM-shadowed EEPROM, and SRAM. for applications that wish to constantly write to the I/Os. the DS4550 is standard SRAM. Pullup Enable for I/O_8. I/O_8 is the LSB. Only the LSB is used. I/O Control for I/O_8. I/O_8 is the LSB. Only the LSB is used. LSB will place the pulldown transistor into a high-impedance state. pullup/down is connected to the pin. determine the state of the I/O_0 to I/O_7 pins. no effect. Read this register to determine the state of the I/O_8 pin. Table 1. DS4550 Memory Map

Register and test data registers remain idle. the controller to the Select-IR-Scan state. controller in the Exit2-DR state. edge on TCK with TMS LOW enters the Shift-DR state. Figure 4. TAP Controller State Diagram

the Select-DR-Scan state if TMS is HIGH. controller enters the Shift-IR state. edge of TCK, the controller enters the Update-IR state. register through TDI using the Shift-DR state. into the Boundary Scan test data register. Table 2. Instruction Codes

CLAMP. All digital outputs of the device output data from the Boundary Scan parallel output while connecting the Bypass test data register between TDI and TDO. The outputs do not change during the CLAMP instruction. HIGHZ. All digital outputs of the device are placed in a high-impedance state. The Bypass test data register is connected between TDI and TDO. IDCODE. When the IDCODE instruction is latched into the parallel Instruction register, the Identification test data register is selected. The device identification code is loaded into the Identification test data register on the rising edge of TCK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially through TDO. During Test-Logic-Reset, the identification code is forced into the Instruction register. The ID code always has a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. See the diagram below. ADDRESS. When the ADDRESS instruction is latched into the Instruction register, TDI connects to TDO through the 8-bit Memory Address test data register during the Shift-DR state. READ. When the READ instruction is latched into the Instruction register, TDI connects to TDO through the 8-bit Memory Read test data register during the Shift-DR state. WRITE. When the WRITE instruction is latched into the Instruction register, TDI connects to TDO through the 8-bit Memory Write test data register during the Shift-DR state. When EEPROM writes occur using the JTAG interface, the DS4550 will write the whole EEPROM memory page (8 bytes) even though only a single byte is modified. The unmodified bytes of the page are transparently rewritten to their current values. The DS4550’s EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature. It is capable of handling many more writes at room temperature. Test Data Registers The DS4550 contains two test data registers; the Bypass Register and the Boundary Scan Register. The optional Identification test data register has been included in the DS4550 design along with three DS4550 specific registers (Address, Read, Write) to support access to the EEPROM. Bypass Register. This is a one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions. It provides a short path between TDI and TDO. Boundary Scan Register. This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells. It is 33 bits in length. See Table 3 for the cell bit locations and definitions. Identification Register. The Identification test data register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. Memory Address Register. This 8-bit register has a latched parallel output that holds the memory address location that is to be read from or written to. This register is selected during the ADDRESS instruction. Memory Read Register. This 8-bit load-only register will latch the 8-bit value from the memory location indicated by the address contained in the Address test data register during the Capture-DR state. The data can then be shifted out the TDO serial output by 8 rising edges of TCK during the Shift-DR state. See Table 4 for a detailed example. Memory Write Register. This 8-bit output-only register will write its 8-bit value to the memory location indicated by the address contained in the Address test data register during the Update-DR state. The data is shifted into the Write test data register through the TDI input with 8 rising edges of TCK during the Shift-DR state immediately prior to the Update-DR state. See Table 5 for a detailed example. MSB LSB Version (4 Bits) Device ID (16 Bits) Manufacturer ID (11 Bits) Fixed Value (1 Bit) 0000 0001000000000000 00010100001 1 www.maximintegrated.com Maxim Integrated │ 12 DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory 32-Bit ID Code

32 A2 input Input Observe Only

31 A1 input Input Observe Only

30 A0 input Input Observe Only

29 SCL input Input Observe Only

28 SDA input Input Observe Only

27 SDA output Output

26 IO8 pubout Output

25 IO8 pdbout Output

24 IO8 input Input Observe Only

23 IO7 pubout Output

22 IO7 pdbout Output

21 IO7 input Input Observe Only

20 IO6 pubout Output

19 IO6 pdbout Output

18 IO6 input Input Observe Only

17 IO5 pubout Output

16 IO5 pdbout Output

15 IO5 input Input Observe Only

14 IO4 pubout Output

13 IO4 pdbout Output

12 IO4 input Input Observe Only

11 IO3 pubout Output

10 IO3 pdbout Output

9 IO3 input Input Observe Only

8 IO2 pubout Output

7 IO2 pdbout Output

6 IO2 input Input Observe Only

5 IO1 pubout Output

4 IO1 pdbout Output

3 IO1 input Input Observe Only

2 IO0 pubout Output

1 IO0 pdbout Output

0 IO0 input Input Observe Only

Shift-IR (4 x TCK) The 4-bit instruction is shifted in through TDI. Shift-DR (8 x TCK) The 8-bit address is shifted in through TDI. Update-DR The shifted 8-bit Address Register data is output latched. Shift-IR (4 x TCK) The 4-bit instruction is shifted in through TDI. Capture-DR The 8-bit EEPROM data is loaded into the EEPROM Read Register. Shift-DR (8 x TCK) The 8-bit data is shifted out through TDO. Table 3. Boundary Scan Control Bits [33 Bits] Table 4. EEPROM Read Cycle

clock pulses, start and stop conditions. power mode for slave devices. master to initiate a new data transfer with a slave. by the master to end a data transfer with a slave. the timing diagram for applicable timing. shifted into the device during the rising edge of the SCL. Shift-IR (4 x TCK) The 4-bit instruction is shifted in through TDI. Shift-DR (8 x TCK) The 8-bit address is shifted in through TDI. Update-DR The shifted 8-bit Address Register data is output latched. Shift-IR (4 x TCK) The 4-bit instruction is shifted in through TDI. Shift-DR (8 x TCK) The 8-bit data is shifted in through TDI. Table 5. EEPROM Write Cycle

pulses including when it is reading bits from the slave. is always the 9th bit transmitted during a byte transfer. is read using the bit read definition. the bit write definition to receive additional data bytes. Figure 5. I2C Timing Diagram

The DS4550’s slave address of the DS4550 is determined by the state of the A0, A1, and A2 address pins as shown in Figure 2. Address pins connected to GND result in a ‘0’ in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a ‘1’ in the corresponding bit positions. When the R/ W bit is 0 (such as in A0h), the master is indicating it will write data to the slave. If R/ W = 1, (A1h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS4550 assumes the master is communicating with another I 2C device and ignores the communication until the next start condition is sent. Memory Address: During an I 2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. I2C Communication Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a stop condition. Remember the master must read the slave’s acknowledgement during all byte write operations. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave, the master generates a start condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a stop condition. The DS4550 is capable of writing up to 8 bytes (1 page or row) with a single I2C write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page. Attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. The first row begins at address 00h and subsequent rows begin at multiples of 8 there on (08h, 10h, 18h, 20h, etc). To prevent address wrapping from occurring, the master must send a stop condition at the end of the page, and then wait for the bus free or EEPROM write time to elapse. Then the master can generate a new start condition, write the slave address byte (R/ W = 0), and the first memory address of the next memory row before continuing to write data. Acknowledge Polling: Any time an EEPROM page is written, the DS4550 requires the EEPROM write time (tWR) after the stop condition to write the contents of the page to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of this phenom- enon by repeatedly addressing the DS4550, which allows communication to continue as soon as the DS4550 is ready. The alternative to acknowledge polling is to wait for a maximum period of tWR to elapse before attempting to access the device. EEPROM Write Cycles: When EEPROM writes occur using the I 2C interface, the DS4550 writes the whole EEPROM memory page even if only a single byte on a page was modified. Writes that do not modify all 8 bytes on the page are valid and do not corrupt any other bytes on the same page. Because the whole page is written, even bytes on the page that were not modified during the transaction are still subject to a write cycle. The DS4550’s EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature. It is capable of handling many more writes at room temperature. Reading a Single Byte from a Slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a start condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. However, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this, the master generates a start condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a stop condition. www.maximintegrated.com Maxim Integrated │ 16 DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory

condition to specify the starting memory location. can be used to read multiple bytes with a single transfer. transfer and generate a stop condition. decoupling capacitor is used on the IC power-supply pins. pins of the IC to minimize lead inductance. Figure 6. I2C Communication Examples *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.

www.maximintegrated.com Maxim Integrated │ 18 DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory

Package Information

For the latest package outline information, go to www.maximintegrated.com/DallasPackInfo. Chip Topology TRANSISTOR COUNT: 21,161 SUBSTRATE CONNECTED TO GROUND

A — ECN DS‐15‐DTSH. B 7/17 Removed IEEE 1149.1 references and general updates 1, 9, 11, 12 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2017 Maxim Integrated Products, Inc. │ 19 DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory

Revision History

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