DS4510U-10/R

DS4510 MAXIM | Alldatasheet

Document overview

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Technical content

Features

♦ Accurate 5%, 10%, or 15% 5V Power-Supply Monitoring ♦ Programmable Reset Timer Maintains Reset After VCC Returns to an In-Tolerance Condition ♦ Four Programmable, NV, Digital I/O Pins with Selectable Internal Pullup Resistor ♦ 64 Bytes of User EEPROM ♦ Reduces Need for Discrete Components ♦ I2C-Compatible Serial Interface ♦ 10-Pin µSOP Package DS4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O I/O0 I/O1 I/O2VCC SCL SDA TOP VIEW I/O3GND µSOP DS4510 RST Pin Configuration

Ordering Information

2.7V TO 5.5V GND RESET CONFIG0 CONFIG1 CONFIG2 CONFIG3 FROM SYSTEM CONTROLLER 4.7kΩ 4.7kΩ 4.7kΩ RST Typical Operating Circuit Rev 2; 8/04 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART VCC TRIP POINT TEMP RANGE PIN- PACKAGE DS4510U-5 5% -40°C to +85°C 10 µSOP DS4510U-10 10% -40°C to +85°C 10 µSOP DS4510U-15 15% -40°C to +85°C 10 µSOP DS4510U-5/T&R 5% -40°C to +85°C 10 µSOP DS4510U-10/T&R 10% -40°C to +85°C 10 µSOP DS4510U-15/T&R 15% -40°C to +85°C 10 µSOP I2C is a registered trademark of Philips Corp. Purchase of I 2C components of Maxim Integrated Products, Inc. or one of its Associated Companies, conveys a license under the Philips I 2C Patent Rights to use these components in an I 2C system, provided the system conforms to the I2C Standard Specifications as defined by Philips.

CPU Supervisor with Nonvolatile Memory and Programmable I/O ABSOLUTE MAXIMUM RATINGS RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on VCC, SDA, and SCL Voltage Range on A0, I/O0, I/O1, I/O2, I/O3 Relative J-STD-020A Specification PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC (Notes 1) 2.7 5.5 V Input Logic 1 V IH (Note 2) 0.7 x VCC VCC + 0.3 V Input Logic 0 V IL -0.3 +0.3 x V CC V DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V to 5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DS4510U-5 4.5 4.625 4.75 DS4510U-10 4.25 4.375 4.49VCC Trip Point V CCTP DS4510U-15 4.0 4.125 4.24 V Standby Current I STBY VCC = 5.0V (Note 3) 50 75 µA Input Leakage I L -1.0 +1.0 µA 3mA sink current 0.4SDA Low-Level Output Voltage V OL 6mA sink current 0.6 V I/OX Low-Level Output Voltage V OLIOX 4mA sink current 0.4 V RST Pin Low-Level Output VOLRST 10mA sink current (Note 4) 0.4 V I/OX Pullup Resistors R P 4.0 5.0 6.5 k Ω I/O Capacitance C I/O (Note 5) 10 pF

CPU Supervisor with Nonvolatile Memory and Programmable I/O CPU SUPERVISOR AC ELECTRICAL CHARACTERISTICS (See Figure 1) (VCC = 2.7V to 5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TD1= 0, TD0 = 0 112 125 138 TD1= 0, TD0 = 1 225 250 275 TD1= 1, TD0 = 0 450 500 550RST Active Time t RST TD1= 1, TD0 = 1 900 1000 1100 ms TD1= 0, TD0 = 0 112 125 138 TD1= 0, TD0 = 1 225 250 275 TD1= 1, TD0 = 0 450 500 550VCC Detect to RST tRPU TD1= 1, TD0 = 1 900 1000 1100 ms VCC Fail to RST tRPD 41 0µ s AC ELECTRICAL CHARACTERISTICS (See Figure 5) (VCC = 2.7V to 5.5V, TA = -40°C to +85°C, timing referenced to V IL(MAX) and VIH(MIN).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency f SCL (Note 6) 0 400 kHz Bus Free Time Between Stop and Start Conditions tBUF 1.3 µs Hold Time (Repeated) Start Condition tHD:STA 0.6 µs Low Period of SCL t LOW 1.3 µs High Period of SCL t HIGH 0.6 µs Data Hold Time tHD:DAT 0 0.9 µs Data Setup Time tSU:DAT 100 ns Start Setup time t SU:STA 0.6 µs SDA and SCL Rise Time t R (Note 7) 20 + 0.1CB 300 ns SDA and SCL Fall Time t F (Note 7) 20 + 0.1CB 300 ns Stop Setup Time tSU:STO 0.6 µs SDA and SCL Capacitive Loading CB (Note 7) 400 pF EEPROM Write Time t W (Note 7) 10 20 ms

CPU Supervisor with Nonvolatile Memory and Programmable I/O Note 1: All voltages referenced to ground. Note 2: The DS4510 does not obstruct the SDA and SCL lines if V CC is switched off, as long as the voltages applied to these inputs do not violate their min and max input voltage levels. Note 3: ISTBY specified with V CC equal to 5.0V, and control port-logic pins are driven to ground or V CC for the corresponding inactive state (SDA = SCL = VCC), does not include pullup resistor current. Note 4: See Typical Operating Characteristics for the RST output voltage vs. supply voltage. Note 5: This parameter is guaranteed by design. Note 6: I2C interface timing shown for is for fast-mode (400kHz) operation. This device is also backward compatible with I 2C standard-mode timing. Note 7: CB—total capacitance of one bus line in picofarads. Note 8: EEPROM write time applies to all the EEPROM memory and SEEPROM memory when SEE = 0. The EEPROM write time begins at the occurrence of a stop condition. NONVOLATILE MEMORY CHARACTERISTICS (VCC = 2.7V to 5.5V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Writes +70°C (Note 5) 50,000 Typical Operating Characteristics (VCC = +5.0V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE DS4510 toc01 SUPPLY VOLTAGE (V) SUPPLY CURRENT (µA) 4.54.03.5 3.0 5.0 VCC (10%) TRIP POINT SDA = SCL = VCC I/O CONTROL BITS = 0 I/O PULLUPS DISABLED SUPPLY CURRENT vs. TEMPERATURE DS4510 toc02 TEMPERATURE (°C) SUPPLY CURRENT (µA) 6040200-20 -40 80 SDA = SCL = VCC SUPPLY CURRENT vs. SCL FREQUENCY DS4510 toc03 SCL FREQUENCY (kHz) SUPPLY CURRENT (µA) 300200100 0 400 SDA = VCC

CPU Supervisor with Nonvolatile Memory and Programmable I/O Typical Operating Characteristics (continued) (VCC = +5.0V, TA = +25°C, unless otherwise noted.) VCC TRIP POINT vs. TEMPERATURE DS4510 toc04 TEMPERATURE (°C) VCC TRIP POINT (V) 6040200-20 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 4.0 -40 80 RST OUTPUT VOLTAGE vs. SUPPLY VOLTAGE DS4510 toc05 SUPPLY VOLTAGE (V) RESET TRIP VOLTAGE (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 5.5 5.6kΩ PULLUP RESISTOR ON RST SDA = SCL = V CC I/O PULLUP RESISTANCE vs. TEMPERATURE DS4510 toc06 TEMPERATURE (°C) I/O PULLUP RESISTANCE (kΩ) 6040200-20 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 4.75 -40 80 Pin Description PIN NAME FUNCTION 1A 0 I C Address Input. This input pin determines the chip address of the device. A0 = 0 sets the slave address to 1010000b, A0 = 1 sets the slave address to 1010001b. 2 SDA Serial Data Input/Output. Bidirectional I C data pin. 3 SCL Serial Clock Input. I C clock input. 4V CC Power Input

5 GND Ground

6 I/O3 Input/Output 3. I C accessible bidirectional I/O pin. 7 I/O2 Input/Output 2. I C accessible bidirectional I/O pin. 8 I/O1 Input/Output 1. I C accessible bidirectional I/O pin. 9 I/O0 Input/Output 0. I C accessible bidirectional I/O pin. 10 RST Active-Low Reset Output. Open-drain CPU supervisor reset output.

CPU Supervisor with Nonvolatile Memory and Programmable I/O Detailed Description The DS4510 contains a CPU supervisor, four program- mable I/O pins, and a 64-byte EEPROM memory. All functions are configurable or controllable through an industry-standard I 2C-compatible bus. DS4510 NV reg- isters that are likely to require frequent modification are implemented using SRAM-shadowed EEPROM (SEEP- ROM) memory. This memory is configurable to act as volatile SRAM or NV EEPROM by adjusting the SEE bit in the Config register. Configuring the SEEPROM as SRAM eliminates the EEPROM write time and allows infinite write cycles to these registers. Configuring the registers as EEPROM allows the application to change the power-on values that are recalled during power-up. Programmable CPU Supervisor The timeout period is adjusted by writing the reset delay register (SEEPROM). The delay for each setting is shown in the CPU Supervisor AC Electrical Characteristics. If the SEE bit is set, changes are writ- ten to SRAM. On power-up the last value written to the EEPROM is recalled. The I 2C bus is also used to acti- vate the RST by setting the SWRST bit in the Config register. This bit automatically returns to zero after the timeout period. The Config register also contains the ready, trip point, and reset status bits. The ready bit determines if the power-on reset level of the DS4510 is surpassed by V CC. The trip point bit determines if V CC is above VCCTP, and the reset status bit is set if RST is in its active state. Note: The RST pin is an open-drain output, therefore an external pullup resistor must be used to realize high logic levels. Programmable NV Digital I/O Pins Each programmable I/O X pin contains an input, open- collector output, and a selectable internal pullup resis- tor. The DS4510 stores changes to the I/O X pin in SEEPROM memory. Using the SEEPROM as SRAM is conducive to applications such as I/O expansion that generally require fast access times and frequent modi- fication of the I/O X pin. Configuring the SEEPROM to behave as EEPROM allows the modification of the power-on state of the I/O X pin. During power-up the I/OX pins are high impedance until V CC exceeds 2.0V (typically), which is when the last value programmed is recalled from EEPROM. On power-down, the I/O X state is maintained until VCC drops below 1.9V (typically). The internal pullups for each I/O X pin are controlled by the pullup-enable register (F0h). Similarly, the individual I/O X control registers (F4h to F7h) adjust the pulldown INTERNAL VOLTAGE REFERENCE VCC VCC VCC VCC 2-WIRE INTERFACE EEPROM

64 BYTES

R P 4 NV I/O PINS

4 BIDIRECTIONAL

PULLUP ENABLE (F0h) I/OX CONTROL (F4h-F7h) I/O STATUS (F8h) RST DS4510 Functional Diagram

mine the logic levels present at the I/O pins. Figure 2. How to Read the Memory Map Figure 1. CPU Supervisor Power-Up and Power-Down Timing

3 CONTROL

*ITALICIZED BYTES HAVE BIT DESCRPTIONS, REFER TO FIGURE 3. Figure 3. Register Memory Map

is always the 9th bit transmitted during a byte transfer. forms a NACK by transmitting a one during the 9th bit. the device is not receiving data. acknowledgement is read using the bit-read definition. the R/W bit is the least significant bit. 00 to 3F User EEPROM 64 bytes of EEPROM memory. 40 to EF Reserved These memory locations are reserved for future products. resistors. Set the bit to enable the pullup, clear it to disable the pullup. CPU Supervisor AC Timing Characteristics. F2 to F3 User SEEPROM SRAM Shadowed EEPROM user byte. ready Reads zero when VCC is above the DS4510's power-on reset voltage. Trip Point Reads one when V CC below VCCTP. Reset Status Reads one when the RST pin is active. SEEPROM registers behave like SRAM. Table 1. Register Definitions

CPU Supervisor with Nonvolatile Memory and Programmable I/O dition, write the slave address (R/ W = 0), and the first memory address of the next page before continuing to write data. Acknowledge Polling: Any time an EEPROM page is written, the DS4510 requires the EEPROM write time W) after the stop condition to write the contents of the page to EEPROM. During the EEPROM write time, the DS4510 does not acknowledge its slave address because it is busy. It is possible to take advantage of that phenomenon by repeated addressing the DS4510, which allows the next page to be written as soon as the DS4510 is ready to receive the data. The alternative to acknowledge polling is to wait for maximum period of t W to elapse before attempting to write again to the DS4510. EEPROM Write Cycles: When EEPROM writes occur, the DS4510 writes the whole EEPROM memory page even if only a single byte on the page was modified. Writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. Because the whole page is written, bytes on the page that were not modified dur- ing the transaction are still subject to a write cycle. This can result in a whole page being worn out over time by writing a single byte repeatedly. Writing a page one byte at a time wears the EEPROM out eight times faster than writing the entire page at once. The DS4510’s EEPROM memory is guaranteed to handle 50,000 write cycles at +70°C. Writing to SEEPROM memory with SEE = 1 does not count as an EEPROM write cycle when evaluating the EEPROM’s estimated lifetime. Reading a Single Byte from a Slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave the mas- ter generates a start condition, writes the slave address with R/W = 1, reads the data byte with a NACK to indi- cate the end of the transfer, and generates a stop con- dition. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master gen- erates a start condition, writes the slave address (R/ W = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address (R/W = 1), reads data with ACK or NACK as applicable, and generates a stop condition. See Figure 7 for a read example using the repeated start condition dummy write cycle. Reading Multiple Bytes from a Slave: The read oper- ation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the mas- ter reads the last byte it NACKs to indicate the end of the transfer and generates a stop condition. This can be done with or without modifying the address counter’s location before the read cycle. The DS4510 does not wrap on page boundaries during read opera- tions, but the counter rolls from its upper-most memory address FFh to 00h if the last memory location is read during the read transaction. Example: The entire memory contents of the DS4510 can be read with a single transfer starting at address F0h that reads 80 bytes of data. Addresses F0h to FFh are read sequentially, the address counter rolls to 00h, and then addresses 00h to 3Fh can be read sequential- ly. This allows the entire memory contents to be read in a single operation without reading the undefined con- tents of the reserved area of the memory.

Application Information

Advantages of Using the SEE Bit to Disable EEPROM Writes The SEE bit allows EEPROM writes to be disabled for the SRAM-shadowed EEPROM bytes, allowing the SRAM of SEE registers to change without writing the EEPROM to the same value. This prevents write opera- tions from changing the power-on value of the I/O pins, reduces the number of EEPROM write cycles, and speeds up I/O operations because the DS4510 does not require an internally timed EEPROM write cycle to complete the operation. Power-Supply Decoupling To achieve the best results when using the DS4510, decouple the power supply with a 0.01µF or a 0.1µF capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as pos- sible to the V CC and GND pins of the DS4510 to mini- mize lead inductance. SDA and SCL Pullup Resistors SDA is an open-collector output on the DS4510 that requires a pullup resistor to realize high logic levels. Because the DS4510 does not utilize clock cycle stretching, a master using either an open-collector out- put with a pullup resistor or a normal output driver can be utilized for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the

CPU Supervisor with Nonvolatile Memory and Programmable I/O Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. is a registered trademark of Dallas Semiconductor Corporation. Chip Topology TRANSISTOR COUNT: 16559 SUBSTRATE CONNECTED TO GROUND

Package Information

For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. S P Sr A N START 8-BITS ADDRESS OR DATAREPEATED START STOP ACK NOT ACK WHITE BOXES INDICATED THE MASTER IS CONTROLLING SDA SHADED BOXES INDICATED THE SLAVE IS CONTROLLING SDA WRITE A SINGLE BYTE WRITE UP TO AN 8-BYTE PAGE WITH A SINGLE TRANSACTION READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER COMMUNICATIONS KEY S XX XX XX XX 10 10 00 A 0 0 A MEMORY ADDRESS A DATA A P S 10 10 00 A 0 0 A MEMORY ADDRESS A DATA A DATA A P S 10 10 00 A 0 0 A MEMORY ADDRESS A Sr 10 1 0 0 0 A 0 1 A DATA N P S 10 10 00 A 0 0 A MEMORY ADDRESS A Sr 10 1 0 0 0 A 0 1 A DATA A DATA A DATA A DATA N P NOTES: 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. 2) THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT. Figure 7. I2C Communications Examples