DS42MB200

DS42MB200 NSC | Alldatasheet

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Features

n Dual 2:1 multiplexer and 1:2 buffer n 1– 4.25 Gbps fully differential data paths n Fixed input equalization n Programmable output pre-emphasis n Independent switch and line side pre-emphasis controls n Programmable switch-side loopback mode n On-chip terminations n +3.3V supply n Low power, 1W max n ESD rating HBM 6 kV n Lead-less LLP-48 package (7mmx7mmx0.8mm, 0.5mm pitch) n –40˚C to +85˚C operating temperature range Functional Block Diagram 20178633 May 2006 DS42MB200 Dual 4.25 Gb/s 1:2 Mux/Buffer with Input Equalization and Output Pre-Emphasis © 2006 National Semiconductor Corporation DS201786 www.national.com

www.national.com 2

See NS Package Number SQA48D DS42MB200 www.national.com3

LINE SIDE HIGH SPEED DIFFERENTIAL IO’s LI_0+ LI_0− I Inverting and non-inverting differential inputs of port_0 at the line side. LI_0+ and LI_0− have an internal 50 Ω connected to an internal reference voltage. LO_0+ LO_0− O Inverting and non-inverting differential outputs of port_0 at the line side. LO_0+ and LO_0− have an internal 50 Ω connected to VCC. LI_1+ LI_1− I Inverting and non-inverting differential inputs of port_1 at the line side. LI_1+ and LI_1− have an internal 50 Ω connected to an internal reference voltage. LO_1+ LO_1− O Inverting and non-inverting differential outputs of port_1 at the line side. LO_1+ and LO_1− have an internal 50 Ω connected to VCC. SWITCH SIDE HIGH SPEED DIFFERENTIAL IO’s SOA_0+ SOA_0− O Inverting and non-inverting differential outputs of mux_0 at the switch_A side. SOA_0+ and SOA_0− have an internal 50 Ω connected to V CC. SOB_0+ SOB_0− O Inverting and non-inverting differential outputs of mux_0 at the switch_B side. SOB_0+ and SOB_0− have an internal 50 Ω connected to VCC. SIA_0+ SIA_0− I Inverting and non-inverting differential inputs to the mux_0 at the switch_A side. SIA_0+ and SIA_0− have an internal 50 Ω connected to an internal reference voltage. SIB_0+ SIB_0− I Inverting and non-inverting differential inputs to the mux_0 at the switch_B side. SIB_0+ and SIB_0− have an internal 50 Ω connected to an internal reference voltage. SOA_1+ SOA_1− O Inverting and non-inverting differential outputs of mux_1 at the switch_A side. SOA_1+ and SOA_1− have an internal 50 Ω connected to VCC. SOB_1+ SOB_1− O Inverting and non-inverting differential outputs of mux_1 at the switch_B side. SOB_1+ and SOB_1− have an internal 50 Ω connected to VCC. SIA_1+ SIA_1− I Inverting and non-inverting differential inputs to the mux_1 at the switch_A side. SIA_1+ and SIA_1− have an internal 50 Ω connected to an internal reference voltage. SIB_1+ SIB_1− I Inverting and non-inverting differential inputs to the mux_1 at the switch_B side. SIB_1+ and SIB_1− have an internal 50 Ω connected to an internal reference voltage. CONTROL (3.3V LVCMOS) MUX_S0 37 I A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high. Default state for mux_0 is switch A. MUX_S1 13 A logic low at MUX_S1 selects mux_1 to switch B. MUX_S0 is internally pulled high. Default state for mux_1 is switch A. PREL_0 PREL_1 I PREL_0 and PREL_1 select the output pre-emphasis of the line side drivers (LO_0 ± and LO_1±). PREL_0 and PREL_1 are internally pulled high. See Table 3for line side pre-emphasis levels. PRES_0 PRES_1 I PRES_0 and PRES_1 select the output pre-emphasis of the switch side drivers (SOA_0 ±, SOB_0±, SOA_1± and SOB_1±). PRES_0 and PRES_1 are internally pulled high. See Table 4for switch side pre-emphasis levels. LB0A 47 I A logic low at LB0A enables the internal loopback path from SIA_0 ± to SOA_0±. LB0A is internally pulled high. LB0B 48 I A logic low at LB0B enables the internal loopback path from SIB_0 ± to SOB_0±. LB0B is internally pulled high. LB1A 23 I A logic low at LB1A enables the internal loopback path from SIA_1 ± to SOA_1±. LB1A is internally pulled high. LB1B 24 I A logic low at LB1B enables the internal loopback path from SIB_1 ± to SOB_1±. LB1B is internally pulled high. RSV 26 I Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND through an external pull-down resistor. DS42MB200 www.national.com 4

typically with a via located as close as possible to the landing pad of the V CC pin. ground impedance and improve the thermal performance of the package. from a short backplane trace (about 10 inches backplane). is 200ps nominal, corresponds to 0.75 bit-width at 4 Gb/s. TABLE 1. LOGIC TABLE FOR MULTIPLEX CONTROLS 0 MUX_0 select switch_B input, SIB_0 ±. 1 (default) MUX_0 select switch_A input, SIA_0 ±.

0 MUX_1 select switch_B input, SIB_1

1 (default) MUX_1 select switch_A input, SIA_0 ±. TABLE 2. LOGIC TABLE FOR LOOPBACK Controls 0 Enable loopback from SIA_0 ± to SOA_0±. 1 (default) Normal mode. Loopback disabled.

0 Enable loopback from SIB_0

1 (default) Normal mode. Loopback disabled.

0 Enable loopback from SIA_1

1 (default) Normal mode. Loopback disabled.

0 Enable loopback from SIB_1

1 (default) Normal mode. Loopback disabled.

TABLE 3. LINE-SIDE PRE-EMPHASIS CONTROLS TABLE 4. SWITCH-SIDE PRE-EMPHASIS CONTROLS FIGURE 1. Driver Pre-Emphasis Differential Waveform (showing all 4 pre-emphasis steps)

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC) −0.3V to 4V CMOS/TTL Input Voltage −0.3V to (VCC +0.3V) CML Input/Output Voltage −0.3V to (VCC +0.3V) Junction Temperature +125˚C Storage Temperature −65˚C to +150˚C Lead Temperature Soldering, 4 sec +260˚C Thermal Resistance, θ JA 33.7˚C/W Thermal Resistance, θJC-top 20.7˚C/W Thermal Resistance, θJC-bottom 5.8˚C/W Thermal Resistance,ΦJB 18.2˚C/W ESD Rating HBM, 1.5 k Ω, 100 pF 6 kV ESD Rating Machine Model 250V Recommended Operating Ratings Min Typ Max Units Supply Voltage (VCC-GND) 3.135 3.3 3.465 V Supply Noise Amplitude

10 Hz to 2 GHz

Ambient Temperature 0 85 ˚C Case Temperature 100 ˚C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ (Note 2) Max Units LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC +0.3 V VIL Low Level Input Voltage −0.3 0.8 V IIH High Level Input Current VIN =V CC −10 10 µA IIL Low Level Input Current VIN = GND 75 94 124 µA RPU Pull-High Resistance 35 k Ω RECEIVER SPECIFICATIONS V ID Differential Input Voltage Range AC Coupled Differential Signal Below 1.25 Gb/s At 1.25 Gbps–3.125 Gbps Above 3.125 Gbps This parameter is not production tested. 100 100 100 1750 1560 1200 mV P-P mVP-P mVP-P VICM Common Mode Voltage at Receiver Inputs Measured at receiver inputs reference to ground. 1.3 V R ITD Input Differential Termination On-chip differential termination between IN+ or IN−. 84 100 116 Ω RITSE Input Termination (single-end) On-chip termination IN+ or IN− to GND for frequency > 100 MHz. 50 Ω DRIVER SPECIFICATIONS VODB Output Differential Voltage Swing without Pre-Emphasis R L = 100Ω ±1% PRES_1=PRES_0=0 PREL_1=PREL_0=0 Driver pre-emphasis disabled. Running K28.7 pattern at 4.25 Gbps. See Figure 5for test circuit. 1000 1200 1400 mV P-P DS42MB200 www.national.com7

Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ (Note 2) Max Units DRIVER SPECIFICATIONS VPE Output Pre-Emphasis Voltage Ratio 20*log(VODPE/VODB) R L = 100Ω ±1% Running K28.7 pattern at 4.25 Gbps PREx_[1:0]=00 PREx_[1:0]=01 PREx_[1:0]=10 PREx_[1:0]=11 x=S for switch side pre-emphasis control x=L for line side pre-emphasis control See Figure 1on waveform. See Figure 5for test circuit. dB dB dB dB t PE Pre-Emphasis Width (Note 8) Tested at −9 dB pre-emphasis level, PREx[1:0]=11 x=S for switch side pre-emphasis control x=L for line side pre-emphasis control See Figure 4on measurement condition. 125 200 250 ps R OTSE Output Termination On-chip termination from OUT+ or OUT− to VCC 42 50 58 Ω ROTD Output Differential Termination On-chip differential termination between OUT+ and OUT− 100 Ω ∆ROTSE Mis-Match in Output Termination Resistors Mis-match in output terminations at OUT+ and OUT− 5 % V OCM Output Common Mode Voltage 2.4 2.9 V POWER DISSIPATION PD Power Dissipation V DD = 3.465V All outputs terminated by 100 Ω ±1%. PREL_[1:0]=0, PRES_[1:0]=0 Running PRBS 2 7-1 pattern at 4.25 Gbps AC CHARACTERISTICS tR Differential Low to High Transition Time Measured with a clock-like pattern at

100 MHz, between 20% and 80% of the

differential output voltage. Pre-emphasis disabled. Transition time is measured with fixture as shown in Figure 5, adjusted to reflect the transition time at the output pins. 80 ps t F Differential High to Low Transition Time 80 ps tPLH Differential Low to High Propagation Delay Measured at 50% differential voltage from input to output. 0.5 2 ns t PHL Differential High to Low Propagation Delay 0.5 2 ns t SKP Pulse Skew (Note 8) |t PHL–tPLH|2 0 p s tSKO Output Skew (Notes 7, 8) Difference in propagation delay among data paths in the same device. 200 ps tSKPP Part-to-Part Skew (Note 8) Difference in propagation delay between the same output from devices operating under identical condition. 500 ps DS42MB200 www.national.com 8

Over recommended operating supply and temperature ranges unless otherwise specified. See Figure 5for test circuit. See Figure 5for test circuit. should be operated at these limits. Note 2: Typical parameters measured at V CC = 3.3V, TA = 25˚C. They are for reference purposes and are not production-tested. RJOUT is the total random jitter measured at the output of the device in psrms, RJ IN is the random jitter of the pattern generator driving the device. between port 0 and port 1. An example is the output skew among data paths from SIA_0± to LO_0±, SIB_0± to LO_0±, SIA_1± to LO_1± and SIB_1± to LO_1±. Note 8: Guaranteed by desigh and characterization using statistical analysis. FIGURE 2. Driver Output Transition Time

FIGURE 6. Data input and output eye patterns with driver set to 0 dB pre-emphasis

FIGURE 7. Data input and output eye patterns with driver set to 9dB pre-emphasis

Application Information

FIGURE 8. Application diagram (showing data paths of port 0)

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