Logic IC

DS42BR400TSQ/NOPB

Texas Instruments

DS42BR400 Quad 4.25 Gbps CML Transceiver with Transmit De-Emphasis and Receive Equalization

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or Cable InterconnectPreB_1 PreB_0 PreA_1 PreA_0 EQA EQB FPGA IA3 IA2 IA1 IA0 OB3 OB2 OB1 OB0 OA3 OA2 OA1 OA0 IB3 IB2 IB1 IB0 Connector PreB_1 PreB_0 PreA_1 PreA_0 EQBEQA FPGA Connector IA3 IA2 IA1 IA0 OB3 OB2 OB1 OB0 OA3 OA2 OA1 OA0 IB3 IB2 IB1 IB0 DS42BR400 www.ti.com SNLS221J –MARCH 2006–REVISED APRIL 2013 DS42BR400Quad4.25GbpsCMLTransceiverwithTransmit De-EmphasisandReceiveEqualization Check forSamples: DS42BR400 1FEATURES DESCRIPTION The DS42BR400 isa quad 250 Mbps – 4.25 Gbps 2• 250 Mbps – 4.25Gbps FullyDifferentialData CML transceiver,or 8-channelbuffer,for use inPaths backplane and cable applications.With operation• OptionalFixedInputEqualization down to250 Mbps, theDS42BR400 can be used in

SelectableOutput De-emphasis applicationsrequiringboth low and high frequency datarates.Each inputstagehas a fixedequalizerto• IndividualLoopback Controls reduce ISI distortionfrom board traces. The• On-Chip Termination equalizersare grouped in foursand are enabled
Lead-lessWQFN-60 Pin Package (9mm x 9 throughtwo controlpins.These controlpinsprovide mm x 0.8mm, 0.5mm Pitch) customers flexibilitywhere ISI distortionmay vary fromone directiontoanother.• −40°C to+85°C IndustrialTemperature Range Alloutputdrivershave fourselectablestepsof de-• 6 kV ESD Rating,HBM emphasis to compensate againsttransmissionloss across long FR4 backplanes.The de-emphasisAPPLICATIONS blocksare also grouped in fours.In addition,the• Backplane Driveror Cable Driver DS42BR400 alsohas loopbackcontrolcapabilityon fourchannels.AllCML drivershave 50Ω termination• SignalRepeating,Bufferingand Conditioning to VCC . Allreceiversare internallyterminatedwithApplications differential100Ω. SimplifiedApplicationDiagram Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

IA_3+- IA_2+- OB_3+- OB_2+- OA_3+- OA_2+- IB_3+- IB_2+- LB2 LB3 PreA EQA PreA EQA PreB EQB PreB EQB Port 0/1 IA_1+- IA_0+- OB_1+- OB_0+- OA_1+- OA_0+- IB_1+- IB_0+- LB0 LB1 VDD GND RSV Equalizer Enable Control Pre-Emphasis Control EQBEQA PreA_0 PreA_1 PreB_0 PreB_1 EQA EQBPreA PreB EQB EQB EQB EQB EQA EQA EQA EQA DS42BR400 SNLS221J –MARCH 2006–REVISED APRIL 2013 www.ti.com FunctionalBlock Diagram

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17 18 19 20 21 22 23 24 25 26 27 28 29 30 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46

60 Pin WQFN

DAP = GND PreB_1 LB1 IB_1+ IB_1- VCC OA_1+ OA_1- GND OA_2- OA_2+ VCC IB_2- IB_2+ LB2 PreB_0 EQA RSV IA_0+IA_0- VCC OB_0+OB_0-GND IB_0- IB_0+VCC OA_0-OA_0+GND LB0 PreA_1 GND OB_1+ OB_1- VCC IA_1+ IA_1- GND IA_2- IA_2+ VCC OB_2- OB_2+ GND PreA_0 EQB GND IA_3+IA_3- VCC OB_3+OB_3-GND IB_3- IB_3+VCC OA_3-OA_3+ GND LB3 DS42BR400 www.ti.com SNLS221J –MARCH 2006–REVISED APRIL 2013 Connection Diagram Figure1. LeadlessWQFN-60 Pin Package (9mm x 9 mm x 0.8mm, 0.5mm pitch) See Package Number NKA0060A Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS42BR400

SNLS221J –MARCH 2006–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS Pin Name Pin Number I/O(1) Description DIFFERENTIAL I/O IB_0+ 51 I Invertingand non-invertingdifferentialinputsofport_0.IB_0+ and IB_0− areinternallyconnectedtoa IB_0− 52 referencevoltagethrougha 50Ω resistor.RefertoFigure8. OA_0+ 48 O Invertingand non-invertingdifferentialoutputsofport_0.OA_0+ and OA_0 − areconnectedtoVCC OA_0 − 49 througha 50Ω resistor. IB_1+ 43 I Invertingand non-invertingdifferentialinputsofport_1.IB_1+ and IB_1− areinternallyconnectedtoa IB_1− 42 referencevoltagethrougha 50Ω resistor.RefertoFigure8. OA_1+ 40 O Invertingand non-invertingdifferentialoutputsofport_1.OA_1+ and OA_1 − areconnectedtoVCC OA_1 − 39 througha 50Ω resistor. IB_2+ 33 I Invertingand non-invertingdifferentialinputsofport_2.IB_2+ and IB_2− areinternallyconnectedtoa IB_2− 34 referencevoltagethrougha 50Ω resistor.RefertoFigure8. OA_2+ 36 O Invertingand non-invertingdifferentialoutputsofport_2.OA_2+ and OA_2 − areconnectedtoVCC OA_2 − 37 througha 50Ω resistor. IB_3+ 25 I Invertingand non-invertingdifferentialinputsofport_3.IB_3+ and IB_3− areinternallyconnectedtoa IB_3− 24 referencevoltagethrougha 50Ω resistor.RefertoFigure8. OA_3+ 28 O Invertingand non-invertingdifferentialoutputsofport_3.OA_3+ and OA_3 − areconnectedtoVCC OA_3 − 27 througha 50Ω resistor. IA_0+ 58 I Invertingand non-invertingdifferentialinputsofport_0.IA_0+ and IA_0− areinternallyconnectedtoa IA_0− 57 referencevoltagethrougha 50Ω resistor.RefertoFigure8. OB_0+ 55 O Invertingand non-invertingdifferentialoutputsofport_0.OB_0+ and OB_0 − areconnectedtoVCC OB_0 − 54 througha 50Ω resistor. IA_1+ 6 I Invertingand non-invertingdifferentialinputsofport_1.IA_1+ and IA_1− areinternallyconnectedtoa IA_1− 7 referencevoltagethrougha 50Ω resistor.RefertoFigure8. OB_1+ 3 O Invertingand non-invertingdifferentialoutputsofport_1.OB_1+ and OB_1 − areconnectedtoVCC OB_1 − 4 througha 50Ω resistor. IA_2+ 10 I Invertingand non-invertingdifferentialinputsofport_2.IA_2+ and IA_2− areinternallyconnectedtoa IA_2− 9 referencevoltagethrougha 50Ω resistor.RefertoFigure8. OB_2+ 13 O Invertingand non-invertingdifferentialoutputsofport_2.OB_2+ and OB_2 − areconnectedtoVCC OB_2 − 12 througha 50Ω resistor. IA_3+ 18 I Invertingand non-invertingdifferentialinputsofport_3.IA_3+ and IA_3− areinternallyconnectedtoa IA_3− 19 referencevoltagethrougha 50Ω resistor.RefertoFigure8. OB_3+ 21 O Invertingand non-invertingdifferentialoutputsofport_3.OB_3+ and OB_3 − areconnectedtoVCC OB_3 − 22 througha 50Ω resistor. CONTROL (3.3VLVCMOS) EQA 60 I ThispinisactiveLOW. A logicLOW atEQA enablesequalizationforinputchannelsIA_0±,IA_1±, IA_2±,and IA_3±.By default,thispinisinternallypulledhighand equalizationisdisabled. EQB 16 I ThispinisactiveLOW. A logicLOW atEQB enablesequalizationforinputchannelsIB_0±,IB_1±, IB_2±,and IB_3±.By default,thispinisinternallypulledhighand equalizationisdisabled. PreA_0 15 I PreA_0 and PreA_1 selecttheoutputde-emphasislevels(OA_0±,OA_1 ±,OA_2 ±,and OA_3 ±). PreA_1 1 PreA_0 and PreA_1 areinternallypulledhigh.Pleasesee Table2 forde-emphasislevels. PreB_0 31 I PreB_0 and PreB_1 selecttheoutputde-emphasislevels(OB_0±,OB_1 ±,OB_2 ±,and OB_3 ±). PreB_1 45 PreB_0 and PreB_1 areinternallypulledhigh.Pleasesee Table2 forde-emphasislevels. LB0 46 I ThispinisactiveLOW. A logicLOW atLB0 enablestheinternalloopbackpathfromIB_0± toOA_0 ±. LB0 isinternallypulledhigh.Pleasesee Table1 formore information. LB1 44 I ThispinisactiveLOW. A logicLOW atLB1 enablestheinternalloopbackpathfromIB_1± toOA_1 ±. LB1 isinternallypulledhigh.Pleasesee Table1 formore information. LB2 32 I ThispinisactiveLOW. A logicLOW atLB2 enablestheinternalloopbackpathfromIB_2± toOA_2 ±. LB2 isinternallypulledhigh.Pleasesee Table1 formore information. LB3 30 I ThispinisactiveLOW. A logicLOW atLB3 enablestheinternalloopbackpathfromIB_3± toOA_3 ±. LB3 isinternallypulledhigh.Pleasesee Table1 formore information. RSV 59 I Reservepintosupportfactorytesting.Thispincan be leftopen,tiedtoGND, ortiedtoGND through an externalpull-downresistor. (1) Note:I= Input,O = Output,P = Power

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www.ti.com SNLS221J –MARCH 2006–REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O(1) Description POWER 35,41,50, Each VCC pinshouldbe connectedtotheVCC planethrougha lowinductancepath,typicallywitha 56 vialocatedas closeas possibletothelandingpad oftheVCC pin. Itisrecommended tohave a 0.01μF or0.1μF,X7R, size-0402bypasscapacitorfromeach VCC pin togroundplane. GND 2,8,14,17, P Ground reference.Each groundpinshouldbe connectedtothegroundplanethrougha low 23,29,38, inductancepath,typicallywitha vialocatedas closeas possibletothelandingpad oftheGND pin. 47,53 GND DAP P DAP isthemetalcontactatthebottomside,locatedatthecenteroftheWQFN-60 pinpackage.It shouldbe connectedtotheGND planewithatleast4 viatolowerthegroundimpedance and improve thethermalperformanceofthepackage. FunctionalDescription Table1. Logic TableforLoopback Controls LB0 Loopback Function 0 EnableloopbackfromIB_0± toOA_0 ±. 1 (default) Normal mode. Loopback disabled. LB1 Loopback Function 0 EnableloopbackfromIB_1± toOA_1 ±. 1 (default) Normal mode. Loopback disabled. LB2 Loopback Function 0 EnableloopbackfromIB_2± toOA_2 ±. 1 (default) Normal mode. Loopback disabled. LB3 Loopback Function 0 EnableloopbackfromIB_3± toOA_3 ±. 1 (default) Normal mode. Loopback disabled. Table2. De-Emphasis Controls De-Emphasis LevelinmV PPPreA_[1:0] DefaultVOD LevelinmV PP (VODB) De-Emphasis indB (VODPE/VODB)(VODPE) 0 0 1200 1200 0 0 1 1200 850 −3 1 0 1200 600 −6 1 1 (Default) 1200 426 −9 De-Emphasis LevelinmV PPPreB_[1:0] DefaultVOD LevelinmV PP (VODB) De-Emphasis indB (VODPE/VODB)(VODPE) 0 0 1200 1200 0 0 1 1200 850 −3 1 0 1200 600 −6 1 1 (Default) 1200 426 −9 Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS42BR400

1-bit 1 to N bits 1-bit 1 to N bits 0 dB -3 dB -6 dB -9 dB DS42BR400 SNLS221J –MARCH 2006–REVISED APRIL 2013 www.ti.com De-emphasisistheprimarysignalconditioningfunctionforuse incompensatingagainstbackplanetransmission loss.The DS42BR400 providesfourstepsof de-emphasisrangingfrom 0,−3,−6 and −9 dB, user-selectable dependent on the lossprofileof the backplane.Figure2 shows a driverde-emphasis waveform. The de- emphasisdurationisnominal200 ps,correspondingto85% bit-widthat4.25Gbps. The highspeed inputsareself-biasedtoabout1.3V and aredesignedforAC couplingallowingtheDS42BR400 to be directlyinsertedintothe datapathwithoutany limitation.The idealAC couplingcapacitorvalueisoften based on thelowestfrequencycomponent embedded withintheseriallink.A typicalAC couplingcapacitorvalue rages between 100 and 1000nF, some specificationswith scrambled data may requirea largercoupling capacitorforoptimalperformance.To reduceunwanted parasiticsaroundand withintheAC couplingcapacitor,a body sizeof0402 isrecommended. Figure7 shows theAC couplingcapacitorplacementinan AC testcircuit. InputEqualization Each differentialinputoftheDS42BR400 has a fixedequalizerfront-endstage.Itisdesignedtoprovidefixed equalizationforshortboard traceswithtransmissionlossesofapproximately5 dB between 375 MHz to1.875 GHz. Programmable de-emphasistogetherwithinputequalizationensuresan acceptableeye openingfora 40- inchFR-4 backplane. The differentialinputequalizerforinputson Channel A and inputson Channel B can be bypassed by usingEQA and EQB, respectively.By default,the equalizersare internallypulledhighand disabled.Therefore,EQA and EQB must be assertedLOW toenableequalization. Figure2. DriverDe-Emphasis DifferentialWaveform (showing all4 de-emphasis steps) These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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www.ti.com SNLS221J –MARCH 2006–REVISED APRIL 2013 AbsoluteMaximum Ratings(1)(2) SupplyVoltage(VCC ) −0.3Vto4V CMOS/TTL InputVoltage −0.3Vto(VCC +0.3V) CML Input/OutputVoltage −0.3Vto(VCC +0.3V) JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead TemperatureSoldering,4 sec +260°C ThermalResistance,θJA 22.3°C/W ThermalResistance,θJC 3.2°C/W ThermalResistance,ΦJB 10.3°C/W ESD Ratings(3) HBM 6kV CDM 1kV MM 350V (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional.Forensuredspecificationsand thetestconditions,see theElectricalCharacteristicsTables.Operationof thedevicebeyond themaximum OperatingRatingsisnotrecommended. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (3) ESD testsconformtothefollowingstandards:HumanBody Model (HBM) applicablestandard:MIL-STD-883,Method 3015.7Machine Model (MM) applicablestandard:JESD22-A115-A (ESD MM std.ofJEDEC)Field-InducedCharge DeviceModel (CDM) applicable standard:JESD22-C101-C (ESD FICDM std.ofJEDEC) Recommended OperatingRatings Min Typ Max Units SupplyVoltage(VCC -GND) 3.135 3.3 3.465 V SupplyNoiseAmplitude 10 Hz to2 GHz 100 mV PP AmbientTemperature −40 +85 °C Case Temperature 100 °C Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS42BR400

SNLS221J –MARCH 2006–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(1)(2) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. TypParameter TestConditions Min Max Units(3) LVCMOS DC SPECIFICATIONS VIH HighLevelInput 2.0 VCC +0.3 VVoltage VIL Low LevelInput −0.3 0.8 VVoltage IIH HighLevelInput VIN = VCC −10 10 µACurrent IIL Low LevelInputCurrent VIN = GND 75 94 124 µA R PU Pull-HighResistance 35 kΩ RECEIVER SPECIFICATIONS VID DifferentialInput AC CoupledDifferentialSignal. VoltageRange Below 1.25Gb/s 100 1750 mV P-P At1.25Gbps –3.125Gbps 100 1560 mV P-P Above 3.125Gbps 100 1200 mV P-P Thisparameterisnotproductiontested. VICM Common Mode Voltage Measured atreceiverinputsreferencetoground. 1.3 VatReceiverInputs R ITD InputDifferential On-chipdifferentialtermination 84 100 116 ΩTermination between IN+ orIN−.SeeFigure8 DRIVER SPECIFICATIONS VODB OutputDifferential R L = 100Ω ±1% VoltageSwing without PreA_1 = 0;PreA_0 = 0 De-Emphasis PreB_1 = 0;PreB_0 = 0 1000 1200 1400 mV P-PDriverde-emphasisdisabled. RunningK28.7patternat4 Gbps. See(Figure7) VPE OutputDe-Emphasis R L = 100Ω ±1% VoltageRatio RunningK28.7patternat4.25Gbps 20*log(VODPE/VODB) PreX_[1:0]= 00 0 dB PreX_[1:0]= 01 −3 dB PreX_[1:0]= 10 −6 dB PreX_[1:0]= 11 −9 dB X = A/B channelde-emphasisdrivers See(Figure2/Figure7) tPE De-Emphasis Width Testedat−9 dB de-emphasislevel,PreX[1:0]= 11 X = A/B channelde-emphasisdrivers 125 200 250 ps See Figure6 on measurement condition. R OTSE OutputTermination On-chipterminationfromOUT+ orOUT − toVCC 42 50 58 Ω R OTD OutputDifferential On-chipdifferentialterminationbetween OUT+ and 100 ΩTermination OUT − ΔR OTSE Mis-MatchinOutput Mis-matchinoutputterminationresistors 5 %TerminationResistors VOCM OutputCommon Mode 2.7 VVoltage POWER DISSIPATION PD Power Dissipation VDD = 3.465V Alloutputsterminatedby 100Ω ±1%. 1.3 WPreB_[1:0]= 0,PreA_[1:0]= 0 RunningPRBS 27-1patternat4.25Gbps (1) IN+ and IN− aregenericnames thatrefertoone ofthemany pairsofcomplementaryinputsoftheDS42BR400. OUT+ and OUT − are genericnames thatrefertoone ofthemany pairsofthecomplementaryoutputsoftheDS42BR400. DifferentialinputvoltageVID is definedas |IN+– IN−|.DifferentialoutputvoltageVOD isdefinedas |OUT+ – OUT −|. (2) K28.7patternisa 10-bitrepeatingpatternofK28.7code group{0011111000}K28.5patternisa 20-bitrepeatingpatternof+K28.5 and −K28.5code groups{1100000101 001111 1010} (3) TypicalspecificationsareatTA=25 C, and representmost likelyparametricnorms atthetimeofproductcharacterization.The typical specificationsarenotensured.

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www.ti.com SNLS221J –MARCH 2006–REVISED APRIL 2013 ElectricalCharacteristics(1)(2)(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. TypParameter TestConditions Min Max Units(3) AC CHARACTERISTICS tR DifferentialLow toHigh Measured witha clock-likepatternat4.25Gbps, 80 psTransitionTime between 20% and 80% ofthedifferentialoutput voltage.tF DifferentialHightoLow De-emphasisdisabled.TransitionTime Transitiontimeismeasured withthefixtureshown in 80 ps Figure7 adjustedtoreflectthetransitiontimeatthe outputpins. tPLH DifferentialLow toHigh Measured at50% differentialvoltagefrominputto 1 nsPropagationDelay output. tPHL DifferentialHightoLow 1 nsPropagationDelay tSKP PulseSkew |tPHL –tPLH | 20 ps tSKO OutputSkew (4) Differenceinpropagationdelaybetween channels on thesame part 100 ps (Channel-to-ChannelSkew)(4) tSKPP Part-to-PartSkew (4) Differenceinpropagationdelaybetween devices acrossallchannelsoperatingunderidentical 165 ps conditions tLB Loopback DelayTime Delayfromenablingloopbackmode tosignals appearingatthedifferentialoutputs 4 ns SeeFigure5 RJ DeviceRandom Jitter(5) At0.25Gbps 2 ps rms At1.5Gbps 2 ps rms At4.25Gbps 2 ps rms Alternating-10pattern. De-emphasisdisabled. See(Figure7) DJ DeviceDeterministic At0.25Mbps, PRBS7 pattern 25 ps pp Jitter(6) At1.5Gbps, K28.5pattern 25 ps pp At4.25Gbps, K28.5pattern 25 ps pp At4.25Gbps, PRBS7 pattern 25 ps pp De-emphasisdisabled. See(Figure7) DR Data Rate(7) Alternating-10pattern 0.25 4.25 Gbps (4) tSKO isthemagnitudedifferenceinpropagationdelaysbetween alldatapathson one device.Thisischannel-to-channelskew.tSKPP is theworstcase differenceinpropagationdelayacrossmultipledeviceson allchannelsand operatingunderidenticalconditions.For example,fortwo devicesoperatingunderthesame conditions,tSKPP isthemagnitudedifferencebetween theshortestpropagation delaymeasurement on one devicetothelongestpropagationdelaymeasurement on anotherdevice. (5) Deviceoutputrandom jitterisa measurement ofrandom jittercontributedby thedevice.Itisderivedby theequationSQRT[(RJ OUT )2 – (RJIN)2],where RJOUT isthetotalrandom jittermeasured attheoutputofthedeviceinps(rms),RJIN istherandom jitterofthepattern generatordrivingthedevice.Below 400 Mbps, systemjitterand devicejittercouldnotbe separated.The 250 Mbps specification includessystemrandom jitter.Pleasesee Figure7 fortheAC testcircuit. (6) Deviceoutputdeterministicjitterisa measurement ofthedeterministicjittercontributionfromthedevice.Itisderivedby theequation (DJOUT -DJIN),where DJOUT isthetotalpeak-to-peakdeterministicjittermeasured attheoutputofthedeviceinps(p-p).DJIN isthe peak-to-peakdeterministicjitterattheinputofthetestboard.Pleasesee Figure7 fortheAC testcircuit. (7) Thisparameterisspecifiedby designand/orcharacterizationand isnottestedinproduction. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS42BR400

1-bit 1 to N bits 1-bit 1 to N bits -9 dB 20% tPE 80% VODB Data Output Data Input Loopback Enable 50% 50% tLB 50% VID 50% VOD tPLH tPHL IN OUT 80% 20% 80% 20% tR tF VODB DS42BR400 SNLS221J –MARCH 2006–REVISED APRIL 2013 www.ti.com TIMING DIAGRAMS Figure3. DriverOutput TransitionTime Figure4. PropagationDelay Figure5. Loopback Delay Timing Figure6. Output De-Emphasis Duration

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3.9k IN + EQ 180 pF IN - 50+-1% 50 +-1% Pattern Generator Oscilloscope or Jitter Measurement Instrument50: TLVCC GND Coax Coax 50: TL < 2" DC Block 1000 mVpp Differential OUT+ OUT- IN+ IN- R D M U X DS42BR400 EQ Coax Coax DC Block DS42BR400 Test Fixture INPUT TL INPUT TL DS42BR400 www.ti.com SNLS221J –MARCH 2006–REVISED APRIL 2013 Figure7. AC TestCircuit Figure8. ReceiverInputTermination Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS42BR400

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REVISION HISTORY

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www.ti.com 12-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS42BR400TSQ/NOPB ACTIVE WQFN NKA 60 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 DS42BR400 TSQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS42BR400TSQ/NOPB WQFN NKA 60 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Pack Materials-Page 2

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