DS42BR400TSQ

DS42BR400 NSC | Alldatasheet

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Features

n Quad 4.25 Gbps Transceiver or 8-Channel CML Serial Buffer n 250 Mbps – 4.25 Gbps Fully Differential Data Paths n Optional Fixed Input Equalization n Selectable Output De-emphasis n Individual Loopback Controls n On-chip Termination n +3.3V supply n Low Power, 1.3 Watts MAX n Lead-less eLLP-60 pin package (9mmx9mmx0.8mm, 0.4mm pitch) n −40˚C to +85˚C Industrial Temperature Range n 6 kV ESD Rating, HBM Functional Block Diagram 20182401 May 2006 DS42BR400 Quad Transceiver with Input Equalization and Output De-Emphasis © 2006 National Semiconductor Corporation DS201824 www.national.com

Leadless eLLP-60 Pin Package (9mmx9mmx0.8mm, 0.4mm pitch) Order number DS42BR400TSQ See NS Package Number SQA060 DS42BR400 www.national.com 2

IB_0+ IB_0− I Inverting and non-inverting differential inputs of port_0. IB_0+ and IB_0− are internally connected to a reference voltage through a 50 Ω resistor. OA_0+ OA_0− O Inverting and non-inverting differential outputs of port_0. OA_0+ and OA_0− are connected to VCC through a 50Ω resistor. IB_1+ IB_1− I Inverting and non-inverting differential inputs of port_1. IB_1+ and IB_1− are internally connected to a reference through a 50 Ω resistor. OA_1+ OA_1− O Inverting and non-inverting differential outputs of port_1. OA_1+ and OA_1− are connected to VCC through a 50Ω resistor. IB_2+ IB_2− I Inverting and non-inverting differential inputs of port_2. IB_2+ and IB_2− are internally connected to a reference voltage through a 50 Ω resistor. OA_2+ OA_2− O Inverting and non-inverting differential outputs of port_2. OA_2+ and OA_2− are connected to VCC through a 50Ω resistor. IB_3+ IB_3− I Inverting and non-inverting differential inputs of port_3. IB_3+ and IB_3− are internally connected to a reference voltage through a 50 Ω resistor. OA_3+ OA_3− O Inverting and non-inverting differential outputs of port_3. OA_3+ and OA_3− are connected to VCC through a 50Ω resistor. IA_0+ IA_0− I Inverting and non-inverting differential inputs of port_0. IA_0+ and IA_0− are internally connected to a reference voltage through a 50 Ω resistor. OB_0+ OB_0− O Inverting and non-inverting differential outputs of port_0. OB_0+ and OB_0− are connected to VCC through a 50Ω resistor. IA_1+ IA_1− I Inverting and non-inverting differential inputs of port_1. IA_1+ and IA_1− are internally connected to a reference through a 50 Ω resistor. OB_1+ OB_1− O Inverting and non-inverting differential outputs of port_1. OB_1+ and OB_1− are connected to VCC through a 50Ω resistor. IA_2+ IA_2− I Inverting and non-inverting differential inputs of port_2. IA_2+ and IA_2− are internally connected to a reference voltage through a 50 Ω resistor. OB_2+ OB_2− O Inverting and non-inverting differential outputs of port_2. OB_2+ and OB_2− are connected to VCC through a 50Ω resistor. IA_3+ IA_3− I Inverting and non-inverting differential inputs of port_3. IA_3+ and IA_3− are internally connected to a reference voltage through a 50 Ω resistor. OB_3+ OB_3− O Inverting and non-inverting differential outputs of port_3. OB_3+ and OB_3− are connected to VCC through a 50Ω resistor. CONTROL (3.3V LVCMOS) EQA 60 I This pin is active LOW. A logic LOW at EQA enables equalization for input channels IA_0±, IA_1±, IA_2±, and IA_3 ±. By default, this pin is internally pulled high and equalization is disabled. EQB 16 I This pin is active LOW. A logic LOW at EQB enables equalization for input channels IB_0±, IB_1±, IB_2±, and IB_3 ±. By default, this pin is internally pulled high and equalization is disabled. PreA_0 PreA_1 I PreA_0 and PreA_1 select the output de-emphasis levels (OA_0 ±, OA_1±, OA_2±, and OA_3±). PreA_0 and PreA_1 are internally pulled high. Please see Table 2for de-emphasis levels. PreB_0 PreB_1 I PreB_0 and PreB_1 select the output de-emphasis levels (OB_0 ±, OB_1±, OB_2±, and OB_3±). PreB_0 and PreB_1 are internally pulled high. Please see Table 2for de-emphasis levels. LB0 46 I This pin is active LOW. A logic LOW at LB0 enables the internal loopback path from IB_0 ± to OA_0±. LB0 is internally pulled high. Please see Table 1for more information. LB1 44 I This pin is active LOW. A logic LOW at LB1 enables the internal loopback path from IB_1 ± to OA_1±. LB1 is internally pulled high. Please see Table 1for more information. DS42BR400 www.national.com3

Pin Descriptions (Continued) Pin Name Pin Number I/O Description CONTROL (3.3V LVCMOS) LB2 32 I This pin is active LOW. A logic LOW at LB2 enables the internal loopback path from IB_2 ± to OA_2±. LB2 is internally pulled high. Please see Table 1for more information. LB3 30 I This pin is active LOW. A logic LOW at LB3 enables the internal loopback path from IB_3 ± to OA_3±. LB3 is internally pulled high. Please see Table 1for more information. RSV 59 I Reserve pin to support factory testing. This pin can be left open, tied to GND, or tied to GND through an external pull-down resistor. POWER V CC 5, 11, 20, 26, 35, 41, 50, 56 PV CC = 3.3V ± 5%. Each VCC pin should be connected to the V CC plane through a low inductance path, typically with a via located as close as possible to the landing pad of the V CC pin. It is recommended to have a 0.01 µF or 0.1 µF, X7R, size-0402 bypass capacitor from each V CC pin to ground plane. GND 8, 14, 23, 29, 38, 47, P Ground reference. Each ground pin should be connected to the ground plane through a low inductance path, typically with a via located as close as possible to the landing pad of the GND pin. GND DAP P DAP is the metal contact at the bottom side, located at the center of the eLLP-60 pin package. It should be connected to the GND plane with at least 4 via to lower the ground impedance and improve the thermal performance of the package. Note: I = Input, O = Output, P = Power DS42BR400 www.national.com 4

TABLE 1. Logic Table for Loopback Controls 0 Enable loopback from IB_0 ± to OA_0±. 1 (default) Normal mode. Loopback disabled. 0 Enable loopback from IB_1 ± to OA_1±. 1 (default) Normal mode. Loopback disabled. 0 Enable loopback from IB_2 ± to OA_2±. 1 (default) Normal mode. Loopback disabled. 0 Enable loopback from IB_3 ± to OA_3±. 1 (default) Normal mode. Loopback disabled. TABLE 2. De-Emphasis Controls use in compensating against backplane transmission loss. nal 188 ps, corresponding to 0.75 bit-width at 4.25 Gbps.

proximately 5 dB between 375 MHz to 1.875 GHz. asserted LOW to enable equalization. FIGURE 1. Driver De-Emphasis Differential Waveform (showing all 4 de-emphasis steps)

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC) −0.3V to 4V CMOS/TTL Input Voltage −0.3V to (VCC +0.3V) CML Input/Output Voltage −0.3V to (VCC +0.3V) Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature Soldering, 4 sec +260˚C Thermal Resistance, θ JA 22.3˚C/W Thermal Resistance, θJC 3.2˚C/W Thermal Resistance, ΦJB 10.3˚C/W (Note: assumes 26 thermal vias) ESD Ratings HBM 6kV CDM 1kV MM 350V Recommended Operating Ratings Min Typ Max Units Supply Voltage (VCC-GND) 3.135 3.3 3.465 V Supply Noise Amplitude

10 Hz to 2 GHz

Ambient Temperature −40 +85 ˚C Case Temperature 100 ˚C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ (Note 2) Max Units LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC +0.3 V VIL Low Level Input Voltage −0.3 0.8 V IIH High Level Input Current VIN =V CC −10 10 µA IIL Low Level Input Current VIN = GND 75 94 124 µA RPU Pull-High Resistance 35 k Ω RECEIVER SPECIFICATIONS V ID Differential Input Voltage Range AC Coupled Differential Signal. Below 1.25 Gb/s At 1.25 Gbps–3.125 Gbps Above 3.125 Gbps This parameter is not production tested. 100 100 100 1750 1560 1200 mV P-P mVP-P mVP-P VICM Common Mode Voltage at Receiver Inputs Measured at receiver inputs reference to ground. 1.3 V R ITD Input Differential Termination On-chip differential termination between IN+ or IN−. 84 100 116 Ω RITSE Input Termination (single-ended) On-chip termination IN+ or IN− to GND for frequency > 100 MHz. 50 Ω DRIVER SPECIFICATIONS VODB Output Differential Voltage Swing without De-Emphasis R L = 100Ω ±1% PreA_1 = 0; PreA_0 = 0 PreB_1 = 0; PreB_0 = 0 Driver de-emphasis disabled. Running K28.7 pattern at 4 Gbps. (Figure 6) 1000 1200 1400 mV P-P DS42BR400 www.national.com7

Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ (Note 2) Max Units DRIVER SPECIFICATIONS VPE Output De-Emphasis Voltage Ratio 20*log(VODPE/VODB) R L = 100Ω ±1% Running K28.7 pattern at 4.25 Gbps PreX_[1:0] = 00 PreX_[1:0] = 01 PreX_[1:0] = 10 PreX_[1:0] = 11 X = A/B channel de-emphasis drivers (Figure 1/ Figure 6) dB dB dB dB t PE De-Emphasis Width Tested at −9 dB de-emphasis level, PreX[1:0] =1 1 X = A/B channel de-emphasis drivers See Figure 5on measurement condition. 125 200 250 ps R OTSE Output Termination On-chip termination from OUT+ or OUT− to VCC 42 50 58 Ω ROTD Output Differential Termination On-chip differential termination between OUT+ and OUT− 100 Ω ∆ROTSE Mis-Match in Output Termination Resistors Mis-match in output termination resistors V OCM Output Common Mode Voltage 2.7 V POWER DISSIPATION PD Power Dissipation V DD = 3.465V All outputs terminated by 100 Ω ±1%. PreB_[1:0] = 0, PreA_[1:0] = 0 Running PRBS 2 7-1 pattern at 4.25 Gbps 1.3 W AC CHARACTERISTICS tR Differential Low to High Transition Time Measured with a clock-like pattern at

4.25 Gbps, between 20% and 80% of the

differential output voltage. De-emphasis disabled. Transition time is measured with the fixture shown in Figure 6adjusted to reflect the transition time at the output pins. 80 ps t F Differential High to Low Transition Time 80 ps tPLH Differential Low to High Propagation Delay Measured at 50% differential voltage from input to output. 1 ns t PHL Differential High to Low Propagation Delay 1n s t SKP Pulse Skew |t PHL–tPLH|2 0 p s tSKO Output Skew (Note 7) Difference in propagation delay between channels on the same part (Channel-to-Channel Skew)(Note 7) 100 ps t SKPP Part-to-Part Skew (Note 7) Difference in propagation delay between devices across all channels operating under identical conditions 165 ps t LB Loopback Delay Time Delay from enabling loopback mode to signals appearing at the differential outputs Figure 4 4n s DS42BR400 www.national.com 8

Over recommended operating supply and temperature ranges unless otherwise specified. VOD is defined as |OUT+ – OUT−|. system jitter and device jitter could not be separated. The 250 Mbps specification includes system random jitter. Please see Figure 6for the AC test circuit. board.. Please see Figure 6for the AC test circuit. measurement on another device. Note 8: This parameter is guaranteed by design and/or characterization and is not tested in production. FIGURE 2. Driver Output Transition Time

FIGURE 6. AC Test Circuit

Physical Dimensions inches (millimeters) unless otherwise noted eLLP-60 Package Order Number DS42BR400TSQ National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. Leadfree products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com DS42BR400 Quad Transceiver with Input Equalization and Output De-Emphasis