DS42BR400

DS42BR400_07 NSC | Alldatasheet

Document overview

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Technical content

Features

■ 250 Mbps – 4.25 Gbps Fully Differential Data Paths ■ Optional Fixed Input Equalization ■ Selectable Output De-emphasis ■ Individual Loopback Controls ■ On-chip Termination ■ Lead-less eLLP-60 pin package (9mmx9mm) ■ −40°C to +85°C Industrial Temperature Range ■ 6 kV ESD Rating, HBM

Applications

■ Backplane driver or cable driver ■ Signal repeating, buffering and conditioning applications ■ XAUI Functional Block Diagram 20182401 © 2007 National Semiconductor Corporation 201824 www.national.com DS42BR400 Quad 4.25 Gbps CMLTransceiver with De-Emphasis and Equalization

Leadless eLLP-60 Pin Package (9mmx9mmx0.8mm, 0.4mm pitch) Order number DS42BR400TSQ See NS Package Number SQA060 www.national.com 2 DS42BR400

Pin Name Pin Number I/O Description DIFFERENTIAL I/O IB_0+ IB_0− I Inverting and non-inverting differential inputs of port_0. IB_0+ and IB_0− are internally connected to a reference voltage through a 50Ω resistor. OA_0+ OA_0− O Inverting and non-inverting differential outputs of port_0. OA_0+ and OA_0− are connected to VCC through a 50Ω resistor. IB_1+ IB_1− I Inverting and non-inverting differential inputs of port_1. IB_1+ and IB_1− are internally connected to a reference through a 50Ω resistor. OA_1+ OA_1− O Inverting and non-inverting differential outputs of port_1. OA_1+ and OA_1− are connected to VCC through a 50Ω resistor. IB_2+ IB_2− I Inverting and non-inverting differential inputs of port_2. IB_2+ and IB_2− are internally connected to a reference voltage through a 50Ω resistor. OA_2+ OA_2− O Inverting and non-inverting differential outputs of port_2. OA_2+ and OA_2− are connected to VCC through a 50Ω resistor. IB_3+ IB_3− I Inverting and non-inverting differential inputs of port_3. IB_3+ and IB_3− are internally connected to a reference voltage through a 50Ω resistor. OA_3+ OA_3− O Inverting and non-inverting differential outputs of port_3. OA_3+ and OA_3− are connected to VCC through a 50Ω resistor. IA_0+ IA_0− I Inverting and non-inverting differential inputs of port_0. IA_0+ and IA_0− are internally connected to a reference voltage through a 50Ω resistor. OB_0+ OB_0− O Inverting and non-inverting differential outputs of port_0. OB_0+ and OB_0− are connected to VCC through a 50Ω resistor. IA_1+ IA_1− I Inverting and non-inverting differential inputs of port_1. IA_1+ and IA_1− are internally connected to a reference through a 50Ω resistor. OB_1+ OB_1− O Inverting and non-inverting differential outputs of port_1. OB_1+ and OB_1− are connected to VCC through a 50Ω resistor. IA_2+ IA_2− I Inverting and non-inverting differential inputs of port_2. IA_2+ and IA_2− are internally connected to a reference voltage through a 50Ω resistor. OB_2+ OB_2− O Inverting and non-inverting differential outputs of port_2. OB_2+ and OB_2− are connected to VCC through a 50Ω resistor. IA_3+ IA_3− I Inverting and non-inverting differential inputs of port_3. IA_3+ and IA_3− are internally connected to a reference voltage through a 50Ω resistor. OB_3+ OB_3− O Inverting and non-inverting differential outputs of port_3. OB_3+ and OB_3− are connected to VCC through a 50Ω resistor. CONTROL (3.3V LVCMOS) EQA 60 I This pin is active LOW. A logic LOW at EQA enables equalization for input channels IA_0±, IA_1±, IA_2±, and IA_3±. By default, this pin is internally pulled high and equalization is disabled. EQB 16 I This pin is active LOW. A logic LOW at EQB enables equalization for input channels IB_0±, IB_1±, IB_2±, and IB_3±. By default, this pin is internally pulled high and equalization is disabled. PreA_0 PreA_1 I PreA_0 and PreA_1 select the output de-emphasis levels (OA_0±, OA_1±, OA_2±, and OA_3±). PreA_0 and PreA_1 are internally pulled high. Please see Table 2 for de-emphasis levels. PreB_0 PreB_1 I PreB_0 and PreB_1 select the output de-emphasis levels (OB_0±, OB_1±, OB_2±, and OB_3±). PreB_0 and PreB_1 are internally pulled high. Please see Table 2 for de-emphasis levels. LB0 46 I This pin is active LOW. A logic LOW at LB0 enables the internal loopback path from IB_0± to OA_0 ±. LB0 is internally pulled high. Please see Table 1 for more information. LB1 44 I This pin is active LOW. A logic LOW at LB1 enables the internal loopback path from IB_1± to OA_1 ±. LB1 is internally pulled high. Please see Table 1 for more information. LB2 32 I This pin is active LOW. A logic LOW at LB2 enables the internal loopback path from IB_2± to OA_2 ±. LB2 is internally pulled high. Please see Table 1 for more information. LB3 30 I This pin is active LOW. A logic LOW at LB3 enables the internal loopback path from IB_3± to OA_3 ±. LB3 is internally pulled high. Please see Table 1 for more information. 3 www.national.com DS42BR400

Pin Name Pin Number I/O Description RSV 59 I Reserve pin to support factory testing. This pin can be left open, tied to GND, or tied to GND through an external pull-down resistor. POWER VCC 5, 11, 20, 26, 35, 41, 50, P VCC = 3.3V ± 5%. Each VCC pin should be connected to the VCC plane through a low inductance path, typically with a via located as close as possible to the landing pad of the VCC pin. It is recommended to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each VCC pin to ground plane. GND 2, 8, 14, 17, 23, 29, 38, 47, 53 P Ground reference. Each ground pin should be connected to the ground plane through a low inductance path, typically with a via located as close as possible to the landing pad of the GND pin. GND DAP P DAP is the metal contact at the bottom side, located at the center of the eLLP-60 pin package. It should be connected to the GND plane with at least 4 via to lower the ground impedance and improve the thermal performance of the package. Note: I = Input, O = Output, P = Power www.national.com 4 DS42BR400

TABLE 1. Logic Table for Loopback Controls 0 Enable loopback from IB_0± to OA_0±. 1 (default) Normal mode. Loopback disabled. 0 Enable loopback from IB_1± to OA_1±. 1 (default) Normal mode. Loopback disabled. 0 Enable loopback from IB_2± to OA_2±. 1 (default) Normal mode. Loopback disabled. 0 Enable loopback from IB_3± to OA_3±. 1 (default) Normal mode. Loopback disabled. TABLE 2. De-Emphasis Controls use in compensating against backplane transmission loss.

asserted LOW to enable equalization. FIGURE 1. Driver De-Emphasis Differential Waveform (showing all 4 de-emphasis steps)

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to 4V CMOS/TTL Input Voltage −0.3V to (VCC +0.3V) CML Input/Output Voltage −0.3V to (VCC +0.3V) Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature Soldering, 4 sec +260°C Thermal Resistance, θJA 22.3°C/W Thermal Resistance, θJC 3.2°C/W Thermal Resistance, ΦJB 10.3°C/W (Note: assumes 26 thermal vias) ESD Ratings HBM 6kV CDM 1kV MM 350V Recommended Operating Ratings Min Typ Max Units Supply Voltage (VCC-GND) 3.13 3.3 3.465 V Supply Noise Amplitude

10 Hz to 2 GHz

Ambient Temperature −40 +85 °C Case Temperature 100 °C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ (Note 2) Max Units LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC +0.3 V VIL Low Level Input Voltage −0.3 0.8 V IIH High Level Input Current VIN = VCC −10 10 µA IIL Low Level Input Current VIN = GND 75 94 124 µA RPU Pull-High Resistance 35 kΩ RECEIVER SPECIFICATIONS VID Differential Input Voltage Range AC Coupled Differential Signal. Below 1.25 Gb/s At 1.25 Gbps–3.125 Gbps Above 3.125 Gbps This parameter is not production tested. 100 100 100 1750 1560 1200 mVP-P mVP-P mVP-P VICM Common Mode Voltage at Receiver Inputs Measured at receiver inputs reference to ground. 1.3 V RITD Input Differential Termination On-chip differential termination between IN+ or IN −. 84 100 116 Ω RITSE Input Termination (single-ended) On-chip termination IN+ or IN− to GND for frequency > 100 MHz. 50 Ω DRIVER SPECIFICATIONS VODB Output Differential Voltage Swing without De-Emphasis RL = 100Ω ±1% PreA_1 = 0; PreA_0 = 0 PreB_1 = 0; PreB_0 = 0 Driver de-emphasis disabled. Running K28.7 pattern at 4 Gbps. (Figure 6) 1000 1200 1400 mVP-P 7 www.national.com DS42BR400

Symbol Parameter Conditions Min Typ (Note 2) Max Units VPE Output De-Emphasis Voltage Ratio 20*log(VODPE/VODB) RL = 100Ω ±1% Running K28.7 pattern at 4.25 Gbps PreX_[1:0] = 00 PreX_[1:0] = 01 PreX_[1:0] = 10 PreX_[1:0] = 11 X = A/B channel de-emphasis drivers (Figure 1 / Figure 6) dB dB dB dB tPE De-Emphasis Width Tested at −9 dB de-emphasis level, PreX[1:0] = 11 X = A/B channel de-emphasis drivers See Figure 5 on measurement condition. 125 200 250 ps ROTSE Output Termination On-chip termination from OUT+ or OUT− to VCC 42 50 58 Ω ROTD Output Differential Termination On-chip differential termination between OUT+ and OUT− 100 Ω ΔROTSE Mis-Match in Output Termination Resistors Mis-match in output termination resistors 5 % VOCM Output Common Mode Voltage 2.7 V POWER DISSIPATION PD Power Dissipation VDD = 3.465V All outputs terminated by 100Ω ±1%. PreB_[1:0] = 0, PreA_[1:0] = 0 Running PRBS 27-1 pattern at 4.25 Gbps 1.3 W AC CHARACTERISTICS tR Differential Low to High Transition Time Measured with a clock-like pattern at 4.25 Gbps, between 20% and 80% of the differential output voltage. De-emphasis disabled. Transition time is measured with the fixture shown in Figure 6 adjusted to reflect the transition time at the output pins. 80 ps tF Differential High to Low Transition Time 80 ps tPLH Differential Low to High Propagation Delay Measured at 50% differential voltage from input to output. 1 ns tPHL Differential High to Low Propagation Delay 1 ns tSKP Pulse Skew |tPHL–tPLH| 20 ps tSKO Output Skew (Note 7) Difference in propagation delay between channels on the same part (Channel-to-Channel Skew)(Note 7) 100 ps tSKPP Part-to-Part Skew (Note 7) Difference in propagation delay between devices across all channels operating under identical conditions 165 ps tLB Loopback Delay Time Delay from enabling loopback mode to signals appearing at the differential outputs Figure 4 4 ns RJ Device Random Jitter (Note 5) At 0.25 Gbps At 1.5 Gbps At 4.25 Gbps Alternating-10 pattern. De-emphasis disabled. (Figure 6) ps rms ps rms ps rms www.national.com 8 DS42BR400

Physical Dimensions inches (millimeters) unless otherwise noted eLLP-60 Package Order Number DS42BR400TSQ 11 www.national.com DS42BR400

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