DS4266

DS4266 MAXIM | Alldatasheet

Document overview

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Technical content

Features

♦ < 0.7psRMS (typ) from 12kHz to 20MHz Jitter ♦ LVDS or LVPECL Output Types ♦ 3.3V Operating Voltage ♦ 5.0mm x 3.2mm x 1.49mm, 10-Pin LCCC Ceramic Package ♦ -40°C to +85°C Operating Temperature Range ♦ Lead-Free/RoHS Compliant DS4266 VCC OUTP OUTN LVDS OPTION OE GND 0.01μF0.1μF 100Ω DS4266 VCC OUTP OUTN LVPECL OPTION OE GND 0.01μF0.1μF 50Ω 50Ω PECL_BIAS VCC - 2.0V Typical Operating Circuits Pin Configuration and Selector Guide appear at end of data sheet. +Denotes a lead-free/RoHS-compliant package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes.

Ordering Information

PART TEMP RANGE PIN-PACKAGE DS4266D+ -40 °C to +85°C 10 LCCC DS4266P+ -40 °C to +85°C 10 LCCC

ELECTRICAL CHARACTERISTICS

(VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Soldering Temperature Profile J-STD-020 Specification. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Voltage Range V CC (Note 1) 3.135 3.3 3.465 V ICC_D LVDS, output loaded or unloaded 52 75 ICC_PU LVPECL, output unloaded 49 70 Operating Current ICC_PI LVPECL, output load 50 at VCC - 2.0V 74 100 mA Output Frequency f OUT f NOM MHz Oscillator Startup Time t STARTUP (Note 2) 50 ms Frequency Stability fTOTAL Over temperature range, aging, load, supply, and initial tolerance (Note 3) -50 f NOM +50 ppm Frequency Stability Over Temperature with Initial Tolerance fTEMP V CC = 3.3V -35 +35 ppm Initial Tolerance fINITIAL V CC = 3.3V, TA = +25 °C ±20 ppm Frequency Change Due to VCC fVCC V CC = 3.3V ±5% -3 +3 ppm/V Frequency Change Due to Load Variation fLOAD ±10% variation in termination resistance ±1 ppm Aging (15 Years) fAGING -7 +7 ppm Integrated phase RMS; 12kHz to 5MHz, VCC = 3.3V, TA = +25 °C 0.7 Integrated phase RMS; 12kHz to 20MHz, VCC = 3.3V, TA = +25 °C 0.7 Jitter J RMS Integrated phase RMS; 12kHz to 80MHz, VCC = 3.3V, TA = +25 °C 1.0 ps Input-Voltage High (OE) V IH (Note 1) 0.7 x VCC V CC V Input-Voltage Low (OE) V IL (Note 1) 0 0.3 x VCC V Input Leakage (OE) I LEAK GND OE VCC -50 +5.0 μA

ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVDS Output High Voltage V OHLVDSO 100 differential load (Note 1) 1.475 V Output Low Voltage V OLLVDSO 100 differential load (Note 1) 0.925 V Differential Output Voltage |VODLVDSO| 100 differential load 250 425 mV Output Common-Mode Voltage Variation VLVDSOCOM 100 differential load 150 mV Change in Differential Magnitude or Complementary Inputs |VODLVDSO| 100 differential load 25 mV Offset Output Voltage V OFFLVDSO 100 differential load (Note 1) 1.125 1.275 V Differential Output Impedance R OLVDSO 80 140 LVSSLVDSO OUTN or OUTP shorted to ground and measure the current in the shorting path 40 Output Current LLVDSO OUTN or OUTP shorted together 6.5 mA Output Rise Time (Differential) t RLVDSO 20% to 80% 175 ps Output Fall Time (Differential) t FLVDSO 80% to 20% 175 ps Duty Cycle D CYCLE_LVDS 48 52 % Propagation Delay from OE Going Low to Logical 1 at OUTP tPA1 200 ns Propagation Delay from OE Going High to Output Active tP1A 200 ns LVPECL Output High Voltage V OH Output connected to 50 at PECL_BIAS at VCC - 2.0V VCC - 1.085 VCC - 0.88 V Output Low Voltage V OL Output connected to 50 at PECL_BIAS at VCC - 2.0V VCC - 1.825 VCC - 1.62 V Differential Voltage V DIFF_PECL Output connected to 50 at PECL_BIAS at VCC - 2.0V 0.595 0.710 V Rise Time t R-PECL 200 ps Fall Time t F-PECL 200 ps Duty Cycle D CYCLE_PECL 48 52 % Propagation Delay from OE Going Low to Output High Impedance tPAZ 200 ns Propagation Delay from OE Going High to Output Active tPZA 200 ns Note 1: All voltages referenced to ground. Note 2: AC parameters are guaranteed by design and not production tested. Note 3: Frequency stability is calculated as: ΔfTOTAL = ΔfTEMP + ΔfVCC x (3.3 x 5%) + ΔfLOAD + ΔfAGING.

SINGLE-SIDEBAND PHASE NOISE AT f O = fNOM (dBc/Hz)fM = 266MHz 10Hz -65 100Hz -95 1kHz -113 10kHz -113 100kHz -118 1MHz -137 10MHz -149 20MHz -153 PIN NAME FUNCTION 1 OE Active-High Output Enable. Has an internal pullup 100k resistor. 2, 7–10 N.C. No Connection. Must be floated.

3 GND Ground

4 OUTP Positive Output for LVPECL or LVDS

5 OUTN Negative Output for LVPECL or LVDS

6 V CC Supply Voltage

— EP Exposed Paddle. Do not connect this pad or place exposed metal under the pad. Single-Sideband Phase Noise at fO = fNOM Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) FREQUENCY vs. TEMPERATURE DS4266 toc01 TEMPERATURE (°C) fOUT DEVIATION (ppm) 806020 400-20 -18 -15 -13 -10 -20 -40 OPERATING CURRENT vs. OPERATING VOLTAGE DS4266 toc02 VCC (V) ICC (mA) 3.135 +85°C 0°C -40°C +70°C +40°C +25°C

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. Chip Information SUBSTRATE CONNECTED TO GROUND PROCESS: BiPOLAR SiGe THETA-JA (°C/W) Selector Guide +Denotes a lead-free/RoHS-compliant package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead- based and lead-free soldering processes. PART FREQUENCY (NOM) (MHz) FREQUENCY STABILITY (ppm) OUTPUT TYPE TOP MARK DS4266D+ 266 ±50 LVDS 66D DS4266P+ 266 ±50 LVPECL 66P Thermal Information1 TOP VIEW OE N.C. N.C. N.C. N.C. N.C. GND VCC OUTN OUTP DS4266 *EP *EXPOSED PAD Pin Configuration PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

10 LCCC — 56-G5032-002

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.