DS4100H_V01 MAXIM | Alldatasheet
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Technical content
Features
♦ 100MHz Output Frequency ♦ 3.3V ±5% Operating Voltage ♦ HCSL Output ♦ Phase Jitter (RMS): 0.9ps Typical ♦ ±39ppm Frequency Stability Over Voltage, Temperature, 10 Years of Aging ♦ Output-Enable (OE) Control Input ♦ 5mm x 3.2mm x 1.49mm Ceramic Package (LCCC) ♦ Pb Free/RoHS Compliant DS4100H 100MHz HCSL Clock Oscillator TOP VIEW OE RREF N.C. *EP *EXPOSED PAD N.C. N.C. N.C. GND VCC OUTN OUTP DS4100H Pin Configuration
Ordering Information
3.3V VCC GND OE OUTP OUTNRREF DS4100H RS RS 475Ω ±1% RT RT PCI Express LOAD OR CONNECTOR Typical Operating Circuit Rev 1; 4/08 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. +Denotes a lead(Pb)-free package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes. PCI Express is a registered trademark of PCI-SIG Corp. PART TEMP RANGE PIN-PACKAGE TOP MARK DS4100H+ -40 °C to +85°C 10 LCCC 10H
100MHz HCSL Clock Oscillator ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Soldering Temperature Profile IPC/JEDEC J-STD-020 specification. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC (Note 1) 3.135 3.300 3.465 V Supply Current I CC OE = V IH, Figure 2 71 85 mA Input High Voltage (OE) V IH (Note 1) 2.0 V CC V Input Low Voltage (OE) V IL (Note 1) 0 0.8 V Input Leakage Current (OE) IIN GND OE VCC -55 +10 μA HCSL OUTPUTS (OUTP, OUTN) Output High Current I OH 475 resistor connected between RREF and GND, V OUTN Output High Voltage V OH R S = 0, RT = 50 (Notes 1, 2) 612.5 696.0 779.5 mV Output Low Voltage V OL R S = 0, RT = 50 (Notes 1, 2) 0 50 mV Output Leakage High Current I_LEAKH V OE = 0; VOUTN, VOUTP = VCC -10 +10 μA Output Leakage Low Current I_LEAKL V OE = 0; VOUTN, VOUTP = 0 -10 +10 μA Output Resistance R O Measure current out of OUTN pin at V OUTN = 0.5V and 1.0V; 3000 Crossover Voltage V CROSS Measure crossing voltage at OUTP and OUTN (Notes 1, 2, and 3) (50% x VOH) ±5% mV Output Rise Time t R 20% to 80%, CL = 2pF 175 700 ps Output Fall Time t F 80% to 20%, CL = 2pF 175 700 ps Overshoot V OVER Measure overshoot voltage at OUTP and OUTN (Notes 1, 2, and 3) VOH + 0.2V V Undershoot V UNDER Measure undershoot voltage at OUTP and OUTN (Notes 1, 2, and 3) -0.2 V Output-Enable Time to Low Level tPZL Figure 3 (Note 4) 200 ns Output-Enable Time to High Level tPZH Figure 3 (Note 5) 200 ns
100MHz HCSL Clock Oscillator Note 1: All voltages are referenced to ground. Note 2: With 50Ω load to ground on each output pin. Note 3: Guaranteed by design and not production tested. Note 4: tPZL is defined as the time at which VOE = 1.0V on the rising edge of OE to the time at which VOUTP or VOUTN = 0.1VOH on the falling edge of OUTP or OUTN. Note 5: tPZH is defined as the time at which the voltage on the rising edge of OE is equal to 1.0V to the time at which VOUTP or VOUTN = 0.9VOH on the rising edge of VOUTP or VOUTN. Note 6: tPZ is defined as the time at which VOE = 1.0V on the falling edge of OE to the time at which both VOUTP and VOUTN are less than 0.1VOH. Note 7: Frequency stability is calculated as: ΔfTOTAL = ΔfTEMP + ΔfVCC x 0.165 + ΔfLOAD + ΔfAGING. Note 8: Measured with 50mVP-P sinusoidal signal on the supply from 10kHz to 1MHz. Note 9: Including oscillator startup time and PLL acquisition time measured after VCC reaches 3.0V from power-on. ELECTRICAL CHARACTERISTICS (continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Disable Time t PZ Figure 3 (Note 6) 10 ns CLOCK OUTPUT AS MEASURED AT OUTP WITH RESPECT TO OUTN Clock Output fOUT 100 MHz Frequency Stability Total f / fO Over temperature range, aging, load, and supply (Note 7) -39 +39 ppm Initial Frequency Tolerance f_TOL V CC = 3.3V, TA = +25 °C ±15 ppm Frequency Stability vs. Temperature f / fO | TA V CC = 3.3V -30 +30 ppm Frequency Stability vs. VCC f / fO | V V CC = 3.3V ±5% -3 +3 ppm/V Frequency Stability vs. Load f / fO | LOAD ±10% variation in termination resistance ±1 ppm Aging (10 Years) f AGING -7 +7 ppm Phase Jitter (RMS) PJ RMS 12kHz to 20MHz 0.9 ps 10kHz 3.0 100kHz 27 200kHz 15 Accumulated Deterministic Jitter Due to Power-Supply Noise (Note 8) DJPN,P-P 1MHz 7.0 ps Rise and Fall Time Mismatching 20% to 80%; CL = 2pF; Figure 2; 2 x (tR - tF) / (tR + tF) ±20 % Duty Cycle t DC Measure at OUTP and OUTN, Figure 2 45 55 % Oscillation Startup Time (Note 9) 3 ms 100Hz -90.0 1kHz -112 10kHz -115 100kHz -123 1MHz -142 Clock Output SSB Phase Noise 10MHz -147 dBc/ Hz
Figure 1. Functional Diagram
enabled. If connected to logic-low, the output is three-stated. 2 RREF Connect a 475 ±1% resistor from RREF to ground.
3 GND Ground
4 OUTP Positive Clock Output. Requires a series resistor and a pulldown resistor. 5 OUTN Negative Clock Output. Requires a series resistor and a pulldown resister. — EP Exposed Paddle. Do not connect this pad or place exposed metal under the pad. RS = 0Ω FOR TEST, 0 TO 33Ω TO MINIMIZE RINGING IN APPLICATION. CL = SIMULATES RECEIVER INPUT CAPACITANCE FOR TEST ONLY. Figure 2. Typical Termination for HCSL Driver and Test Conditions Figure 3. HCSL Output Timing Diagram When OE is Enabled and Disabled
100MHz HCSL Clock Oscillator Detailed Description The DS4100H is a low-jitter HCSL 100MHz clock oscilla- tor. It combines an AT-cut crystal, an oscillator, and a low-noise PLL in a 5mm by 3.2mm ceramic package. The typical phase jitter is 0.9ps RMS from 12kHz to 20MHz. The device operates from a single +3.3V supply. PLL The PLL generates a 1.6GHz high-speed clock signal based on the 25MHz crystal oscillator output. Clock- divider circuit M generates the output clock by scaling the VCO output frequency. Clock-divider circuit N applies a scaled version of the output clock signal to the phase/frequency detector (PFD) circuit. Output Drivers The DS4100H is available with HCSL output buffers. When not needed, the output buffers can be disabled by driving the OE input to a logic-low. OE has an inter- nal pullup resistor so that, if OE is left open, the outputs are enabled by default. When disabled, the output buffer goes to a high-impedance state. Chip Information TRANSISTOR COUNT: 2850 SUBSTRATE CONNECTED TO GROUND PROCESS: Bipolar SiGe Thermal Information THETA-JA (°C/W) PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
10 LCCC L1053+H2 21-0389
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
100MHz HCSL Clock Oscillator Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 © 2008 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
0 11/07 Initial release. — In the Electrical Characteristics table, added the typical supply current value of 71mA; corrected the units for the clock phase noise parameter from ps to dBc/Hz. 2, 3 1 4/08 In the Pin Description, changed the exposed pad description to indicate that it should not be connected and to avoid placing exposed metal under the pad location.