DS40MB200SQ

DS40MB200_16 TI1 | Alldatasheet

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Technical content

PRE_S LO_0 ± MUX_S0 SIA_0 ± SIB_0 ± LB0A LB0B SOA_0 ± EQ EQ EQ SOB_0 ±LI_0 ± PRE_S PRE_L PRE_S LO_1 ± MUX_S1 SIA_1 ± SIB_1 ± LB1A LB1B SOA_1 ± EQ EQ EQ SOB_1 ±LI_1 ± PRE_S PRE_L Pre-emphasis Control PreL_0 PreS_1 PreS_0 PreL_1 PRE_S PRE_L VCC GND Port 0 Port 1 RSV Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community DS40MB200 SNLS144J – JUNE 2005– REVISED JANUARY 2016 DS40MB200Dual4-Gbps2:1/1:2CMLMUX/BufferWithTransmitPre-Emphasisand ReceiveEqualization

1 Features 3 Description

The DS40MB200 device is a dual signal conditioning 1• 1-Gbps to 4-Gbps Low Jitter Operation 2:1 multiplexer (MUX) and 1:2 fan-out buffer designed• Fixed Input Equalization for use in backplane-redundancy applications. Signal

• Programmable Output Pre-Emphasis conditioning features include continuous time linear equalization (CTLE) and programmable output pre-• Independent Switch and Line Side Pre-Emphasis emphasis, extending data communication in FR4Controls backplanes at rates up to 4 Gbps. Each input stage• Programmable Switch-Side Loopback Mode has a fixed equalizer to reduce intersymbol
• On-Chip Terminations interference distortion from board traces.
• 3.3-V Supply All output drivers have four selectable steps of pre-
• ESD Rating of 6-kV HBM emphasis to compensate for transmission losses from long FR4 backplanes and reduce deterministic jitter.• 48-leadless WQFN Package (7 mm × 7 mm) The pre-emphasis levels can be independently• 0°C to +85°C Operating Temperature Range controlled for the line-side and switch-side drivers. The internal loopback paths from switch-side input to2 Applications switch-side output enable at-speed system testing. All receiver inputs are internally terminated with 100-Ω• Backplane or Cable Driver differential terminating resistors. All drivers are• Redundancy and Signal Conditioning Applications internally terminated with 50 Ω to VCC.• XAUI Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DS40MB200 WQFN (48) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Block Diagram All CML inputs and outputs must be AC coupled for optimal performance. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SNLS144J – JUNE 2005– REVISED JANUARY 2016 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (March 2013) to Revision J Page

• Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Thermal Information table, Parameter Measurement Information section, Feature Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

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13 14 15 16 17 18 2019 21 22 48 47 46 45 44 43 4142 40 39 VCC SOB_0- SOB_0+ GND LI_0+ LI_0- VCC LO_1+ LO_1- GND 36PreL1 WQFN-48 DAP = GND 12PreL0 SIA_1+ LB1A SOA_1+SOA_1- VCC SIB_1+SIB_1- GND SIA_1- MUX_S1 LB1BVCC SOA_0-LB0A SIA_0-SIA_0+GNDSIB_0-SIB_0+VCCLB0B SOA_0+ VCC MUX_S0 VCC LO_0- LO_0+ GND LI_1- LI_1+ VCC SOB_1+ RSV SOB_1- PreS0 PreS1 DS40MB200 www.ti.com SNLS144J – JUNE 2005– REVISED JANUARY 2016

5 Pin Configuration and Functions

I/O(1) DESCRIPTION(2) NAME NO. LINE-SIDE HIGH-SPEED DIFFERENTIAL I/Os LI_0+ 6 Inverting and noninverting differential inputs of port_0 at the line side. LI_0+ and LI_0− have anILI_0− 7 internal 50 Ω connected to an internal reference voltage. See Figure 7. LI_1+ 30 Inverting and noninverting differential inputs of port_1 at the line side. LI_1+ and LI_1− have anILI_1− 31 internal 50 Ω connected to an internal reference voltage. See Figure 7. LO_0+ 33 Inverting and noninverting differential outputs of port_0 at the line side. LO_0+ and LO_0− haveOLO_0− 34 an internal 50 Ω connected to VCC. LO_1+ 9 Inverting and noninverting differential outputs of port_1 at the line side. LO_1+ and LO_1− haveOLO_1− 10 an internal 50 Ω connected to VCC. SWITCH-SIDE HIGH SPEED-DIFFERENTIAL I/Os SIA_0+ 40 Inverting and noninverting differential inputs to the mux_0 at the switch_A side. SIA_0+ andISIA_0− 39 SIA_0− have an internal 50 Ω connected to an internal reference voltage. See Figure 7. SIA_1+ 16 Inverting and noninverting differential inputs to the mux_1 at the switch_A side. SIA_1+ andISIA_1− 15 SIA_1− have an internal 50 Ω connected to an internal reference voltage. See Figure 7. SIB_0+ 43 Inverting and noninverting differential inputs to the mux_0 at the switch_B side. SIB_0+ andISIB_0− 42 SIB_0− have an internal 50 Ω connected to an internal reference voltage. See Figure 7. SIB_1+ 19 Inverting and noninverting differential inputs to the mux_1 at the switch_B side. SIB_1+ andISIB_1− 18 SIB_1− have an internal 50 Ω connected to an internal reference voltage. See Figure 7. SOA_0+ 46 Inverting and noninverting differential outputs of mux_0 at the switch_A side. SOA_0+ andOSOA_0− 45 SOA_0− have an internal 50 Ω connected to VCC. SOA_1+ 22 Inverting and noninverting differential outputs of mux_1 at the switch_A side. SOA_1+ andOSOA_1− 21 SOA_1− have an internal 50 Ω connected to VCC. (1) I = Input, O = Output, P = Power (2) All CML Inputs or Outputs must be AC coupled. Copyright © 2005–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DS40MB200

SNLS144J – JUNE 2005– REVISED JANUARY 2016 www.ti.com Pin Functions (continued) PIN I/O(1) DESCRIPTION(2) NAME NO. SOB_0+ 4 Inverting and noninverting differential outputs of mux_0 at the switch_B side. SOB_0+ andOSOB_0− 3 SOB_0− have an internal 50 Ω connected to VCC. SOB_1+ 28 Inverting and noninverting differential outputs of mux_1 at the switch_B side. SOB_1+ andOSOB_1− 27 SOB_1− have an internal 50 Ω connected to VCC. CONTROL (3.3-V LVCMOS) A logic low at LB0A enables the internal loopback path from SIA_0± to SOA_0±. LB0A isLB0A 47 I internally pulled high. A logic low at LB0B enables the internal loopback path from SIB_0± to SOB_0±. LB0B isLB0B 48 I internally pulled high. A logic low at LB1A enables the internal loopback path from SIA_1± to SOA_1±. LB1A isLB1A 23 I internally pulled high. A logic low at LB1B enables the internal loopback path from SIB_1± to SOB_1±. LB1B isLB1B 24 I internally pulled high. A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high. DefaultMUX_S0 37 I state for mux_0 is switch A. A logic low at MUX_S1 selects mux_1 to switch B. MUX_S1 is internally pulled high. DefaultMUX_S1 13 I state for mux_1 is switch A. PREL_0 and PREL_1 select the output pre-emphasis of the line side drivers (LO_0± andPREL_0 12 I LO_1±). PREL_0 and PREL_1 are internally pulled high. See Table 3 for line side pre-emphasisPREL_1 1 levels. PRES_0 and PRES_1 select the output pre-emphasis of the switch side drivers (SOA_0±,PRES_0 36 I SOB_0±, SOA_1± and SOB_1±). PRES_0 and PRES_1 are internally pulled high. See Table 4PRES_1 25 for switch side pre-emphasis levels. Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GNDRSV 26 I through an external pull-down resistor. POWER Ground reference. Each ground pin must be connected to the ground plane through a low5, 11, 17, 32,GND P inductance path, typically with a via located as close as possible to the landing pad of the GND41 pin. Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the GND DAP P WQFN-48 package. It must be connected to the GND plane with at least 4 via to lower the ground impedance and improve the thermal performance of the package. VCC = 3.3 V ± 5%. 2, 8, 14, 20, Each VCC pin must be connected to the VCC plane through a low inductance path, typically with VCC 29, 35, 38, P a via located as close as possible to the landing pad of the VCC pin. 44 TI recommends to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each VCC pin to ground plane.

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www.ti.com SNLS144J – JUNE 2005– REVISED JANUARY 2016

6 Specifications

6.1 Absolute Maximum Ratings

see(1)(2) MIN MAX UNIT Supply voltage (VCC) −0.3 4 V CMOS/TTL input voltage −0.3 VCC + 0.3 V CML input/output voltage −0.3 VCC + 0.3 V Junction temperature 125 °C Lead temperature (soldering, 4 sec) 260 °C Storage temperature, Tstg −65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.

6.2 ESD Ratings

Human body model (HBM), 1.5 kΩ, 100 pF, per ANSI/ESDA/JEDEC JS-001(1) ±6000ElectrostaticV(ESD) Vdischarge Machine model (MM), per JEDEC specification JESD22-A115-A ±250 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Ratings

Supply voltage (VCC – GND) 3.135 3.3 3.465 V Supply noise amplitude (10 Hz to 2 GHz) 20 mVPP Ambient temperature 0 85 °C Case temperature 100 °C

6.4 Thermal Information

THERMAL METRIC(1) NJU (WQFN) UNIT

48 PINS

RθJA Junction-to-ambient thermal resistance 32.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 15.2 °C/W RθJB Junction-to-board thermal resistance 9 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2005–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DS40MB200

SNLS144J – JUNE 2005– REVISED JANUARY 2016 www.ti.com

6.5 Electrical Characteristics

over recommended operating supply and temperature ranges (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT LVCMOS DC SPECIFICATIONS VIH High level input voltage 2 VCC + 0.3 V VIL Low level input voltage −0.3 0.8 V IIH High level input current VIN = VCC −10 10 µA IIL Low level input current VIN = GND 75 94 124 µA RPU Pull-high resistance 35 kΩ RECEIVER SPECIFICATIONS Common mode voltageVICM Measured at receiver inputs reference to ground. 1.3 Vat receiver inputs Input differentialRITD On-chip differential termination between IN+ or IN−. 84 100 116 Ωtermination DRIVER SPECIFICATIONS RL = 100 Ω ±1% PRES_1 = PRES_0 = 0Output differential PREL_1 = PREL_0 = 0VODB voltage swing without 1000 1200 1400 mVP-PDriver pre-emphasis disabled.pre-emphasis Running K28.7 pattern at 4 Gbps. See Figure 6 for test circuit. RL = 100 Ω ±1% PREx_[1:0] = 00 0 Running K28.7 pattern at PREx_[1:0] = 01 −34 Gbps(2) Output pre-emphasis PREx_[1:0] = 10 −6x = S for switch side pre-voltage ratioVPE emphasis control dB20 × log (VODPE / x = L for line side pre-emphasisVODB) control PREx_[1:0] = 11 −9 See Figure 8 on waveform. See Figure 6 for test circuit. Tested at −9-dB pre-emphasis level, PREx[1:0] = 11 x = S for switch side pre-emphasis controltPE Pre-emphasis width(3) 125 200 250 psx = L for line side pre-emphasis control See Figure 3 on measurement condition. ROTSE Output termination On-chip termination from OUT+ or OUT− to VCC (4) 42 50 58 Ω Output differentialROTD On-chip differential termination between OUT+ and OUT−(4) 100 Ωtermination ΔROTS Mismatch in output Mismatch in output terminations at OUT+ and OUT−(4) 5% E termination resistors Output common modeVOCM 2.7 Vvoltage POWER DISSIPATION VDD = 3.465 V All outputs terminated by 100 Ω ±1%.PD Power dissipation 1 WPREL_[1:0] = 0, PRES_[1:0] = 0 Running PRBS 27–1 pattern at 4 Gbps (1) Typical parameters measured at VCC = 3.3 V, TA = 25°C. They are for reference purposes and are not production-tested. (2) K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000} K28.5 pattern is a 20-bit repeating pattern of +K28.5 and –K28.5 code groups {110000 0101 001111 1010} (3) Specified by design and characterization using statistical analysis. (4) IN+ and IN− are generic names refer to one of the many pairs of complementary inputs of the DS40MB200. OUT+ and OUT− are generic names refer to one of the many pairs of the complimentary outputs of the DS40MB200. Differential input voltage VID is defined as |IN+–IN−|. Differential output voltage VOD is defined as |OUT+–OUT−|.

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www.ti.com SNLS144J – JUNE 2005– REVISED JANUARY 2016 Electrical Characteristics (continued) over recommended operating supply and temperature ranges (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT AC CHARACTERISTICS See Figure 6 for test circuit. At 1.25 Gbps 2Device randomRJ Alternating-1-0 pattern. psrmsjitter(5)(6) At 4 Gbps 2Pre-emphasis disabled. Device deterministic See Figure 6 for test circuit. At 4 Gbps,DJ 30 psp-pjitter(7)(6) Pre-emphasis disabled. PRBS7 pattern DRMA Maximum data rate(6) Tested with alternating-1-0 pattern 4 Gbps X (5) Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt (RJOUT2 – RJIN2), where RJOUT is the random jitter measured at the output of the device in psrms, RJIN is the random jitter of the pattern generator driving the device. (6) Specified by design and characterization using statistical analysis. (7) Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJOUT – DJIN), where DJOUT is the peak-to-peak deterministic jitter measured at the output of the device in psp-p, DJIN is the peak-to- peak deterministic jitter of the pattern generator driving the device.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Differential low-to-high transition Measured with a clock-like pattern at 100 MHz,tR 80 pstime between 20% and 80% of the differential output voltage. Pre-emphasis disabled. Transition time is measured with fixture asDifferential high-to-low transitiontF 80 psshown in Figure 6, adjusted to reflect thetime transition time at the output pins. Differential low-to-high propagationtPLH 0.5 2 nsdelay Measured at 50% differential voltage from input to output.Differential high-to-low propagationtPHL 0.5 2 nsdelay tSKP Pulse skew(2) |tPHL–tPLH| 20 ps Difference in propagation delay among datatSKO Output skew(3)(2) 200 pspaths in the same device. Difference in propagation delay between the tSKPP Part-to-part skew(2) same output from devices operating under 500 ps identical condition. Measured from VIH or VIL of the mux-control or tSM MUX switch time loopback control to 50% of the valid differential 1.8 6 ns output. (1) Typical parameters measured at VCC = 3.3 V, TA = 25°C. They are for reference purposes and are not production-tested. (2) Specified by design and characterization using statistical analysis. (3) tSKO is the magnitude difference in the propagation delays among data paths between switch A and switch B of the same port and similar data paths between port 0 and port 1. An example is the output skew among data paths from SIA_0± to LO_0±, SIB_0± to LO_0±, SIA_1± to LO_1± and SIB_1± to LO_1±. Another example is the output skew among data paths from LI_0± to SOA_0±, LI_0± to SOB_0±, LI_1± to SOA_1± and LI_1± to SOB_1±. tSKO also refers to the delay skew of the loopback paths of the same port and between similar data paths between port 0 and port 1. An example is the output skew among data paths SIA_0± to SOA_0±, SIB_0± to Copyright © 2005–2016, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DS40MB200

Figure 1. Driver Output Transition Time Figure 2. Propagation Delay From Input to Output Figure 3. Test Condition for Output Pre-Emphasis Duration

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6.7 Typical Characteristics

Figure 4. PRBS-7, Pre-Emphasis = 0 dB at 4 Gbps Figure 5. PRBS-7, Pre-Emphasis = –9 dB at 4 Gbps

7 Parameter Measurement Information

Figure 6. AC Test Circuit

LI_0+ 50 50 1.5V LI_0- Input stage +EQ M U X M U X 50501.5V 50501.5V M U X SOA_0+ SOA_0- SOB_0+ SOB_0- SIA_0+ SIA_0- SIB_0+ SIB_0- LO_0+ LO_0- 50 50 50 50 50 50 PreL_0 PreL_1 PreS_0 PreS_1 PRE_L PRE_S LB0A LB0B MUX_S0 DS40MB200 VCC VCC PRE_L PRE_S PRE_S CML driver CML driver Pre-emphasis Control CML driver Input stage +EQ Input stage +EQ LI_1+ 50 50 1.5V LI_1- Input stage +EQ M U X M U X M U X SOA_1+ SOA_1- SOB_1+ SOB_1- SIA_1+ SIA_1- SIB_1+ SIB_1- LO_1+ LO_1- 50 50 50 50 50 50 LB1A LB1B MUX_S1 VCC pins GND pins & DAP PRE_L PRE_S PRE_S CML driver CML driver CML driver Input stage +EQ Input stage +EQ PORT 0 PORT 1 VCC VCC VCC VCC 50501.5V 50501.5V DS40MB200 SNLS144J – JUNE 2005– REVISED JANUARY 2016 www.ti.com

8 Detailed Description

8.1 Overview

The DS40MB200 is a signal conditioning 2:1 multiplexer and 1:2 buffer designed to support port redundancy with encoded or scrambled data rates between 1 and 4 Gbps. The DS40MB200 provides fixed equalization at the receive input and pre-emphasis control on the output in order to support signal reach extension.

8.2 Functional Block Diagram

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8.3 Feature Description

• CML Inputs and EQ
• Multiplexer and Loopback Control
• CML Drivers and Pre-Emphasis Control

8.3.1 CML Inputs and EQ

Figure 7 for details about the internal receiver input termination and bias circuit. Figure 7. Receiver Input Termination and Bias Circuit coupling capacitor placement in an AC test circuit. transmission loss from a short backplane trace (about 10 inches backplane).

8.3.2 Multiplexer and Loopback Control

Table 1 and Table 2 provide details about how to configure the DS40MB200 multiplexer and loopback settings. Table 1. Logic Table for Multiplex Controls 0 MUX_0 select switch_B input, SIB_0±. 1 (default) MUX_0 select switch_A input, SIA_0±. 0 MUX_1 select switch_B input, SIB_1±. 1 (default) MUX_1 select switch_A input, SIA_0±. Table 2. Logic Table for Loopback Controls 0 Enable loopback from SIA_0± to SOA_0±. 1 (default) Normal mode. Loopback disabled.

Table 2. Logic Table for Loopback Controls (continued) 0 Enable loopback from SIB_0± to SOB_0±. 1 (default) Normal mode. Loopback disabled. 0 Enable loopback from SIA_1± to SOA_1±. 1 (default) Normal mode. Loopback disabled. 0 Enable loopback from SIB_1± to SOB_1±. 1 (default) Normal mode. Loopback disabled.

8.3.3 CML Drivers and Pre-Emphasis Control

4Gbps. The pre-emphasis levels of switch-side and line-side can be individually programmed. Figure 8. Driver Pre-Emphasis Differential Waveform (Showing All 4 Pre-Emphasis Steps) Table 3. Line-Side Pre-Emphasis Controls Table 4. Switch-Side Pre-Emphasis Controls

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9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.2 Typical Application

A typical application for the DS40MB200 is shown in Figure 9 and Figure 10. Figure 9. System Diagram (Showing Data Paths of Port 0)

Figure 10. DS40MB200 Connection Block Diagram (Showing Data Paths of Port 0)

9.2.1 Design Requirements

place of the short backplane link. A block diagram of this example is shown in Figure 11.

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Figure 11. Block Diagram of DS40MB200 Application Example connected between the pattern generator and the differential inputs of the DS40MB200 for AC measurements. Table 5. Input Trace Parameters with similar trace width, separation, and dielectric characteristics is placed at the DS40MB200 output. list of critical areas for consideration and study during design.

• Use 100-Ω impedance traces. Generally, these are very loosely coupled to ease routing length differences.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• The maximum body size for AC-coupling capacitors is 0402.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.

9.2.2 Detailed Design Procedure

1. The DS40MB200 must be configured to provide the correct multiplexer and buffer routes in order to satisfy

(SOA_0±) and Switch Card B (SOB_0±).

1. The DS40MB200 is designed to be placed at an offset location with respect to the overall channel

–9 dB of transmit pre-emphasis.

9.2.3 Application Curves

measured locations can be referenced back to the labeled points provided in Figure 11.

• Point (A): Output signal of source pattern generator
• Point (B): Input to DS40MB200 after 25 inches of FR4 trace from source
• Point (C): Output of DS40MB200 driver
• Point (D): Signal after 40 inches of FR4 trace from DS40MB200 driver The source signal is a PRBS-7 pattern at 4 Gbps. For the long output traces, the eye after 40 inches of output FR4 trace is significantly improved by adding –9 dB of pre-emphasis.

Figure 13. Eye Measured at Point (B)Figure 12. Eye Measured at Point (A) Figure 14. Eye Measured at Point (C), Pre-Emph = 0 dB Figure 15. Eye Measured at Point (D), Pre-Emph = 0 dB

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Figure 16. Eye Measured at Point (C), Pre-Emph = –9 dB Figure 17. Eye Measured at Point (D), Pre-Emph = –9 dB

10 Power Supply Recommendations

Figure 10 for further details.

11 Layout

11.1 Layout Guidelines

is provided in AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

11.2 Layout Examples

Figure 18. No Pullback WQFN, Single Row Reference Diagram Table 6. No Pullback WQFN Stencil Aperture Summary for DS40MB200

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Figure 19. 48-Pin WQFN Stencil Example of Via and Opening Placement

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following: AN-1187 Leadless Leadframe Package (LLP), SNOA401

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: DS40MB200

www.ti.com 14-Oct-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS40MB200SQ NRND WQFN NJU 48 250 TBD Call TI Call TI -40 to 85 40MB200 DS40MB200SQ/NOPB ACTIVE WQFN NJU 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 40MB200 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 14-Oct-2015 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS40MB200SQ WQFN NJU 48 250 213.0 191.0 55.0 DS40MB200SQ/NOPB WQFN NJU 48 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2015 Pack Materials-Page 2

www.ti.com SQA48D (Rev A)

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