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Technical content
Features
♦ 50MHz to 122.88MHz Frequency ♦ 3.135V to 3.465V Operation ♦ Low Jitter: < 0.8ps RMS ♦ ±69ppm Absolute Pull Range (APR) ♦ Output Options: LVCMOS Output Buffer LVDS Complementary Output Buffer ♦ Minimum ±110ppm Tuning Range (+25°C) ♦ 14mm x 9mm x 3.06mm Plastic LGA Package DS4077 50MHz to 122.88MHz VCXO N.C. LVCMOS (LVDSO+)VSS 9 8 7 6V DD 5 N.C. (LVDSO-) VC ( ) LVDS OPTION TRANSFER-MOLDED PLASTIC PACKAGE LGA TOP VIEW DS4077 Pin Configuration
Applications
Rev 3; 9/06 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
PART TEMP RANGE OUTPUT TYPE FREQUENCY (fNOM) (MHz) PIN-PACKAGE TOP MARK DS4077L-DCN -40°C to +85°C LVCMOS 54 9 LGA DS4077L-DCN DS4077L-DDN -40°C to +85°C LVDS 54 9 LGA DS4077L-DDN DS4077L-CCN -40°C to +85°C LVCMOS 61.44 9 LGA DS4077L-CCN DS4077L-CDN -40°C to +85°C LVDS 61.44 9 LGA DS4077L-CDN Ordering Information continued at end of data sheet. Clock-Data Recovery in Telecom/Datacom Reference Clock Generation in Base Stations and Wireless Applications Block Diagram VDD LVCMOS OUTPUT VARACTOR OSC CONTROL LVCMOS OPTION SHOWN HERE. CRYSTAL VC DS4077
50MHz to 122.88MHz VCXO ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 3.135V to 3.465V, T A = -40°C to +85°C, unless otherwise noted.) (Typical values at +25°C, V DD = 3.3V, unless otherwise noted.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature Range Thermal Resistance Soldering Temperature (reflow, 2 passes max)....See IPC/JEDEC STD-020 Specification PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VDD Operating Supply Range V DD 3.135 3.3 3.465 V fOUT ≤ 106.25MHz 20 30 VDD Supply Current I DD Output open fOUT > 106.25MHz 25 35 mA Frequency f OUT VC = 1.6V, VDD = 3.3V, TA = +25°C (Note 2) fNOM –8ppm fNOM fNOM +8ppm MHz Frequency vs. VDD Sensitivity V DDppm V DD = 3.3V ±5% -3.5 +11.5 ppm Frequency vs. Load Sensitivity LOADpmm 10pF to 20pF (Note 3) -1 ppm/pF Frequency vs. Temperature TEMPppm From +25°C -20 +20 ppm VC Voltage Range VC RANGE 0.3 1.60 2.8 V Frequency Tuning Sensitivity VC SEN 41 164 ppm/V Tuning Voltage Bandwidth VC BW (Note 3) 10 kHz Absolute Pull Range f TUNE VC = 0.3V to 2.8V (Note 2) -69 +69 ppm VC Input Leakage I LCV VC = 0V to VDD -500 +500 nA Aging, First Year AGEppm -5 +5 ppm Aging, Years 0–10 t AGE Total aging -10 +10 ppm LVDS OUTPUT Output High Voltage V OHLVDSO (Note 4) 1.475 V Output Low Voltage V OLLVDSO (Note 4) 0.925 V Differential Output Voltage V ODLVDSO (Note 4) 250 400 mV Output Common-Mode Variation V LVDSOCOM (Note 4) 150 mV Offset Output Voltage V OFFLVDSO (Note 4) 1.125 1.275 V Differential Output Impedeance R OLVDSO (Note 3) 80 140 Ω Output Current I VSSLVDSO Short ground 40 mA Output Current I LVDSO Short together (Note 3) 12 mA Output Rise Time (Differential) t RLVDSO 20% to 80% (Note 3) 150 ps Output Fall Time (Differential) t FLVDSO 80% to 20% (Note 3) 150 ps
50MHz to 122.88MHz VCXO ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.135V to 3.465V, T A = -40°C to +85°C, unless otherwise noted.) (Typical values at +25°C, V DD = 3.3V, unless otherwise noted.) (Note 1) Note 1: Limits at -40°C are guaranteed by design and not production tested. Note 2: 10pF, LVCMOS. Note 3: Guaranteed by design and not production tested. Note 4: 100Ω differential load. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVCMOS OUTPUT Output Logic 0 V OL Output Current -450µA 0 0.4 V Output Logic 1 V OH Output Current +450µA VDD - 0.8V VDD V Output Rise Time t R Load condition: 10pF to ground; 10% to 90% VDD (Note 3) 2n s Output Fall Time t F Load condition: 10pF to ground; 90% to 10% VDD (Note 3) 2n s Duty Cycle D CYC Load condition: 10pF, VDD / 2 (Note 3) 40 60 % Harmonics H V DD = 3.3V, TA = +25°C (Note 3) -18 -8 dBc/Hz SSB PHASE NOISE AND JITTER, VDD = 3.3, TA = +25°C (Note 3) 10Hz Offset -70 100Hz Offset -100 1kHz Offset -125 10kHz Offset -145 100kHz Offset LVCMOS -150 dBc/Hz Jitter (12kHz to 20MHz) 0.8 ps RMS Pin Description PIN LVCMOS LVDS NAME FUNCTION 1 1 VC VCXO Control Voltage 2, 5, 7, 8, 9 2, 7, 8, 9 N.C. No Connection 3 3 VSS Ground 4 — LVCMOS LVCMOS Output 6 6 VDD DC Power — 4, 5 LVDSO+/LVDSO- LVDS Positive and Negative Outputs
50MHz to 122.88MHz VCXO Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) FREQUENCY vs. TEMPERATURE DS4077 toc01 TEMPERATURE (°C) fOUT DEVIATION (ppm) 6040200-20 -10 -40 80 fOUT = 77.76MHz VC = 1.55V LVCMOS OUTPUT FREQUENCY vs. LOAD CAPACITANCE vs. VC DS4077 toc02 VC (V) fOUT DEVIATION (ppm) -50 -75 -100 125 100 -25 150 -125 0.3 CL = 0pF CL = 20pF fOUT = 77.76MHz OUTPUT FREQUENCY vs. SUPPLY VOLTAGE vs. VC DS4077 toc03 VDD (V) fOUT DEVIATION FROM VDD = 3.3V (ppm) -10 -15 -20 3.135 fOUT = 77.76MHz TA = +25°C VC = 0.3V VC = 2.8V VC = 1.6V
50MHz to 122.88MHz VCXO Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 5 © 2006 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. Ordering Information (continued) PART TEMP RANGE OUTPUT TYPE FREQUENCY (fNOM) (MHz) PIN-PACKAGE TOP MARK DS4077L-ECN -40°C to +85°C LVCMOS 74.17582 9 LGA DS4077L-ECN DS4077L-EDN -40°C to +85°C LVDS 74.17582 9 LGA DS4077L-EDN DS4077L-FCN -40°C to +85°C LVCMOS 74.25 9 LGA DS4077L-FCN DS4077L-FDN -40°C to +85°C LVDS 74.25 9 LGA DS4077L-FDN DS4077L-ACN -40°C to +85°C LVCMOS 76.8 9 LGA DS4077L-ACN DS4077L-ADN -40°C to +85°C LVDS 76.8 9 LGA DS4077L-ADN DS4077L-0CN -40°C to +85°C LVCMOS 77.76 9 LGA DS4077L-0CN DS4077L-0DN -40°C to +85°C LVDS 77.76 9 LGA DS4077L-0DN DS4077L-GCN -40°C to +85°C LVCMOS 106.25 9 LGA DS4077L-GCN DS4077L-GDN -40°C to +85°C LVDS 106.25 9 LGA DS4077L-GDN DS4077L-BDN -40°C to +85°C LVDS 122.88 9 LGA DS4077L-BDN
Revision History
Rev 0; 8/05: Initial release. Rev 1; 12/05: Added LVDS option. Rev 2; 6/06: Changed device description/frequency range; changed jitter typical value from 1 to 0.8psRMS; added new parts numbers to Ordering Information table; changed jitter range upper limits from 80MHz to 20MHz. Rev 3; 9/06: Changed V DDppm units from ppm/PF to ppm; added separate I DD parameter for parts with fOUT greater than 106.25MHz. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
9 LGA L949A-1 21-0265
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.