DS4026 MAXIM | Alldatasheet

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Features

♦ ±1ppm Frequency Accuracy Over -40°C to +85°C ♦ Standard Frequencies: 12.8, 19.44, 20.0, 38.88, 40.0, 51.84MHz ♦ Maximum ±4.6ppm Deviation Over 10 Years ♦ Minimum ±8ppm Digital Frequency Tuning Through I2C Interface ♦ Surface-Mount 16-Pin SO Package ♦ Pb Free/RoHS Compliant DS4026 12.8MHz to 51.84MHz TCXO GNDA VCCD FOUT GNDD SCL SDA GND N.C. N.C. TOP VIEW SO VREF VCC N.C. VOSC GNDOSC N.C. N.C. DS4026 Pin Configuration Rev 0; 2/07 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. +Lead-free package. *The top mark will include a “+” for a lead-free/RoHS-compliant device. Ordering Information continued at end of data sheet.

Ordering Information

PART TEMP RANGE OUTPUT (fNOM) (MHz, CMOS) PIN-PACKAGE TOP MARK* DS4026S+BCC 0°C to +70°C 12.8 16 SO DS4026-BCC DS4026S+BCN -40°C to +85°C 12.8 16 SO DS4026-BCN DS4026S+HCC 0°C to +70°C 19.44 16 SO DS4026-HCC DS4026S+HCN -40°C to +85°C 19.44 16 SO DS4026-HCN DS4026S+JCC 0°C to +70°C 20.0 16 SO DS4026-JCC DS4026S+JCN -40°C to +85°C 20.0 16 SO DS4026-JCN

12.8MHz to 51.84MHz TCXO ABSOLUTE MAXIMUM RATINGS RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on VCC, VCCD, and VOSC Voltage Range on SDA, SCL, and FOUT Operating Temperature Range (noncondensing)....-40°C to +85°C J-STD-020 Specification PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power-Supply Voltage V CC 3.135 3.3 3.465 V Oscillator Power Supply V OSC 3.135 3.3 3.465 V Driver Power Supply V CCD 3.135 3.3 3.465 V DC ELECTRICAL CHARACTERISTICS (Note 1) (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC Active-Supply Current I CC (Note 4) 1.5 2.5 mA FOUT CMOS output on, CL = 10pF, frequency < 25MHz 34 VOSC Oscillator Active-Supply Current IOSC FOUT CMOS output on, CL = 10pF, frequency ≥ 25MHz 59 mA FOUT CMOS output on, CL = 10pF, frequency < 25MHz 23 VCCD Driver Active-Supply Current ICCD FOUT CMOS output on, CL = 10pF, frequency ≥ 25MHz 35 mA SCL Input Leakage I LI -1 +1 µA SDA Leakage I LO Output off -1 +1 µA SCL, SDA High Input Voltage V IH 0.7 x VCC VCC + 0.3 V SCL, SDA Low Input Voltage V IL -0.3 +0.3 x VCC V SDA Logic 0 Output I OL VCC = 3.0V, VOL = 0.4V 3 mA FOUT High Output Voltage V OH VCCD = 3V, IOH = -2mA 2.4 V FOUT Low Output Voltage V OL VCCD = 3V, IOL = 2.0mA 0.4 V FOUT Rise/Fall Time t R/tF (0.1 x VCCD) - (0.9 x VCCD)2 n s FOUT Duty Cycle t D 0.5 x VCCD (Note 5) 45 55 %

12.8MHz to 51.84MHz TCXO AC ELECTRICAL CHARACTERISTICS (Note 1) (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Frequency Stability vs. Temperature f1/TA CL = 10pF to ground fNOM – 1ppm fNOM fNOM + 1ppm ppm Frequency Stability vs. Voltage f1/V CL = 10pF -2 +2 ppm/V Aging, First Year f1/Yr (Note 5) -1 +1 ppm Aging, Years 2–15 f1/Yr (Note 5) -2 +2 ppm Frequency Pull Range f FTUNEH = 3Fh and FTUNEL = FFh; FTUNEH = 40h and FTUNEL = 00h ±8 ±15 ppm Frequency Pull Resolution fRES 1 ppb PHASE NOISE PHASE NOISE (dBc/Hz) (TYPICAL, +25°C, 3.3V) OFFSET (MHz) 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 20.00 CARRIER FREQUENCY

12.8MHz to 51.84MHz TCXO TEMPERATURE SENSOR ELECTRICAL CHARACTERISTICS (Note 1) (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Temperature Sensor Accuracy T -3 +3 °C Temperature Sensor Conversion Time tCONVT 11 ms Temperature Sensor Resolution N2 12 Bits AC ELECTRICAL CHARACTERISTICS (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Standard mode 0 100SCL Clock Frequency f SCL Fast mode 100 400 kHz Standard mode 4.7Bus Free Time Between STOP and START Conditions tBUF Fast mode 1.3 µs Standard mode 4.0Hold Time (Repeated) START Condition (Note 6) tHD:STA Fast mode 0.6 µs Standard mode 4.7Low Period of SCL Clock t LOW Fast mode 1.3 µs Standard mode 4.0High Period of SCL Clock t HIGH Fast mode 0.6 µs Standard mode 0 0.9Data Hold Time (Notes 7, 8) tHD:DAT Fast mode 0 0.9 µs Standard mode 250Data Setup Time (Note 9) t SU:DAT Fast mode 100 ns Standard mode 4.7Start Setup Time t SU:STA Fast mode 0.6 µs Standard mode 20 + 0.1C B 1000Rise Time of Both SDA and SCL Signals (Note 10) tR Fast mode 20 + 0.1C B 300 ns Standard mode 20 + 0.1C B 300Fall Time of Both SDA and SCL Signals (Note 10) tF Fast mode 20 + 0.1C B 300 ns

12.8MHz to 51.84MHz TCXO Note 1: Typical values are at +25°C, nominal supply voltages, unless otherwise indicated. Note 2: Voltages referenced to ground. Note 3: Limits at -40°C are guaranteed by design and not production tested. Note 4: Specified with I2C bus inactive. Note 5: Guaranteed by design and not production tested. Note 6: After this period, the first clock pulse is generated. Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 8: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 9: A fast-mode device can be used in a standard-mode system, but the requirement that tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does not stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 10: CB—total capacitance of one bus line in pF. AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Standard mode 4.7Setup Time for STOP Condition t SU:STO Fast mode 0.6 µs Pin Capacitance SDA, SCL (Note 5) CI/O 10 pF Capacitive Load for Each Bus Line (Note 10) CB 400 pF Pulse Width of Spikes That Must Be Suppressed by the Input Filter tSP Fast mode 30 ns Data Transfer on I2C Serial Bus SDA SCL tHD:STA tLOW tHIGH tR tF tBUF tHD:DAT tSU:DAT REPEATED START tSU:STA tHD:STA tSU:STO tSP STOP START

12.8MHz to 51.84MHz TCXO Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) ACTIVE-SUPPLY CURRENT vs. POWER-SUPPLY CURRENT DS4026 toc01 VCC (V) CURRENT (mA) 0.3 0.2 0.1 0.6 0.5 0.4 0.8 0.7 0.9 1.1 1.0 1.4 1.3 1.2 1.6 1.5 3.0 3.6 12.8 51.84 ACTIVE-SUPPLY CURRENT vs. OSCILLATOR POWER SUPPLY DS4026 toc02 VOSC (V) CURRENT (mA) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 3.0 3.6 51.84 12.8 ACTIVE-SUPPLY CURRENT vs. DRIVER POWER SUPPLY DS4026 toc03 VCCD (V) CURRENT (mA) 8.0 6.0 4.0 2.0 10.0 -0.1 3.0 3.6 51.84 12.8 FREQUENCY vs. FTUNE DS4026 toc04 VC (V) OFFSET (ppm) 000h4000h -25 -20 -15 -10 -30 3FFFh 12.8 51.84 FREQUENCY vs. TEMPERATURE DS4026 toc05 TEMPERATURE (°C) DEVIATION (ppm) 6040200-20 -10 -13 -15 -40 80 DCOMP = 1 DCOMP = 0

1 GNDA Ground for DAC

2V REF Voltage Reference Output. This pin must be decoupled with a 100µF ceramic capacitor to ground. 4V OSC Power Supply for Oscillator Circuit. This pin must be decoupled with a 100nF capacitor to ground.

5 GNDOSC Ground for Oscillator Circuit

6–10 N.C. No Connection. Must be connected to ground.

11 GND Ground for Digital Control, Temperature Sensor, and Controller Substrate

requires an external pullup resistor. movement on the serial interface.

14 GNDD Ground for Oscillator Output Driver

15 FOUT Frequency Output, CMOS Push-Pull

16 V CCD

Figure 1. Typical Operating Circuit

Figure 2. Functional Diagram with a typical resolution of 1ppb (typ) per LSB.

  • Oscillator block with variable capacitor for compen- sation
  • Output driver block
  • Temperature sensor
  • Controller to read the temperature, control lookup table, and adjust the DAC input
  • DAC output to adjust the capacitive load 2C interface to communicate with the chip The oscillator block consists of an amplifier and variable capacitor in a Pierce crystal oscillator with a crystal res- onator of fundamental mode. The oscillator amplifier is a single transistor amplifier and its transconductance is temperature compensated. The variable capacitor is adjusted by the DAC to provide temperature compen- sation. With the FTUNEH and FTUNEL registers, a mini- mum pullability of ±15ppm (typ) is achieved with a typical resolution of 1ppb (typ) per LSB.

DS4026The output driver is a CMOS square-wave output with symmetrical rise and fall time. The temperature sensor provides a 12-bit temperature reading with a resolution of 0.0625°C. The sensor is in continuous conversion mode unless the DCOMP bit in the control register is set to disable temperature updates. The controller coordinates the conversion of tempera- ture into digital codes. When the temperature reading is different from the previous one or the frequency tuning register is changed, the controller looks up the two cor- responding capacitance trim codes from the lookup table at a 0.5°C increment. The trim codes are interpo- lated to 0.0625°C resolution. The result is added with the tuning value from the fre- quency tuning register and loaded into the DAC regis- ters to adjust voltage output. The monotonic DAC provides an analog voltage based on temperature compensation to drive the variable capacitor. The DS4026 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code fol- lowed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. Address Map Disable Compensation Update (DCOMP) DCOMP is bit 7 of the frequency tuning register (see the Frequency Tuning Register (00h–01h), POR = 00h table). When set to logic 1, this bit’s temperature-com- pensation function is disabled. This disabling prevents the variable capacitor in the oscillator block from changing. However, the temperature register still per- forms temperature conversions. The temperature trim code from the last temperature conversion before DCOMP is enabled is used for temperature compensa- tion. The FTUNE registers are still functional when DCOMP is disabled. The frequency tuning registers adjust the base frequen- cy. The frequency tuning value is represented in two’s complement data. Bit 6 of FTUNEH is the sign, bit 5 is the MSB, and bit 0 of FTUNEL is the LSB (see Table 1). When the tuning register low (01h) is programmed with a value, the next temperature update cycle sums the programmed value with the factory compensated value. This allows the user to digitally control the base frequency using the I 2C protocol. These frequency tuning register bits allow the tuning of the base frequency. Each bit typically represents about 1ppb (typ). For FTUNEH = 3Fh and FTUNEL = FFh, the device pushes the base frequency by approx- imately +15ppm. 12.8MHz to 51.84MHz TCXO Frequency Tuning Register (00h–01h), POR = 00h ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00h DCOMP Sign Data Data Data Data Data Data P O R 00000000 01h Data Data Data Data Data Data Data Data P O R 00000000 Temperature Register (02h–03h) ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 02h Sign Data Data Data Data Data Data Data P O R 00000000 03h Data Data Data Data 0 0 0 0 P O R 00000000

write is received and when a word address is received. the internal temperature registers.

  • Data transfer can be initiated only when the bus is not busy. 12.8MHz to 51.84MHz TCXO

Table 1. Register Map

00 DCOMP SIGN FTUNEH Frequency Tuning High

01 FTUNEL Frequency Tuning Low

02 SIGN TREGH Temperature MSB

03 TREGL Temperature LSB

Figure 3. I2C Data Transfer Overview

12.8MHz to 51.84MHz TCXO Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation.

Package Information

For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. The DS4026 can operate in the following two modes: Slave receiver mode (write mode): Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the mas- ter generates a START condition. The slave address byte contains the 7-bit DS4026 address, which is 1000001, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte, the DS4026 outputs an acknowledge on SDA. After the DS4026 acknowledges the slave address and write bit, the master transmits a word address to the DS4026. This sets the register pointer on the DS4026, with the DS4026 acknowledging the transfer. The master can then transmit zero or more bytes of data, with the DS4026 acknowledging each byte received. The register pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. Slave transmitter mode (read mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indi- cates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS4026 while the serial clock is input on SCL. START and STOP condi- tions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates a START condi- tion. The slave address byte contains the 7-bit DS4026 address, which is 1000001, followed by the direction bit (R/W), which is 1 for a read. After receiv- ing and decoding the slave address byte, the DS4026 outputs an acknowledge on SDA. The DS4026 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initia- tion of a read mode, the first address that is read is the last one stored in the register pointer. The DS4026 must receive a not acknowledge to end a read. Chip Information TRANSISTOR COUNT: 77, 712 SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS Ordering Information (continued) PART TEMP RANGE OUTPUT (fNOM) (MHz, CMOS) PIN-PACKAGE TOP MARK* DS4026S+MCC 0°C to +70°C 38.88 16 SO DS4026-MCC DS4026S+MCN -40°C to +85°C 38.88 16 SO DS4026-MCN DS4026S+PCC 0°C to +70°C 40.0 16 SO DS4026-PCC DS4026S+PCN -40°C to +85°C 40.0 16 SO DS4026-MCN DS4026S+QCC 0°C to +70°C 51.84 16 SO DS4026-QCC DS4026S+QCN -40°C to +85°C 51.84 16 SO DS4026-QCN PACKAGE TYPE DOCUMENT NO. 16-pin SO (300 mils) 56-G4009-001 +Lead-free package. *The top mark will include a “+” for a lead-free/RoHS-compliant device.