DS3984 MAXIM | Alldatasheet

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Technical content

Features

♦ High-Density CCFL Controller for LCD TV and PC Monitor Backlights ♦ Can Be Easily Cascaded to Support More Than

4 Lamps

♦ Minimal External Components ♦ Analog Brightness Control ♦ Per-Channel Lamp Control Ensures Equal Brightness Among Lamps and Maximizes Lamp Life ♦ Gate Driver Phasing Minimizes DC Supply Current Surges ♦ Per-Channel Lamp Fault Monitoring for Lamp Open, Lamp Overcurrent, Failure to Strike, and Overvoltage Conditions ♦ Accurate (±5%) Independent On-Board Oscillators for Lamp Frequency (40kHz to 80kHz) and DPWM Burst Dimming Frequency (22.5Hz to 440Hz) ♦ Can Be Synchronized to External Sources for the Lamp and DPWM Frequencies ♦ <10% to 100% Dimming Range ♦ Programmable Soft-Start Minimizes Audible Transformer Noise ♦ I 2C-Compatible Serial Port and On-Board Nonvolatile (NV) Memory Allow Device Customization ♦ 8-Byte NV User Memory for Storage of Serial Numbers and Date Codes ♦ 4.5V to 5.5V Single-Supply Operation ♦ -40°C to +85°C Temperature Range ♦ 32-Lead TQFP (7mm x 7mm) Package or 28-Pin SO (300 mils) Package DS3984 4-Channel Cold-Cathode Fluorescent Lamp Controller LSYNC FAULT SCL SDA OVD4 LCM4 GND GB4 GA4 OVD3 LCM3 GB3 GA3 V CC OVD2 LCM2 GB2 GA2 OVD1 LCM1 GB1 GA1 SVM BRIGHT POSC PSYNC LOSC 28-SO-300 TOP VIEW DS3984 Pin Configurations Rev 1; 5/07 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

Typical Operating Circuit appears at end of data sheet. Pin Configurations continued at end of data sheet. PART TEMP RANGE PIN-PACKAGE DS3984T -40°C to +85°C 32 TQFP DS3984T+ -40°C to +85°C 32 TQFP DS3984Z -40°C to +85°C 28 SO.300 DS3984Z+ -40°C to +85°C 28 SO.300 +Denotes a lead-free package.

Fluorescent Lamp Controller ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +85°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on VCC, SDA, and SCL Voltage on Leads Other than VCC, not to exceed +6.0V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC (Note 1) 4.5 5.5 V Input Logic 1 V IH 0.7 x VCC VCC + 0.3 V Input Logic 0 V IL -0.3 0.3 x VCC V SVM Voltage Range V SVM -0.3 VCC + 0.3 V BRIGHT Voltage Range V BRIGHT -0.3 VCC + 0.3 V LCM Voltage Range V LCM (Note 2) -0.3 VCC + 0.3 V OVD Voltage Range V OVD (Note 2) -0.3 VCC + 0.3 V Gate-Driver Output Charge Loading QG 20 nC

ELECTRICAL CHARACTERISTICS

(VCC = +4.5V to +5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current I CC GA, GB loaded with 600pF, 4 channels active 12 16 mA Input Leakage (Digital Pins) I L -1.0 +1.0 µA Output Leakage (SDA, FAULT)I LO High impedance -1.0 +1.0 µA VOL1 IOL1 = 3mA 0.4Low-Level Output Voltage (SDA, Fault) VOL2 IOL2 = 6mA 0.6 V Low-Level Output Voltage (PSYNC, LSYNC) VOL3 IOL3 = 4mA 0.4 V Low-Level Output Voltage (GA, GB) VOL4 IOL4 = 4mA 0.4 V High-Level Output Voltage (PSYNC, LSYNC) VOH1 IOH1 = -1mA V CC - 0.4 V

Fluorescent Lamp Controller ELECTRICAL CHARACTERISTICS (continued) (VCC = +4.5V to +5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS High-Level Output Voltage (GA, GB) VOH2 IOH2 = -1mA V CC - 0.4 V UVLO Threshold—V CC Rising V UVLOR 4.3 V UVLO Threshold—V CC Falling V UVLOF 3.7 V UVLO Hysteresis V UVLOH 100 mV SVM Threshold V SVMT 1.8 2.0 2.2 V SVM Hysteresis V SVMH 50 mV LCM and OVD Source Current 4µ A LCM and OVD Sink Current 4µ A LCM and OVD DC Bias Voltage V DCB 1.35 V LCM and OVD Input Resistance R DCB 50 k Ω Lamp Off Threshold V LOT (Note 3) 0.3 0.4 0.5 V Lamp Overcurrent Threshold V LOC (Note 3) 1.8 2.0 2.2 V Lamp Regulation Threshold V LRT (Note 3) 0.9 1.0 1.1 V OVD Threshold V OVDT (Note 3) 0.9 1.0 1.1 V Lamp Frequency Range f LF:OSC 40 80 kHz Lamp Frequency Source Frequency Tolerance fLFS:TOL LOSC resistor ±2% over temperature -5 +5 % Lamp Frequency Receiver Duty Cycle fLFR:DUTY 40 60 % DPWM Frequency Range f D:OSC 22.5 440.0 Hz DPWM Source Frequency Tolerance fDSR:TOL POSC resistor ±2% over temperature -5 +5 % DPWM Receiver Duty Cycle f DFE:DUTY 40 60 % DPWM Receiver Frequency Range fDR:OSC 22.5 440.0 Hz DPWM Receiver Minimum Pulse Width tDR:MIN (Note 4) 25 µs BRIGHT Voltage—Minimum Brightness VBMIN 0.5 V BRIGHT Voltage—Maximum Brightness VBMAX 2.0 V Gate-Driver Output Rise/Fall Time t R/tF CL = 600pF 100 ns GAn and GBn Duty Cycle (Note 5) 44 %

Fluorescent Lamp Controller I2C AC ELECTRICAL CHARACTERISTICS (See Figure 9) (VCC = +4.5V to +5.5V, timing referenced to VIL(MAX) and VIH(MIN), TA = -40°C to +85°C.) Note 1: All voltages are referenced to ground, unless otherwise noted. Currents into the IC are positive, out of the IC negative. Note 2: During fault conditions, the AC-coupled feedback values are allowed to be outside the Absolute Max Rating of the LCM or OVD pin for up to 1 second. Note 3: Voltage with respect to VDCB. Note 4: This is the minimum pulse width guaranteed to generate an output burst, which will generate the DS3984’s minimum burst duty cycle. This duty cycle may be greater than the duty cycle of the PSYNC input. Once the duty cycle of the PSYNC input is greater than the DS3984’s minimum duty cycle, the output’s duty cycle will track the PSYNC’s duty cycle. Leaving PSYNC low (0% duty cycle) disables the GAn and GBn outputs in DPWM Slave mode. Note 5: This is the maximum lamp frequency duty cycle that will be generated at any of the GAn or GBn outputs. Note 6: I 2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I 2C stan- dard-mode timing. Note 7: After this period, the first clock pulse can be generated. Note 8: CB—total capacitance allowed on one bus line in picofarads. Note 9: EEPROM write time applies to all the EEPROM memory. EEPROM write begins after a stop condition occurs. Note 10: Guaranteed by design. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency f SCL (Note 6) 0 400 kHz Bus Free Time Between Stop and Start Conditions tBUF 1.3 µs Hold Time (Repeated) Start Condition tHD:STA (Note 7) 0.6 µs Low Period of SCL t LOW 1.3 µs High Period of SCL t HIGH 0.6 µs Data Hold Time t HD:DAT 0 0.9 µs Data Setup Time t SU:DAT 100 ns Start Setup Time t SU:STA 0.6 µs SDA and SCL Rise Time t R (Note 8) 20 + 0.1CB 300 ns SDA and SCL Fall Time t F (Note 8) 20 + 0.1CB 300 ns Stop Setup Time t SU:STO 0.6 µs SDA and SCL Capacitive Loading CB (Note 8) 400 pF EEPROM Write Time t W (Note 9) 20 30 ms NONVOLATILE MEMORY CHARACTERISTICS (VCC = +4.5V to +5.5V) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM Write Cycles +70°C (Note 10) 50,000 Cycles

Fluorescent Lamp Controller Typical Operating Characteristics (VCC = +5.0V, TA = +25°C, unless otherwise noted.) ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3984 toc01 SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 5.35.14.94.7 4.5 5.5 fLF:OSC = 71kHz GATE QC = 3.5nC DPWM = 100% DPWM = 50% DPWM = 10% SVM = 0V ACTIVE SUPPLY CURRENT vs. TEMPERATURE DS3984 toc02 TEMPERATURE (°C) SUPPLY CURRENT (mA) 60-15 35 10 9.5 10.0 10.5 11.0 12.0 11.5 12.5 13.0 13.5 14.0 9.0 -40 85 VCC = 5.5V VCC = 5.0V DPWM = 100% fLF:OSC = 71kHz GATE QC = 3.5nC VCC = 4.5V INTERNAL FREQUENCY CHANGE vs. TEMPERATURE DS3984 toc03 TEMPERATURE (°C) FREQUENCY CHANGE (%) 6035-15 10 -40 85 LAMP FREQUENCY DPWM FREQUENCY TYPICAL OPERATION AT 12V DS3984 toc0410μs 5.0V GA 10μs 5.0V GB 10μs 2.0V LCM 10μs 2.0V OVD TYPICAL OPERATION AT 15V DS3984 toc0510μs 5.0V GA 10μs 5.0V GB 10μs 2.0V LCM 10μs 2.0V OVD TYPICAL OPERATION AT 18V DS3984 toc0610μs 5.0V GA 10μs 5.0V GB 10μs 2.0V LCM 10μs 2.0V OVD TYPICAL STARTUP WITH SVM DS3984 toc07 2ms 2.0V SVM 2ms 5.0V GB 2ms 2.0V LCM 2ms 2.0V OVD BURST DIMMING AT 150Hz AND 10% DS3984 toc081ms 5.0V GA 1ms 5.0V GB 1ms 2.0V LCM 1ms 2.0V OVD

Fluorescent Lamp Controller Typical Operating Characteristics (continued) (VCC = +5.0V, TA = +25°C, unless otherwise noted.) BURST DIMMING AT 150Hz AND 50% DS3984 toc091ms 5.0V GA 1ms 5.0V GB 1ms 2.0V LCM 1ms 2.0V OVD SOFT-START AT VINV = 18V DS3984 toc1050μs 5.0V GA 50μs 5.0V GB 50μs 2.0V LCM 50μs 2.0V OVD LAMP STRIKE—EXPANDED VIEW DS3984 toc111ms 5.0V GA 1ms 5.0V GB 1ms 2.0V LCM 1ms 2.0V OVD LAMP STRIKE WITH OPEN LAMP AUTORETRY ENABLED DS3984 toc1250ms 5.0V GA 50ms 5.0V GB 50ms 2.0V LCM 50ms 2.0V OVD LAMP STRIKE WITH OPEN LAMP AUTORETRY DISABLED DS3984 toc1350ms 5.0V GA 50ms 5.0V GB 50ms 2.0V LCM 50ms 2.0V OVD STAGGERED BURST DIMMING START DS3988 toc14 0.2ms 5.0V GA1 0.2ms 5.0V GA2 0.2ms 5.0V GA3 0.2ms 5.0V GA4 LAMP-OUT (LAMP OPENED) AUTORETRY DISABLED DS3984 toc15 0.5ms 5.0V GA 0.5ms 5.0V GB 0.5ms 2.0V LCM 0.5ms 2.0V OVD LAMP-OUT (LAMP OPENED) AUTORETRY ENABLED DS3984 toc16 50ms 5.0V GA 50ms 5.0V GB 50ms 2.0V LCM 50ms 2.0V OVD

Fluorescent Lamp Controller Pin Description PINS BY CHANNEL (n = 1–4) [TQFP/SO] DESCRIPTIONNAME CH 1 CH 2 CH 3 CH 4 GAn 5/7 10/11 17/17 21/21 MOSFET A Gate Drive. Connect directly to logic-level mode n-channel MOSFET. Leave open if channel is unused. GBn 6/8 11/12 18/18 22/22 MOSFET B Gate Drive. Connect directly to logic-level mode n-channel MOSFET. Leave open if channel is unused. LCMn 7/9 12/13 19/19 23/23 Lamp Current Monitor Input. Lamp current is monitored by measuring a voltage across a resistor placed in series with the low-voltage side of the lamp. Leave open if channel is unused. OVDn 8/10 13/14 20/20 24/24 Overvoltage Detection. Lamp voltage is monitored through a capacitor- divider placed on the high-voltage side of the transformer. Leave open if channel is unused. PINNAME TQFP SO DESCRIPTION GND 1, 9, 14, 16 15 Ground Connection VCC 2, 15 16 Power-Supply Connection BRIGHT 35 Analog Brightness Control Input. Used to control DPWM dimming. Ground when using a PWM signal at PSYNC to control brightness. SVM 4 6 Supply Voltage Monitor Input. Used to monitor the inverter voltage for undervoltage conditions. SDA 25 25 Serial Data Input/Output. I2C bidirectional data pin, which requires a pullup resistor to realize high logic levels. SCL 26 26 Serial Clock Input. I 2C clock input. FAULT 27 27 Fault Output. Active-low, open-drain, requires external pullup resistor to realize high logic levels. LSYNC 28 28 Lamp Frequency Input/Output. This pin is the input for an externally sourced lamp frequency when the DS3984 is configured as a lamp frequency receiver. If the DS3984 is configured as a lamp frequency source (i.e., the lamp frequency is generated internally), the frequency is output on this pin for use by other lamp frequency receiver DS3984s. LOSC 29 1 Lamp Oscillator Resistor Adjust. A resistor to ground on this lead sets the frequency of the lamp. A0 30 2 Address Select Input. Determines the DS3984’s I 2C slave address. PSYNC 31 3 DPWM Input/Output. This pin is the input for an externally generated DPWM signal when the DS3984 is configured as a DPWM receiver. If the DS3984 is configured as a DPWM source (i.e., the DPWM signal is generated internally), the DPWM signal is output on this pin for use by other DPWM receiver DS3984s. POSC 32 4 DPWM Oscillator Resistor Adjust. A resistor to ground on this lead sets the frequency of the DPWM oscillator (dimming clock). This lead can optionally accept a 22.5Hz to 440Hz clock as the source timing for the internal DPWM signal.

Fluorescent Lamp Controller Functional Diagram I2C- COMPATIBLE INTERFACE 8-BYTE USER MEMORY EEPROM SYSTEM ENABLE/POR FOUR INDEPENDENT CCFL CONTROLLERS CHANNEL FAULT CHANNEL ENABLE [40kHz TO 80kHz]4-PHASE GENERATOR x512 PLL MUX RGSO BIT AT CR1.4 RAMP GENERATOR MUX POSCS BIT AT CR1.1 MUX DPSS BIT AT CR1.3 DPWM SIGNAL GND GBn GAn MOSFET GATE DRIVERS OVDn OVERVOLTAGE DETECTION LCMn LAMP CURRENT MONITOR FAULT HANDLING 40kHz TO 80kHz SDAI 2C DEVICE CONFIGURATION PORT LAMP FREQUENCY INPUT/OUTPUT EXTERNAL RESISTOR LAMP FREQUENCY SET DPWM SIGNAL INPUT/OUTPUT ANALOG BRIGHTNESS CONTROL EXTERNAL RESISTOR DPWM FREQUENCY SET/ DPWM CLOCK INPUT SCL FAULT LSYNC LOSC PSYNC BRIGHT POSC [20.48MHz TO 40.96MHz] 22.5Hz TO 440Hz 40kHz TO 80kHz OSCILLATOR (±5%) 22.5Hz TO 440Hz OSCILLATOR (±5%) LFSS BIT AT CR1.2 DPSS BIT AT CR1.3 UVLO VCC [4.5V TO 5.5V] SVM SUPPLY VOLTAGE MONITOR 2.0V CONTROL REGISTERS DS3984

1 OF 4 CHANNELS

256 LAMP CYCLE

Figure 1. Per Channel Logic Diagram and produces near-sinusoidal waveforms. the amount of current flowing through the CCFL. and maximizes the lamp’s brightness and lifetime. fault-monitoring options, and channel enabling/disabling. numbers, or product identification numbers. MixedSignal.Apps@dalsemi.com.

ply. Figure 2 details how the four channels are phased. phased, NOT the DPWM signals. lamp frequency (40kHz to 80kHz) as shown in Figure 6. supplied from an external source (set DPSS = 1 in CR1). Figure 2. Channel Phasing Detail

result from current surges in the transformer primary. ramp by using the Most Recent Value duty-cycle code. twice to make up the 16 soft-start lamp cycles. A 16 LAMP CYCLE PERIOD RESULTS IN A LINEAR RAMP IN LAMP CURRENT. Figure 6. Digital PWM Dimming and Soft-Start

els are adequate for proper operation. former’s input voltage drops below any specified value. monitor cannot be disabled by any means. fault monitoring options are located in CR1 and CR2. Figure 7. Setting the SVM Threshold Voltage

the supply voltage monitor (SVM) input is ≥2V. DS3984 will immediately enter a Fault State. to 15 restrike attempts before entering a Fault State. immediately enter a Fault State. Figure 8. Fault-Handling Flow Chart

The DS3984’s Register Map is shown in Table 1. cycle of the previous burst. F6h CR3 00h Do not modify. If it has been modified, restore to all zeros. *All the configuration settings are saved in nonvolatile (EEPROM) memory. Table 1. Register Map Table 2. MOSFET Duty Cycle (MDC) *The most significant bit of each MDC code is ignored.

DS3984Table 3. Control Register 1 (CR1) BIT NAME FUNCTION

0 LOC

Lamp Overcurrent. 0 = Lamp overcurrent detection disabled. 1 = Lamp overcurrent detection enabled. Note: Gate duty cycle changes during soft-start larger than 5% can cause false LOC fault.

1 POSCS

POSC Select. See POSCR0 and POSCR1 bits in Control Register 2 to select the oscillator range. 0 = Connect POSC to ground with a resistor to set the dimming frequency. 1 = Connect POSC to an external 22.5Hz to 440Hz dimming clock to set the dimming frequency.

2 LFSS

Lamp Frequency Source Select. 0 = Lamp frequency source mode. The lamp frequency is generated internally and sourced at the LSYNC output for use by lamp frequency receivers. 1 = Lamp frequency receiver mode. The lamp frequency must be provided at the LSYNC input.

3 DPSS

DPWM Signal Source Select. 0 = D P W M sour ce m od e. D P WM si g nal i s g ener ated i nter nal l y, and can b e outp ut at P S Y N C p i n ( see RGS O b i t) . 1 = DPWM receiver mode. DPWM signal is generated externally and supplied at the PSYNC input.

4 RGSO

Ramp Generator Source Option. 0 = Sources DPWM at the PSYNC output. 1 = Sources the internal ramp generator at PSYNC output.

5 ARD

Autoretry Disable. 0 = Autoretry function enabled. 1 = Autoretry function disabled.

6 FRS

Fault Response Select. 0 = Disable only the malfunctioning channel. 1 = Disable all channels upon fault detection at any channel.

7 DPD

DPWM Disable. 0 = DPWM function enabled. 1 = DPWM function disabled. DPWM set to 100% duty cycle. 4-Channel Cold-Cathode Fluorescent Lamp Controller

Table 4. Control Register 2 (CR2)

0 UMWP

1 POSCR0

frequency, these bits plus the external resistor control the frequency.

2 POSCR1

Lamp Sample Rate Select. Determines the feedback sample rate of the LCM inputs.

3 LSR0

Lamp Disable. Used to disable channels if all 4 are not required for an application.

5 LD0

7 Reserved Reserved. Should be set to zero.

describe I2C data transfers. clock pulses, start, and stop conditions. master to initiate a new data transfer with a slave. shifted into the device during the rising edge of the SCL. forms a NACK by transmitting a one during the 9th bit. the device is not receiving data. Figure 9. I2C Timing Diagram NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN).

acknowledgement is read using the bit-read definition. the bit write definition to receive additional data bytes. cant seven bits and the R/W bit in the least significant bit. slave. If R/W = 1, the master reads data from the slave. memory location where the slave is to store the data. all byte write operations. See Figure 11 for more detail. the stop condition to write the contents to EEPROM. elapse before attempting to write again to the DS3984. are performed at room temperature. Figure 10. DS3984’s Slave Address Byte

addresses based on the state of the address input (A0). CC and GND pins to minimize trace inductance. 28% to 35% duty cycle during steady state operation. open-circuit voltage that will be used to strike the lamp. for a 12V inverter supply, 438mm x 2.2mm lamp design. channel MOSFETs now available in SO-8 packages. and capacitors used in the typical operating circuit. Figure 11. I2C Communications Examples 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.

Table 5. Transformer Specifications Table 6. Resistor and Capacitor Selection Guide 105kΩ 1 — See the Setting the SVM Threshold Voltage section. Configuration section to determine value. Configuration section to determine value. R8 1/Ch 140 Ω 1 — See the Setting the RMS Lamp Current section. for V D C B to r each i ts nor m al op er ati ng l evel . C2 1/Ch 10pF 5 ±1000ppm/°C 2kV to 4kV breakdown voltage required. for V D C B to r each i ts nor m al op er ati ng l evel . C5 2/DS3984 0.1µF 10 X7R Place close to V CC and GND on DS3984. Note 11: Primary should be Bifilar wound with center tap connection. Note 12: Turns ratio is defined as secondary winding divided by the sum of both primary windings. Note 13: 40:1 is the nominal turns ratio for driving a 438mm x 2.2mm lamp with a 12V supply. Refer to AN3375 for more information.

Note 14: Only one channel shown to simplify drawing. Note 15: See the Component Selection section for recommended external components. Figure 12. Typical Operating Circuit

Fluorescent Lamp Controller Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. DS3984

Package Information

For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Chip Information TRANSISTOR COUNT: 70,200 SUBSTRATE CONNECTED TO: Ground POSC PSYNC LOSC LSYNC FAULT SCL

25 SDA

TQFP 7 x 7 x 1.0mm 1GND 24 OVD4 TOP VIEW DS3984 Pin Configurations (continued)