DS3923 MAXIM | Alldatasheet

Document overview

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Technical content

Features

  • Supports -32dBm to -5dBm Optical Input Range with ±0.5dB Accuracy
  • 15V to 76V APD Bias
  • Pin Discharge Option
  • Sampling Period as Short as 300ns
  • External Capacitor Connection for Controlled RC Time Constant of APD Voltage Filter
  • Current Clamp with Adjustable Limit and External Shutdown with Limit Status
  • 3.5mm x 3.5mm, 24-Pin TQFN Package with Exposed Pad
  • Two Current Mirror Outputs and Additional Small- Signal Current Mirror Output for ADC Measurement
  • High-Voltage Switch FET for DC-DC Boost Converter Ordering Information appears at end of data sheet. For related parts and recommended products to use with this part, refer to www.maximintegrated.com/DS3923.related. 19-6848; Rev 1; 8/14 0.1I10.2I10.8I1I1 MIRIN 100Ω 0.1µF 0.1µF 330kΩ 4.99kΩ CLD 1.8V MIRIN MIROUT 330pF TO 500pF APDPAPD 250µw 1µw 3.3V 300ns min 250µw 0V APDV VIP1 VIP2 1kΩ OPT. C4 1kΩ OPT. CURRENT LIMIT TEMP LIMIT DUAL GAIN SAMPLE/ HOLD DISCHARGE RLIM IOUT DIFFEN VOP VON VIN ILIMS GAIN SENXOR ISRC/ SHDN 30kΩ ISRC 4.7µH HVG PWM GPIO[2:0] GPIO (BY DEFAULT Hi-Z) [APD SHUTDOWN] >300ns PULSE OCCURS ONCE PER 100µS TO ONCE PER 100ms HVD DS3923 DS4830 VCC GND SEN 3.3V 3.3V AVCC3.3V 3.3V 10kΩ GPIO (EDGE INTERRUPT) [DETECT SEN EDGE] ADC [BM RSSI MONITOR, AVERAGE RSSI, MIRROR VOLTAGE DROP DC-DC FEEDBACK] 200µA TIA ADJUSTED FROM 55V AT -40°C TO 65V AT 95°C Typical Application Circuit DS3923 High-Speed Current Mirror with Sample/Hold Output EVALUATION KIT AVAILABLE

Voltage on HVD, MIRIN, MIRCAP, and MIROUT Voltage on All Other Pins Relative Continuous Power Dissipation (TA = +70°C)

Electrical Characteristics

(VMIRIN = 15V to 76V, VCC = 2.85V to 3.63V, TA = -40°C to +95°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Low Voltage Supply VCC 2.85 3.63 V Low Voltage Current ICC (Note 2) 8 16 mA MIRIN Quiescent Current IMIRIN VMIRIN = 60V, ISRC/SHDN = 30kΩ to GND IMIROUT = 0µA 1 2 mA IMIROUT = 1mA 3.2 4 MIRIN Voltage VMIRIN 15 76 V HV FET On-Resistance RDSONHV VGS = 3.0V, ID = 170mA 0.85 2 Ω HVG Voltage VGSHV 0 VCC + 0.3 V HVD Voltage VDHV 76 V HVD Leakage IILHV -1 +1 µA Logic-Input Thresholds (DIFFEN, DISCHARGE, GAIN, HVG, SEN, SENXOR) VIL 0.3 x VCC V VIH 0.7 x VCC ISRC/SHDN Threshold VIL_SHDN 1.4 V VIH_SHDN VCC - 0.2 ISRC/SHDN Resistor RISRC (Note 3 29.7 30 30.3 kΩ Maximum MIROUT Current ICLAMP ISRC/SHDN = low RLIM = 40.2kΩ 1.4 2 2.8 mARLIM = 24.9kΩ 2.5 3.2 4.1 ISRC/SHDN = high 0.01 MIROUT Capacitive Load CMIROUT Total capacitance on MIROUT to achieve accuracy specification 330 500 pF Logic Output Levels (ILIMS) VOL_ILIMS IILIMS = -2mA 0.45 V VOH_ILIMS IILIMS = +2mA VCC -0.45 DS3923 High-Speed Current Mirror with Sample/Hold Output www.maximintegrated.com Maxim Integrated │ 2 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Electrical Characteristics (continued) (VMIRIN = 15V to 76V, VCC = 2.85V to 3.63V, TA = -40°C to +95°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Logic Output Levels (GAIN Has 3.5kΩ Internal Nominal Impedance) VOL IGAIN = -30µA 0.4 V VOH IGAIN = +30µA VCC - 0.4 ILIMS Output Time tILIMS (Note 4) 1 µs IOUT to MIROUT Ratio KIOUT IMIROUT = 1mA 0.090 0.100 0.110 A/A VIP1 to MIROUT Ratio KVIP1 IMIROUT = 1mA 0.720 0.800 0.880 A/A VIP2 to MIROUT Ratio KVIP2 IMIROUT = 1mA 0.180 0.200 0.220 A/A KVIP1, KVIP2, and KIOUT Voltage Variation K VAR VMIRIN = 40V ± 10% ±0.3 ±2.5 % Mirror Voltage Drop Monitor Load Capacitance VAPDV:CAP External capacitance required on APDV 50 250 pF Mirror Voltage Drop VMIRIN - VMIROUT Current limit not exceeded, VSHDN = Hi-Z, IMIRIN = 1mA 4 V Shutdown Temperature TSHDN 150 °C Shutdown Temperature Hysteresis THYS 20 °C VIP1 Offset Current IVIP1OFF RISRC = 30kΩ 20 40 µA VIP2 Offset Current IVIP2OFF RISRC = 30kΩ 19 30 µA IOUT Offset Current IOUTOFF RISRC = 30kΩ 18 25 µA DS3923 High-Speed Current Mirror with Sample/Hold Output www.maximintegrated.com Maxim Integrated │ 3

Sample and Hold Parameters (VMIRIN = 15V to 76V, VCC = 2.85V to 3.63V, TA = -40°C to +95°C, RISRC = 30kΩ, DISCHARGE = high, unless otherwise noted.) (Note 1) Note 1: Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage rating are guaranteed by design and characterization. Note 2: ISRC/SHDN is not connected; HV FET is driven by a 100Ω source at 250kHz with a 2.97V square wave; HVD is connected to GND. Note 3: External resistor connected to GND. This value guarantees accuracy of DS3923. I ISRC = (6/RISRC) ±6%. Note 4: Resistor connected to RLIM for 1mA clamp limit. I MIROUT step from 10μA to 10mA. Time measured from I MIROUT step to IMIROUT < 1.1mA (see the Typical Application Circuit). C3 = 47pF, C1 = C2 = 0.1μF, VVC1 = 30V; R1 = 100Ω. Note 5: Output Error = VOP – 4 x (VIP1 or VIP2) and sampled at t OUT. Measured at +25°C with offset removed. Note 6: To change internal gain selection, external driver must be capable of meeting the GAIN input logic level with the GAIN impedance connected to either VCC or GND. Note 7: See Figure 1 for more detail on timing. Note 8: Time referenced to SENINT falling edge when output is valid at VOP - VON if DIFFEN = High or VOP if DIFFEN = Low. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Error (Total Error from All Sources) VERR IMIROUT from 600µA to 60uA (Note 5) ±5.5 IMIROUT from 20µA to 500µA (Note 5) -9.0 +9.0 Output Voltage VOUT VOUT = VVOP - VVON, 100kΩ output load 0 2.5 V Output Voltage Common Mode VOUTCM VDIFFEN = High 1.4 V Output Impedance ROUT 1 kΩ VOP Output Capacitive Load CLD Capacitance for stable operation 50 pF Gain Selection Threshold VGTHR 320 400 460 mV GAIN Impedance RG (Note 6) 2.1 3.5 4.9 kΩ Sample Time tS 1kΩ resistors connected to VIP1 and VIP2 (Note 7) 300 ns Delay Time tDEL (Note 7) 10 ns Output Valid Time tO_VAL Less than 1% change from the time the output is valid, CLD = 50pF (Notes 7 and 8) 9 109 µs DS3923 High-Speed Current Mirror with Sample/Hold Output www.maximintegrated.com Maxim Integrated │ 4

Figure 1. DS3923 Sample/Hold Timing Diagram

0.1I1 CS CS DIFFEN AVCC VOP VON DISCHARGE SEN GAIN SENXOR SENINT VCC HVG HVGND AVCC VCC 0.2I10.8I1 CURRENT LIMIT TEMP LIMIT DISCHARGE DS3923 SAMPLE 0.4 RG D Q RMIRCAP 1.8V ISRC/ SHDN RLIM ILIMS MIRCAP MIRIN MIROUT HVD APDV AVCC 0.5V/V MIROUT MIRIN GND DS3923 High-Speed Current Mirror with Sample/Hold Output www.maximintegrated.com Maxim Integrated │ 6

(TA = +25°C, unless otherwise noted.) 6.2 6.4 6.6 6.8 7.2 7.4 -40 -15 10 35 60 85 110 ICC (mA) TEMPERATURE (°C) ICC vs. TEMPERATURE toc01 VCC = 3.3V IMIROUT = 0.4mA IMIROUT = 1.0mA -30 -25 -20 -15 -10 50 500 5,000 50,000 NOISE ATTENUATION (dB) NOISE FREQUENCY (Hz) CURRENT MIRROR FILTER FREQUENCY RESPONSE 0.01µF MIRCAP CAPACITOR toc05 0.1µF MIRCAP CAPACITOR 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 -40 -15 10 35 60 85 110 VVOP (V) TEMPERATURE (°C) VVOP vs. TEMPERATURE toc02 VCC = 3.3V IMIROUT = 0.4mA IMIROUT = 1.0mA IMIROUT = 2.0mA 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.01 0.10 1.00 10.00 CURRENT MIRROR RATIOS MIROUT CURRENT (mA) CURRENT MIRROR RATIO vs. MIROUT CURRENT toc06 KVIP1 KIOUT KVIP2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VVOP (V) VCC (V) VVOP vs. VCC toc03 DIFFEN = LOW IMIROUT = 0.4mA IMIROUT = 1.0mA IMIROUT = 2.0mA SINGLE-ENDED OUTPUT, TRANSIENT WITH 10% VCC STEP 50mV/div 2.0V/div 500mV/div toc04 2.0ms/div VOUTN VINSIDE VBACKUP VSEN VCC = 3.0V VCC = 3.3V VVOP Maxim Integrated │ 7 www.maximintegrated.com DS3923 High-Speed Current Mirror with Sample/Hold Output Typical Operating Characteristics

1 VCC Digital 3.3V (Nominal) Supply 2 AVCC Analog 3.3V (Nominal) Supply

3 DIFFEN

Sample/Hold Single-Mode/Differential Mode Selection. When logic input is: Low: Single-mode sample/hold output High: Differential mode sample/hold output. 4 VIP2 20% Current Mirror Output. Connect to resistor to ground. 5 VIP1 80% Current Mirror Output. Connect to resistor to ground. 6 VIN Negative Voltage Input. Connect to the same ground point as resistors connected to VIP1 and VIP2. 7 IOUT 10% Current Mirror Output. If unused, do not connect.

8 SENXOR

Sample Enable XOR. The start and stop of the sampling depend on the logic input of SENXOR and SEN. When SENXOR is low, the rising edge of the SEN pulse activates sampling, and the falling edge of the SEN pulse deactivates sampling. When SENXOR is high, the falling edge of the SEN pulse activates sampling, and the rising edge of the SEN pulse deactivates sampling. Note: If SENXOR is high, the discharge function should not be used. See Figure 3 for more detail. 9 SEN Sample Enable Pulse. Logic input. See the description of SENXOR and Figure 3 for more detail. AVCC VIP2 VIP1 VIN VCC RLIM ILIMS ISRC/SHDN DISCHARGE GAIN 1 2 MIRIN 4 5 6 1718 16 14 13 HVGND HVD GND SEN SENXOR IOUT EP DS3923 DIFFEN APDV MIRCAP 20 11 VONHVG 19 12 VOPMIROUT 24-LEAD TQFN (3.5mm x 3.5mm x 0.8mm) DS3923 High-Speed Current Mirror with Sample/Hold Output www.maximintegrated.com Maxim Integrated │ 8 Pin Configuration Pin Description

10 GND Ground

11 VON Negative Sample/Hold Voltage Output. Do not connect for single-ended mode. 12 VOP Sample/Hold Voltage Output. Positive output in differential mode. Also used for single-ended output.

13 GAIN

Hold Amplifier Gain Indicator. Both as output and logic input. Indicates which current mirror’s output is active. 3.5kΩ input/output impedance. Pin as input (mirror selection for sample/hold): Low: Sample/hold Conversion from Current Mirror 1 (VIP1); High: Sample/hold Conversion from Current Mirror 2 (VIP2). Pin as output (mirror indication for sample/hold): Low: Sample/hold Conversion from Current Mirror 1 (VIP1); High: Sample/hold Conversion from Current Mirror 2 (VIP2).

14 ISRC/

Dual-Purpose Pin. ISRC: A resistor connected to this pin controls the amount of current flowing through a current source connected to MIROUT. (Note: During this mode of operation, the microcontroller pin (if connected) should be in the high impedance.) SHDN: If pulled high, sets MIROUT to high-impedance. 15 ILIMS Current-Limit Status. Active-low signal indicating that the current-limit threshold is exceeded. 16 APDV APD Voltage Monitor. Provides output voltage used to calculate the voltage on the APD. 17 RLIM Resistor Limit. Connect a resistor between RLIM and GND to set the current clamp limit.

18 DIS-

Discharge Enable. When sampling is deactivated and the DISCHARGE pin logic input is low, the discharge function is disabled. When sampling is deactivated and the DISCHARGE pin logic input is high, the discharge function is enabled, and the DS3923 pulls current mirror outputs VIP1 and VIP2 low to ensure accurate sam- pling. During the sample time, the pin discaharge is internally disabled by the DS3923. See Figure 4 and Figure 5 for more detail. Note: The discharge function should not be used if SENXOR is a logic-high. 19 MIROUT Current Mirror Output. Connect to APD. 20 HVG High-Voltage NMOS FET Gate. Connect to ground if unused. 21 MIRCAP Mirror Filter. Connect external capacitor to filter voltage at MIROUT. 22 MIRIN Current Mirror Input. Connect to high voltage supply. 23 HVGND High-Voltage NMOS FET Source. Connect to ground of the DC-DC boost circuit. 24 HVD High-Voltage NMOS FET Drain. Connect to HVGND if unused. — EP Exposed Pad. Connect to ground with a minimum of 9 vias for thermal conductivity improvement. It is acceptable to use solder mask between the IC and the ground pad. It is not necessary to electrically connect the exposed pad ground. DS3923 High-Speed Current Mirror with Sample/Hold Output www.maximintegrated.com Maxim Integrated │ 9 Pin Description (continued)

the feedback resistors for the APD bias boost converter. using the ISRC/SHDN pin, effectively disabling the APD. The ISRC/SHDN pin is active-high. capacitors is then amplified by the hold amplifier. Figure 3. SEN Pulse and Sample/Hold Output Timing Diagram

allows VIP1 or VIP2 forced selection using the GAIN pin. The sample/hold amplifier output is shown in Table 1. by setting the DISCHARGE pin to high. choice. The choice made is indicated on the GAIN pin. Table 1. Sample/Hold Output Voltage

3.2 I1 R 4

0.8 I1 R5

Figure 4. Discharge Logic Diagram

The logical circuit is shown in Figure 6. window is larger than the DS3923’s recovery time. the relative offset errors to become more significant. Table 2. Sample/Hold Input Selection Figure 5. Discharge, Current Mirror, and SEN Pulse Timing Diagram

Proper PCB layout helps to reduce switching noise in the system. HVGND is the connection of the switching FET and thus carries high current pulses. HVGND should also be connected to the boost converter’s input capacitor and output bulk capacitor. Ensure that the HVGND trace is low impedance and able to carry the high current from the FET. To keep the switching noise on HVGND isolated from GND, a star ground configuration should be used. HVGND and GND should only be connected together at one point on the PCB. This point can be either the ground side of the output bulk capacitor or the common ground point of the PCB. Keeping all PCB traces as short as possible reduces radiated noise, stray capacitance, and trace resistance.

Package Information

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

24 TQFN-EP T243A3+1 21-0188 90-0122

Ordering Information

PART TEMP TANGE PIN-PACKAGE DS3923T+ -40°C to +95°C 24-TQFN-EP** DS3923T+T* -40°C to +95°C 24-TQFN-EP** +Denotes a lead(Pb)-free/RoHS-compliant package. *First T denotes package type. Second T denotes Tape and reel. **EP = Exposed pad. Figure 6. GAIN Selection Logic Diagram

Revision History

0 12/13 Initial release — 1 8/14 Notes added to Pin Description and Discharge section stating SENXOR should not be a logic-high if the discharge feature is being used. 8, 9, 12 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2014 Maxim Integrated Products, Inc. │ 15 DS3923 High-Speed Current Mirror with Sample/Hold Output For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.