DS3911T+

DS3911 MAXIM | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 24

Technical content

Features

S Four10-BitDelta-SigmaOutputs S On-ChipTemperatureSensorandADC S FourTemperature-IndexedLUTs,Upto2NC Resolution S I2C-CompatibleSerialInterface S AddressPinsAllowUptoFourDS3911stoShare theSameI2CBus S 2.8Vto5.5VDigitalSupply S -40NCto+100NCOperatingTemperatureRange S 3mmx5mm,14-PinTDFNPackage Typical Operating Circuit 19-5933; Rev 0; 6/11 Ordering Information appears at end of data sheet. For related parts and recommended products to use with this part, refer to www.maxim-ic.com/DS3911.related. DS3911 I2C SLAVE TEMP SENSOR SDA VCC GND 3.3V RPU SCLI2C MASTER VCC 3.3V 0.1µF VREF GND VREF 3.3V 0.1µF 100Ω 2.5V 10-BIT DAC EEPROM LUT DAC0 MODSET LASER DRIVERAPCSETC1 C2 10-BIT DAC EEPROM LUT DAC1 MODSET LASER DRIVERAPCSET 10-BIT DAC EEPROM LUT DAC2 MODSET LASER DRIVERAPCSET 10-BIT DAC EEPROM LUT DAC3 MODSET LASER DRIVERAPCSET Forpricing,delivery,andorderinginformation,pleasecontactMaximDirectat1-888-629-4642, orvisitMaxim’swebsiteatwww.maxim-ic.com.

Maxim Integrated Products 2 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Voltage Range on SDA, SCL, and V CC Voltage Range on DAC0, DAC1, DAC2, DAC3, Continuous Power Dissipation (TA = +70NC) ABSOLUTEMAXIMUMRATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDEDOPERATINGCONDITIONS (TA = -40NC to +100NC, unless otherwise noted.) DCELECTRICALCHARACTERISTICS (VCC = +2.8V to +5.5V, T A = -40NC to +100NC, unless otherwise noted.) DACELECTRICALCHARACTERISTICS (VCC = +2.8V to +5.5V, T A = -40NC to +100NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC (Note 1) 2.8 5.5 V Input Logic 1 (SCL, SDA, A0, A1) VIH 0.7 x VCC VCC + 0.3 V Input Logic 0 (SCL, SDA, A0, A1) VIL -0.3 +0.3 x VCC V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage (SDA, SCL, A0, A1) IL -1 +1 FA VCC Supply Current ICC (Note 2) 0.9 2.0 mA Low-Level Output Voltage (SDA) VOL 3mA sink current 0 0.4 V I/O Capacitance CI/O 5 10 pF Power-On Recall Voltage VPOR (Note 3) 1.6 2.7 V Power-Up Recall Delay tD (Note 4) 5 ms PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Delta-Sigma Clock Frequency fDS 2.1 MHz Reference Voltage Input (VREF) VREF Minimum 0.1FF to GND 2.4 VCC V Output Range 0 VREF V Output Resolution See the Delta-Sigma DAC Output and Control section for details 10 Bits Output Impedance RDS 35 100 I

Maxim Integrated Products 3 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC TEMPERATURESENSORCHARACTERISTICS (VCC = +2.8V to +5.5V, T A = -40NC to +100NC, unless otherwise noted.) ANALOGVOLTAGEMONITORINGCHARACTERISTICS (VCC = +2.8V to +5.5V, T A = -40NC to +100NC, unless otherwise noted.) I2CACELECTRICALCHARACTERISTICS (VCC = +2.8V to +5.5V, T A = -40NC to +100NC, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted.) (See Figure 1.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Temperature Error TA = -40NC to +100NC Q5 NC Update Rate (Temperature and Supply Conversion Time) tFRAME 16 ms PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Resolution LSB Full-scale voltage of 6.5536V 800 FV Input/Supply Accuracy ACC At factory setting 0.25 1 %FS Input Supply Offset VOS (Note 5) 0 5 LSB Update Rate (Temperature and Supply Conversion Time) tFRAME 16 ms PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency fSCL (Note 6) 0 400 kHz Bus Free Time Between STOP and START Conditions tBUF 1.3 Fs Hold Time (Repeated) START Condition tHD:STA 0.6 Fs Low Period of SCL tLOW 1.3 Fs High Period of SCL tHIGH 0.6 Fs Data Hold Time tHD:DAT 0 0.9 Fs Data Setup Time tSU:DAT 100 ns START Set-Up Time tSU:STA 0.6 Fs SDA and SCL Rise Time tR (Note 7) 20 + 0.1CB 300 ns SDA and SCL Fall Time tF (Note 7) 20 + 0.1CB 300 ns STOP Set-Up Time tSU:STO 0.6 Fs SDA and SCL Capacitive Loading CB (Note 7) 400 pF EEPROM Write Time tW (Note 8) 10 20 ms A0, A1 Setup Time tSU:A Before START 0.6 Fs A0, A1 Hold Time tHD:A After STOP 0.6 Fs Input Capacitance on A0, A1, SDA, or SCL CI 5 10 pF Startup time tST 2 ms

device are specified as negative. Note2: ICC is specified with SCL = SDA = V CC, and EN bit = 1. Typical values are at VCC = 3.3V and TA = +25NC. Note3: This is the minimum VCC voltage that causes NV memory to be recalled. Note4: This is the time from V CC > VPOR until initial memory recall is complete. Note5: Guaranteed by design. Note7: CB = total capacitance of one bus line in pF. Note8: EEPROM write time begins after a STOP condition occurs. Note9: Guaranteed by characterization. Figure 1. I2C Timing Diagram NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).

Maxim Integrated Products 5 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) VREF CURRENT vs. DAC1 CODE SWEEP (CURRENT SINK FILTER) DS3911 toc08 DAC1 VALUE VREF (mA) 1000800600400200 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VREF CURRENT vs. DAC0 CODE SWEEP (VOLTAGE OUTPUT FILTER) DS3911 toc07 DAC0 VALUE VREF (mA) 1000800600400200 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 DAC1 DEVIATION FROM AVERAGE CURRENT vs. DAC3 CODE SWEEP (BOTH CURRENT SINK FILTERS) DS3911 toc06 DAC3 VALUE 1.25V SOURCE CURRENT (nA) 1000800600400200 -400 -200 200 400 600 -600 DAC1 VALUE = 0000h DAC0 VALUE = 8000h DAC1 VALUE = FFC0h FILTERED DAC0 VOLTAGE VARIATION FROM IDEAL vs. DAC2 CODE SWEEP (BOTH VOLTAGE OUTPUT FILTERS) DS3911 toc05 DAC2 VALUE VOLTAGE VARIATION FROM IDEAL (µV) 1000800600400200 -1000 -800 -600 -400 -200 200 400 600 800 1000 1200 -1200 DAC0 VALUE = 0000h DAC0 VALUE = FFC0h DAC0 VALUE = 8000h INL vs. OUTPUT CODE (CURRENT SINK FILTER) DS3911 toc04 DAC VALUE LSB 1000800600400200 -12 -10 -14 INL vs. OUTPUT CODE (VOLTAGE OUTPUT FILTER) DS3911 toc03 DAC VALUE LSB 1000800 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 -0.5 0 600400200 SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3911 toc02 VDD (V) IDD (mA) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.7 TA = +25°C SUPPLY CURRENT vs. TEMPERATURE DS3911 toc01 TEMPERATURE (°C) IDD (mA) 10080-20 0 20 40 60 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 0.5 -40 120 V DD = 3.3V

Maxim Integrated Products 6 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Multiple Device Connection Diagram DS3911 I2C SLAVE TEMP SENSOR SDA VREF SCLI2C MASTER I2C ADDRESS 3.3V 3.3V 0.1µF 0.1µF 63Ω VCC VCC 10-BIT DAC EEPROMMODSET LASER DRIVERBIASSET 10-BIT DAC 10-BIT DAC MODSET LASER DRIVERBIASSET 10-BIT DAC LUT LUT LUT LUT DS3911 I2C SLAVE TEMP SENSOR SDA VREF 3.3V RPU SCL I2C ADDRESS 3.3V 10-BIT DAC EEPROMMODSET LASER DRIVERBIASSET 10-BIT DAC 10-BIT DAC MODSET LASER DRIVERBIASSET 10-BIT DAC LUT LUT LUT LUT 2.5V

Maxim Integrated Products 7 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Pin Configuration Pin Description PIN NAME TYPE FUNCTION

1 DAC0 Output Delta-Sigma DAC Output

2 DAC1 Output Delta-Sigma DAC Output

3 VREF Input DAC Reference Voltage Input

4 GND Supply Ground

5 DAC2 Output Delta-Sigma DAC Output

6 DAC3 Output Delta-Sigma DAC Output

7, 8 N.C. — No Internal Connection

9 GND Supply Ground

10 A1 Input I2C Slave Address Input

11 A0 Input I2C Slave Address Input

12 SDA I/O 2-Wire Serial Data

13 SCL Input 2-Wire Clock

14 VCC Supply Positive Supply

— EP — Exposed Pad. Connect to ground. TOP VIEW TDFN (3mm x 5mm) 1DAC0 2DAC1 3VREF 4GND 5DAC2 6DAC3 7N.C.

14 VCC

13 SCL

12 SDA

9 GND

8 N.C. DS3911

Maxim Integrated Products 9 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC DAC Power-On Values Each 10-bit DAC is controlled directly by the value in its corresponding DAC VALUE register. Each DAC also has a DAC POR register that contains the power-on-reset (POR) value for the associated DAC, along with two con- trol bits: enable (EN) and polarity (POL). See the Lower Memory Register Descriptions section for complete lower memory descriptions. The DAC POR (DAC0 POR, DAC1 POR, DAC2 POR, and DAC3 POR) registers are shadowed EEPROM with func - tionality controlled by the shadow EEPROM bit ( SEE). If the SEE bit is high, the DAC POR registers function as SRAM only. If the SEE bit is low, the registers are shad - owed EEPROM and EEPROM write timing, t W, must be observed. On power-up, the initial DAC settings are always trans - ferred from the DAC POR registers to the corresponding DAC VALUE registers. Manual Control Mode On power-up, the device starts performing temperature conversions and the DAC VALUE register whose corre - sponding EN bit is set is updated by the LUT controller as described in the Lookup Table Mode section. Clearing the EN bit enables I2C writes to the corresponding DAC VALUE and disables LUT controller updates. This allows the indi- vidual DACs whose EN bit is cleared to be controlled by writing the corresponding DAC VALUE register directly. Lookup Table Mode The device has four nonvolatile memory tables, one for each of the four DACs. Each memory table is associated with an individual DAC as follows: Table 04h (DAC0), Table 05h (DAC1), Table 06h (DAC2), Table 07h (DAC3), and selected by setting the table select bits, TS[3:0], in the CTRL regis- ter. Each DAC memory table consists of a DAC LUT table (addresses 80h–AFh) (DAC0 LUT, DAC1 LUT, DAC2 LUT, and DAC3 LUT) and a DAC OFFSET table (addresses F8h–FFh) (DAC0 OFFSET, DAC1 OFFSET, DAC2 OFFSET, and DAC3 OFFSET). Because these four memory tables all share the same address and register mapping, the TS[3:0] bits must be used to select among them. Each LUT address represents as little as a 2 N change in temperature. Table 1 shows the full temperature-to- register mapping. The first DAC OFFSET address corresponds to 32 N of temperature. After this, every 16 N of temperature con - verts into one DAC OFFSET address slot. Table 2 shows the full temperature-to-register mapping. The TINDEX register points to a LUT address slot. The TINDEX register can operate in two modes, as defined by the AEN bit. When the AEN bit is cleared, I 2C writes to the TINDEX register are enabled, and updates from the LUT controller are blocked. The register can be used to force DAC updates to be based on the user-selected index. The TINDEX register directly addresses the LUT Table1.LUTTemperatureMapping Table2.OffsetTemperatureMapping ROW (HEX) BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 4NCLUT 80h < -36N -36N -32N -28N -24N -20N -16N -12N 88h -8N -4N 0N +4N +8N +12N +16N +20N 90h +24N +28N +32N +36N +40N +44N +48N +52N 2NCLUT 98h +56N +58N +60N +62N +64N +66N +68N +70N A0h +72N +74N +76N +78N +80N +82N +84N +86N A8h +88N +90N +92N +94N +96N +98N +100N R +102N ROW (HEX) BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 F8h < -8N -8N +8N +24N +40N +56N +72N R +88N

on the TINDEX value so only one pointer is necessary. the 16-bit DAC VALUE register. table location FCh and contains data = 2Ah. table location 94h and contains data = 7Bh. OFFSET values to ensure this overflow does not occur. Figure 4. DAC OFFSET LUT Examples EXAMPLE ILLUSTRATES POSITIVE TEMPCO.

Maxim Integrated Products 12 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. Repeated START Condition: The master can use a repeated START condition at the end of one data trans- fer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. BitWrite:Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements. Data is shifted into the device during the rising edge of the SCL. BitRead:At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledge (ACK and NACK): An acknowledge (ACK) or not-acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiv - ing data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one (done by releasing SDA) during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data (see Figure 7). A NACK is used to terminate a read sequence, or used as an indication that the device is not receiving data. ByteWrite: A byte write consists of 8 bits of informa - tion transferred from the master to the slave (most sig - nificant bit first) plus a 1-bit acknowledgment from the slave to the master. The 8 bits transmitted by the mas - ter are done according to the bit write definition and the acknowledgment is read using the bit read definition. ByteRead:A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I 2C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The device’s slave address is determined by the state of the A0 and A1 address pins as shown in Figure 6. Address pins connected to GND result in a 0 in the corre- sponding bit position in the slave address. Conversely, address pins connected to V CC result in a 1 in the corresponding bit positions. When the R/ W bit is 0 (such as in B0h), the master is indicating it will write data to the slave. If R/ W is set to 1 (B1h in this case), the master is indicating it wants to read from the slave. If an incorrect (nonmatching) slave address is written, the device assumes the master is communicating with another I 2C device and ignores the communication until the next START condition is sent. MemoryAddress:During an I2C write operation to the device, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. I2C Communication See Figure 7 for I2C communication examples. Writing a Single Byte to a Slave: The master must generate a START condition, write the slave address byte (R/ W = 0), write the memory address, write the byte of data, and generate a STOP condition. The mas- ter must read the slave’s acknowledgement during all byte write operations. When writing to the device, the DAC’s output adjusts to the new setting once it has acknowledged the new data that is being written, and writes to the EEPROM are written following the STOP condition at the end of the write command. Writing Multiple Bytes to a Slave: I2C write opera - tions of multiple bytes can also be performed. During a single write sequence, up to 8 bytes in one page

elapse before attempting to access the device. perform reads from a specified memory location. read another byte before terminating the transaction. Figure 7. I2C Communication Examples *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.

Maxim Integrated Products 14 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC bytes, after the last address counter position of FFh is accessed, the address counter automatically wraps back to the first location, 00h. Read operations can continue indefinitely. I2C LUT Lockout Both the I2C port and the LUT controller have access to the LUTs. To prevent bus/data contention, the LUT con - troller goes into a wait state instead of accessing the LUT if the I 2C port is active. Register updates and memory access are briefly described below.

• After a voltage or temperature conversion completes or the TINDEX register is calculated, the results are loaded into a shadow SRAM for the associated regis - ter by a backdoor that is not seen by the I2C port. The value is pushed forward to the SRAM cell seen by the I2C port at a later state. It is not pushed if the I2C port is active.
• After TINDEX is calculated and loaded into the shad - ow SRAM, the LUT controller goes into a round-robin loop where it updates the VCC VALUE, TEMP VALUE, and TINDEX registers, reads the DAC OFFSET and DAC LUT , performs the calculation, and loads the result into the DAC VALUE register. This process is where contention could occur. As such, the state machine waits until I 2C is inactive before performing this process. If the I 2C port were to become active for a long time period, the temperature compensation does not run. Memory Description The device’s internal memory consists of both volatile and nonvolatile registers located in Lower Memory and four separate memory tables (Upper Memory), as shown in Figure 8. The LowerMemory is addressed from 00h–7Fh. Lower Memory contains temperature reading, V CC reading, status bits, control registers, table select bits, and all four DAC VALUE and DAC POR registers. The UpperMemory consists of the following four memory tables. The table select bits, TS[3:0], determine which table is currently accessible through I2C at memory loca- tion 80h–FFh. Table04h contains a nonvolatile temperature-indexed DAC0 LUT and DAC0 OFFSET register designed to hold the pulse-density modulation profile for DAC0. Table05h contains a nonvolatile temperature-indexed DAC1 LUT and DAC1 OFFSET register designed to hold the pulse-density modulation profile for DAC1. Table06h contains a nonvolatile temperature-indexed DAC2 LUT and DAC2 OFFSET registers designed to hold the pulse-density modulation profile for DAC2. Table07h contains a nonvolatile temperature-indexed DAC3 LUT and DAC3 OFFSET registers designed to hold the pulse-density modulation profile for DAC3. Shadowed EEPROM The DAC POR memory locations are actually shadowed EEPROM and are controlled by the shadowed EEPROM bit, SEE. By default, SEE is not set and these locations act as ordinary EEPROM. By setting SEE these loca - tions function like SRAM cells, which allow an infinite number of write cycles without concern of wearing out the EEPROM. This also eliminates the requirement for the EEPROM write time, tW. Because changes made with SEE enabled do not affect the EEPROM, these changes are not retained through power cycles. The power-on value is the last value written with SEE disabled. This function can be used to speed up calibration and mini - mize the number of EEPROM write cycles.

Figure 8. Memory Map NOTE: TABLES 00h–03h AND 08h–0Fh DO NOT EXIST.

Maxim Integrated Products 16 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Register Description This register map shows each byte/word (2-byte) in terms of its row and byte/word placement in the memory. The first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte/ word on the row is one/two memory locations beyond the previous byte/word’s address. A total of 8 bytes are present on each row. See the Lower Memory Register Descriptions section for more information about each of these bytes. Lower Memory Register Map Lower Memory Register Descriptions LowerMemory,Register00h:CTRL LOWERMEMORY ADDR (HEX) WORD0 WORD1 WORD2 WORD3 BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 00h CTRL MODE SRAM TINDEX TEMP VALUE VCC VALUE 08h — 10h DAC3 VALUE DAC2 VALUE DAC1 VALUE DAC0 VALUE 78h DAC3 POR DAC2 POR DAC1 POR DAC0 POR POWER-ON VALUE 00h ACCESS R/W MEMORY TYPE Volatile 00h DONETEMP DONEVCC SRAM SRAM TS3 TS2 TS1 TS0 BIT 7 BIT 0 BIT 7 DONETEMP: Done Temp Status 0 = Temperature conversion in progress. 1 = Temperature conversion completed since this bit was last cleared. BIT 6 DONEVCC: Done VCC Status 0 = VCC conversion in progress. 1 = VCC conversion completed since this bit was last cleared. BITS 5:4 SRAM: General-Purpose SRAM. These bits have no affect on device operation. BITS 3:0 TS[3:0]: Table Select. The device’s memory tables are accessed by writing the desired table value in this bit field. The device only contains four addressable memory tables, 04h–07h, and therefore the values listed below are the only usable options. TS[3:0] TABLESELECTED CORRESPONDINGDACLUT 0100b 04h 0 0101b 05h 1 0110b 06h 2 0111b 07h 3

Maxim Integrated Products 17 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC LowerMemory,Register01h:MODE LowerMemory,Register02h:SRAM POWER-ON VALUE 00h ACCESS R/W MEMORY TYPE Volatile 02h SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM BIT 7 BIT 0 These general-purpose SRAM bits have no affect on device operation. POWER-ON VALUE 40h ACCESS R/W MEMORY TYPE Volatile 01h SEE AEN SRAM SRAM SRAM SRAM SRAM SOFTTXD BIT 7 BIT 0 BIT 7 SEE: Shadowed EEPROM Disable 0 = Enables EEPROM writes to the shadowed EEPROM bytes. 1 = Disables EEPROM writes to shadowed EPPROM bytes during configuration, so that the configuration of the device is not delayed by the EEPROM cycle time. Once the values are known, write this bit to a 0 and write the shadowed EEPROM locations again for data to be written to the EEPROM. BIT 6 AEN: Automatic Enable 0 = The temperature-calculated index value TINDEX is writable by the user and the automatic updates of calculated indexes are disabled. This allows users to interactively test their modules by controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC VALUE registers after the next completion of a temperature conversion. 1 = The internal temperature sensor determines the value of TINDEX. BITS 5:1 SRAM: General-Purpose SRAM. These bits have no affect on device operation. BIT 0 SOFTTXD:Soft Transmit Disable 0 = DACs operate normally. 1 = The DAC outputs are forced to the bit value of the POL bit, which is located in the DAC’s associate DAC POR register. For example, when SOFTTXD is set and POL = 1 in the DAC0 POR register, DAC0 is forced to full- scale output, but if POL = 0, DAC0 is forced to a zero output. This applies to all four DACs.

Maxim Integrated Products 18 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC LowerMemory,Register03h:TINDEX LowerMemory,Register04h–05h:TEMPVALUE POWER-ON VALUE 0000h ACCESS R MEMORY TYPE Volatile 04h S 26 25 24 23 22 21 20 05h 2-1 2-2 2-3 2-4 0 0 0 0 BIT 7 BIT 0 Left-justified signed two’s complement direct-to-temperature measurement. The lower 4 bits always return zero. The temperature reading is clamped to -128 NC and +127.9375NC. POWER-ON VALUE 00h ACCESS When AEN = 1: R ACCESS When AEN = 0: R/W MEMORY TYPE Volatile 03h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The TINDEX register is the temperature indexed address pointer. The TINDEX value corresponds directly to the LUT memory address for the given temperature ranges. The DAC OFFSET address is calculated based on the TINDEX value, so only one pointer is necessary. The pointer value is calculated based on the current temperature reading (see the below equation). The calculation uses different math depending on which LUT range (2NC or 4NC) the current temperature measurement resides in. temp 56 temp 56 Temperature 40 Temperature 8TINDEX 128 1284 2< ≥ + −= + = + A 1NC hysteresis is implemented in the TINDEX value calculation by adding 1 NC to temperature changes of nega - tive slope. When the AEN bit is high, the TINDEX register is read-only and the pointer is updated after the temperature and voltage conversions have completed. When the AEN bit is cleared, I 2C writes to the TINDEX register are enabled and updates from the LUT controller are blocked. The register can be used to force DAC updates to be based on the user-selected index. The TINDEX register directly addresses the LUT memory locations by dropping TINDEX[7] and forcing it high. When AEN = 0, any address between 80h and FFh can be addressed. To obtain known results in the DAC VALUE register, TINDEX should be kept between 80h and AFh. TINDEX value is clamped for temperatures below -40 NC and above 102NC.

Maxim Integrated Products 19 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC LowerMemory,Register06h–07h:VCCVALUE LowerMemory,Register10h–11h:DAC3VALUE LowerMemory,Register12h–13h:DAC2VALUE LowerMemory,Register14h–15h:DAC1VALUE LowerMemory,Register16h–17h:DAC0VALUE POWER-ON VALUE 0000h ACCESS R MEMORY TYPE Volatile 06h 212 211 210 29 28 27 26 25 07h 24 23 22 21 20 0 0 0 BIT 7 BIT 0 Left-justified unsigned voltage measurement. To calculate the supply voltage, simply convert the hexadecimal result into decimal and then multiply it by the LSB as shown in the Analog Voltage Monitoring Characteristics electrical characteristics table. The lower 3 bits always return zero. POWER-ON VALUE 0000h ACCESS When EN = 1: R ACCESS When EN = 0: R/W MEMORY TYPE Volatile 10h, 12h, 14h, 16h 29 28 27 26 25 24 23 22 11h, 13h, 15h, 17h 21 20 SRAM SRAM SRAM SRAM SRAM SRAM BIT 7 BIT 0 These registers are the left- justified digital 10-bit value used for their associated DAC output. The lower 6 bits have no effect on device operation. At POR these registers are updated to the EEPROM value DAC POR. When the EN bit in DAC POR is set, this register is updated at the end of each temperature conversion, with the calcu - lated result of values recalled from LUT and OFFSET LUT pointed to by TINDEX. REFDAC VV DAC VALUE1024= ×

Maxim Integrated Products 20 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC LowerMemory,Register78h–79h:DAC3POR LowerMemory,Register7Ah–7Bh:DAC2POR LowerMemory,Register7Ch–7Dh:DAC1POR LowerMemory,Register7Eh–7Fh:DAC0POR POWER-ON VALUE Recalled from EEPROM ACCESS R/W MEMORY TYPE Nonvolatile (SEE) 78h, 7Ah, 7Ch, 7Eh 29 28 27 26 25 24 23 22 79h, 7Bh, 7Dh, 7Fh 21 20 SEE SEE SEE SEE POL EN BIT 7 BIT 0 BITS 15:6 A left-justified, digital, 10-bit initial DAC value. During a POR these 10 bits are used to fill the corresponding DAC VALUE register. BITS 5:2 SEE: These bits have no effect on device operation. BIT 1 POL: Polarity Select 0 = Normal DAC mode, DAC VALUE = 3FFh results in full-scale output. 1 = Inverted DAC mode, DAC VALUE = 3FFh results in zero output. BIT 0 EN:LUT Enable 0 = DAC mode: At power-on, the corresponding DAC VALUE register is loaded with the value stored in the corresponding DAC POR register. Updates from the temperature-referenced LUT and LUT OFFSET are disabled. The user can write to the DAC VALUE register to set the value for the DAC. The DAC VALUE register is R/W. 1 = LUT mode: At power-on, the corresponding DAC VALUE register is loaded with the value stored in the corresponding DAC POR register. After the first valid temperature conversion, the DAC VALUE register is loaded with the value calculated from the LUT and LUT OFFSET that correspond to the measured temperature. The DAC VALUE register is read-only.

Maxim Integrated Products 21 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Upper Memory Register Descriptions Table04h,Register80h–AFh:DAC0LUT Table05h,Register80h–AFh:DAC1LUT Table06h,Register80h–AFh:DAC2LUT Table07h,Register80h–AFh:DAC3LUT FACTORY DEFAULT 00h ACCESS R/W MEMORY TYPE Nonvolatile 80h–AFh 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The DAC LUT is a set of registers assigned to hold the pulse-density modulation profile for the associated DAC. The values in this table are added to four times the corresponding value in the DAC OFFSET table to determine the set point for the associated DAC. In all four DAC tables, the DAC LUT registers are formatted the same. Beginning at -40NC, the LUT increments in 4 NC steps per address until the temperature reaches 56 NC, then it increments in 2NC steps until it clamps at 102 NC. See the LUT Temperature Mapping table for full register-to- temperature mapping. Register 80h defines the -40 NC to -36NC DAC LUT value, register 81h defines the -36NC to -32NC DAC LUT value, and so on. LUTTEMPERATUREMAPPING ROW (HEX) BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 4NCLUT 80h < -36N -36N -32N -28N -24N -20N -16N -12N 88h -8N -4N 0N +4N +8N +12N +16N +20N 90h +24N +28N +32N +36N +40N +44N +48N +52N 2NCLUT 98h +56N +58N +60N +62N +64N +66N +68N +70N A0h +72N +74N +76N +78N +80N +82N +84N +86N A8h +88N +90N +92N +94N +96N +98N +100N R +102N

Maxim Integrated Products 22 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Table04h,RegisterF8h–FFh:DAC0OFFSET Table05h,RegisterF8h–FFh:DAC1OFFSET Table06h,RegisterF8h–FFh:DAC2OFFSET Table07h,RegisterF8h–FFh:DAC3OFFSET Applications Information Power-Supply Decoupling To achieve the best results when using the DS3911, decouple the power supply with a 0.01FF or 0.1FF capac- itor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceram - ic capacitors tend to have adequate high-frequency response for decoupling applications. Likewise, a decou- pling capacitor should be placed from VREF to GND. SDA and SCL Pullup Resistors SDA is an I/O with an open-collector output that requires a pullup resistor to realize high-logic levels. A master using either an open-collector output with a pullup resis - tor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the I2C AC Electrical Characteristics table are within specification. A typical value for the pullup resistors is 4.7k I. FACTORY DEFAULT 00h ACCESS R/W MEMORY TYPE Nonvolatile F8h–FFh 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The DAC OFFSET is a set of registers assigned to hold the pulse-density modulation profile for the associated DAC. The values in this table are multiplied by four and added to the corresponding value in the LUT table to determine the set point for the associated DAC. In all four DAC tables, the DAC OFFSET registers are formatted the same. The OFFSET registers increase in 16NC steps from -8NC to +88NC. Below -8NC the DAC OFFSET is indexed at 0xF8. See the Offset Temperature Mapping table for full register to temperature mapping. Register F8h defines the -40NC to -8NC DAC OFFSET value, register F9h defines the -8NC to +8NC DAC OFFSET value, and so on. OFFSETTEMPERATUREMAPPING ROW (HEX) BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 F8h < -8N -8N +8N +24N +40N +56N +72N R +88N

Maxim Integrated Products 23 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Ordering Information Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.Note: Contact the factory about CSBGA version availability. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. PART TEMPRANGE PIN-PACKAGE DS3911T+ -40NC to +100NC 14 TDFN-EP* DS3911T+T -40NC to +100NC 14 TDFN-EP* PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERNNO.

14 TDFN-EP T1435N+1 21-0253 90-0246

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 24 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC

Revision History

0 6/11 Initial release —