DS3903E-020/T

DS3903 MAXIM | Alldatasheet

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Technical content

Features

♦ Three 128-Position Linear Potentiometers (Two 10kΩ, One 90kΩ) ♦ NV Wiper Storage ♦ 0 to 5.5V on Any Potentiometer Terminal Independent of VCC ♦ Low End-to-End Temperature Coefficient ♦ Operates on an Industry-Standard 2-Wire Bus ♦ Write-Protect Pin ♦ Supply Voltage: 3V or 5V ♦ Operating Temperature Range: -40°C to +85°C ♦ Packaging: 20-Pin TSSOP DS3903 Triple 128-Position Nonvolatile Digital Potentiometer 129 SDA VCC 192SCL N.C. N.C. N.C. N.C. TSSOP WP N.C. GND DS3903 Pin Configuration 0.1µF 4.7kΩ 2-WIRE MASTER VCC VCC VCC VREF1 VREF2 5.1kΩ Iref VCC SCL SDA POTENTIOMETER 2 10kΩ ADDDR FAh POTENTIOMETER 0 10kΩ ADDDR F9h POTENTIOMETER 1 90kΩ ADDDR F8h WP GND 4.7kΩ VARIABLE RESISTANCE FOR ADJUSTABLE CURRENT SOURCE HIGH-OUTPUT-IMPEDANCE VOLTAGE REFERENCE BUFFERED VOLTAGE REFERENCE VCC MAX427 DS3903 Typical Operating Circuit

Ordering Information

Rev 0; 6/02 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART TEMP RANGE PIN-PACKAGE DS3903E-020 -40°C to +85°C 20 TSSOP DS3903E-020/T&R -40°C to +85°C 20 TSSOP (Tape-and-Reel)

Triple 128-Position Nonvolatile Digital Potentiometer ABSOLUTE MAXIMUM RATINGS RECOMMENDED DC OPERATING CONDITIONS (TA = -40° to +85°C) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on SDA, SCL, A0, and WP V CC + 0.5V Voltage on L0, L1, L2, W0, W1, W2, H0, H1, and Specification PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC (Note 1) +2.7 +5.5 V Input Logic 1 V IH (Notes 2, 3) 0.7 x VCC VCC + 0.3 V Input Logic 0 V IL (Notes 2, 3) -0.3 0.3 x VCC V Wiper Current I W -3 +3 mA Resistor Terminals L0, L1, L2, W0, W1, W2, H0, H1, H2 VCC = +2.7V to +5.5V -0.3 +5.5 V DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V to 5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage I L -1 +1 µA VCC = 3V (Note 2) 100 200Standby Supply Current I stby VCC = 5V (Note 2) 150 250 µA VOL1 3mA sink current 0 0.4 VLow-Level Output Voltage (SDA) VOL2 6mA sink current 0 0.6 V I/O Capacitance C I/O 10 pF WP Internal Pullup Resistance R WP 35 65 110 k Ω

Triple 128-Position Nonvolatile Digital Potentiometer AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V to 5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Fast mode (Note 4) 0 400SCL Clock Frequency f SCL Standard mode (Note 4) 0 100 kHz Fast mode (Note 4) 1.3Bus Free Time Between Stop and Start Conditions tBUF Standard mode (Note 4) 4.7 µs Fast mode (Notes 4, 5) 0.6Hold Time (Repeated) Start Condition tHD:STA Standard mode (Notes 4, 5) 4.0 µs Fast mode (Note 4) 1.3Low Period of SCL Clock t LOW Standard mode (Note 4) 4.7 µs Fast mode (Note 4) 0.6High Period of SCL Clock t HIGH Standard mode (Note 4) 4.0 µs Fast mode (Notes 4, 6, 7) 0 0.9Data Hold Time tHD:DAT Standard mode (Notes 4, 6, 7) 0 0.9 µs Fast mode (Note 4) 100Data Set-Up Time tSU:DAT Standard mode (Note 4) 250 ns Fast mode 0.6Start Set-Up Time t SU:STA Standard mode 4.7 µs Fast mode (Note 8) 20 + 0.1CB 300Rise Time of Both SDA and SCL Signals tR Standard mode (Note 8) 20 + 0.1CB 1000 ns Fast mode (Note 8) 20 + 0.1CB 300Fall Time of Both SDA and SCL Signals tF Standard mode (Note 8) 20 + 0.1CB 300 ns Fast mode 0.6Set-Up Time for Stop Condition tSU:STO Standard mode 4.7 µs Capacitive Load for Each Bus CB (Note 8) 400 pF EEPROM Write Time t W (Note 9) 10 ms Startup Time t ST 2m s ANALOG RESISTOR CHARACTERISTICS (VCC = 2.7V to 5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS End-to-End Resistance Tolerance +25°C -20 +20 % 10kΩ Pot 10.5End-to-End Resistance 90kΩ Pot 90 kΩ Factory-Default Wiper Setting Position 127 (max resistance) Wiper Resistance R W 250 500 Ω Absolute Linearity (Note 10) -1.0 +1.0 LSB Relative Linearity (Note 11) -0.25 +0.25 LSB End-to-End Temperature Coefficient -300 0 +300 ppm/°C Ratiometric Temperature Coefficient ±30 ppm/°C

Triple 128-Position Nonvolatile Digital Potentiometer Note 1: All voltages are referenced to ground. Note 2: ISTBY specified for VCC equal to 3.0V and 5.0V while control port logic pins are driven to the appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or VCC for the corresponding inactive state. WP must be disconnected or connected high. Note 3: I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off. Note 4: A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t RMAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. Note 5: After this period, the first clock pulse is generated. Note 6: The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIN MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Note 8: CB—total capacitance of one bus line in picofarads, timing referenced to 0.9 x V CC and 0.1 x VCC. Note 9: EEPROM write begins after a stop condition occurs. Note 10: Absolute linearity is used to measure expected wiper voltage as determined by wiper position in a voltage-divider configuration. Note 11: Relative linearity is used to determine the change of wiper voltage between two adjacent wiper positions in a voltage-divider configuration. Typical Operating Characteristics (VCC = 5.0V, 10kΩ plots apply to both pot0 and pot2, TA = +25°C unless otherwise noted.) 100 W-L RESISTANCE vs. WIPER SETTING (90kΩ) DS3903 toc03 WIPER SETTING W-L RESISTANCE (kΩ) 1251007550250 W-L RESISTANCE vs. WIPER SETTING (10kΩ) DS3903 toc02 WIPER SETTING W-L RESISTANCE (kΩ) 125100755025 STANDBY SUPPLY CURRENT vs. TEMPERATURE DS3903 toc01 TEMPERATURE (°C) SUPPLY CURRENT (µA) 5040-30 -20 -10 10 2003 0 100 120 140 160 -40 60 70 80 VCC = 5V VCC = 3V

Triple 128-Position Nonvolatile Digital Potentiometer END-TO-END RESISTANCE PERCENT CHANGE FROM 25°C vs. TEMPERATURE (90kΩ) DS3903 toc09 TEMPERATURE (°C) % CHANGE 807050 60-10 0 10 2 03 04 0-30 -20 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 1.0 -0.8 -1.0 -40 END-TO-END RESISTANCE PERCENT CHANGE FROM 25°C vs. TEMPERATURE (10kΩ) DS3903 toc08 TEMPERATURE (°C) % CHANGE 807050 60-10 0 10 2 03 04 0-30 -20 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 1.0 -0.8 -1.0 -40 VOLTAGE-DIVIDER PERCENT CHANGE FROM 25°C vs. TEMPERATURE (10kΩ) DS3903 toc07 TEMPERATURE (°C) % CHANGE (FROM 25°C) 807050 60-10 0 10 2 03 04 0-30 -20 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 -0.05 -0.06 -40 WIPER = 60h WIPER = 20h Tc = 1.9ppm/°C Tc = 0.7ppm/°C WIPER = 40h Tc = 5.0ppm/°C VOLTAGE-DIVIDER PERCENT CHANGE FROM 25°C vs. TEMPERATURE (10kΩ) DS3903 toc06 TEMPERATURE (°C) % CHANGE (FROM 25°C) 807050 60-10 0 1 02 03 04 0-30 -20 -0.04 -0.02 0.02 0.04 0.06 0.08 0.10 0.12 -0.06 -40 WIPER = 60h WIPER = 20h Tc = 18.0ppm/°C Tc = 3.7ppm/°C WIPER = 40h Tc = 1.5ppm/°C WIPER RESISTANCE vs. WIPER VOLTAGE (90kΩ) DS3903 toc05 WIPER VOLTAGE (V) WIPER RESISTANCE (Ω) 34521 100 150 200 250 300 350 VCC = 3V POS 7Fh WIPER RESISTANCE vs. WIPER VOLTAGE (10kΩ) DS3903 toc04 WIPER VOLTAGE (V) WIPER RESISTANCE (Ω) 34521 100 150 200 250 300 350 VCC = 3V POS 7Fh Typical Operating Characteristics (continued) (VCC = 5.0V, 10kΩ plots apply to both pot0 and pot2, TA = +25°C unless otherwise noted.) VOLTAGE-DIVIDER ABSOLUTE LINEARITY vs. WIPER SETTING (10kΩ) DS3903 toc11 WIPER SETTING ABSOLUTE LINEARTIY (LSB) 10080604020 0.04 0.08 0.12 0.16 0.20 0 120 VOLTAGE-DIVIDER RELATIVE LINEARITY vs. WIPER SETTING (10kΩ) DS3903 toc10 WIPER SETTING RELATIVE LINEARTIY (LSB) 10080604020 0.01 0.02 0.03 0.04 0.05 0 120

Triple 128-Position Nonvolatile Digital Potentiometer Typical Operating Characteristics (continued) (VCC = 5.0V, 10kΩ plots apply to both pot0 and pot2, TA = +25°C unless otherwise noted.) VOLTAGE-DIVIDER ABSOLUTE LINEARITY vs. WIPER SETTING (90kΩ) DS3903 toc13 WIPER SETTING ABSOLUTE LINEARTIY (LSB) 10080604020 0.04 0.08 0.12 0.16 0.20 0 120 VOLTAGE-DIVIDER RELATIVE LINEARITY vs. WIPER SETTING (90kΩ) DS3903 toc12 WIPER SETTING RELATIVE LINEARTIY (LSB) 10080604020 0.01 0.02 0.03 0.04 0.05 0 120 Pin Description PIN NAME FUNCTION 1 SDA 2-Wire Serial Data. Input/output for 2-wire data. 2 SCL 2-Wire Serial Clock. Input for 2-wire clock. 3A 0 Address-Select Input. Determines device 2-wire address. 4W P Write-Protect Input. Must be grounded to write to the potentiometer registers. An internal pullup locks the potentiometer positions if this pin is not connected. 5, 16, 17 18, 19 N.C. No Connection 6, 8, 9 L0, L1, L2 Potentiometer Low Terminals. Voltages on these pins should remain between GND and +5.5V while VCC is above +2.7V. Low terminals can be at potentials above the wiper or high terminals. 7, 12, 14 W1, W2, W0 Potentiometer Wiper Terminal. Voltages on these pins should remain between GND and +5.5V while VCC is above +2.7V.

10 GND Ground Terminal

11, 13, 15 H2, H1, H0 Potentiometer High Terminals. Voltages on these pins should remain between GND and +5.5V while VCC is above +2.7V. High terminals can be at potentials below the low terminals.

20 V CC Supply Voltage Terminal

tiometer as a 2-terminal variable resistor. be placed on the same 2-wire bus. potentiometers retain their settings. communicating with the registers in Table 1. diagrams for further details (Figures 2 and 3). the timing diagrams for further details (Figures 2 and 3). ing diagrams for further details (Figures 2 and 3). 2) Look for SDA high in each cycle while SCL is high. 3) Create a start condition while SDA is high. Figure 1. DS3903 Block Diagram Table 1. Potentiometer Registers

Triple 128-Position Nonvolatile Digital Potentiometer write process tw to the EEPROM memory. All inputs are disabled during this write cycle. The DS3903 is capable of an 8-byte page write. A page write is initiated the same way as a byte write, but the master does not send a stop condition after the first data byte. Instead, after the slave acknowledges the data byte has been received, the master can send up to seven more data bytes using the same nine-clock sequence. After a write to the last byte in the page, the address returns to the beginning of the same page. The master must then terminate the write cycle with a stop condition or the data clocked into the DS3903 is not latched into EEPROM. Note that in order for eight bytes to be stored sequentially (and to prevent looping around), the address byte must be set to the beginning of the desired page (three LSBs of the address are 0). For detailed information concerning page operations, see the Potentiometer Memory Organization section. Acknowledge Polling Once the internally timed write has started and the DS3903 inputs are disabled, acknowledge polling can be initiated. The process involves transmitting a start condition followed by the device address. The R/W bit signifies the type of operation that is desired. The read or write sequence is only allowed to proceed if the internal write cycle has completed and the DS3903 responds with a zero. Read Operations After receiving a matching address byte with the R/W bit set high, the device goes into the read mode of opera- tion. There are three read operations: current address read, random read, and sequential address read. Current Address Read The DS3903 has an internal address register that main- tains the address used during the last read or write operation, incremented by one. This data is maintained as long as V CC is valid. If the most recent address was the last byte in memory, then the register resets to the first address. This address stays valid between opera- tions as long as power is available. Once the device address is clocked in and acknowl- edged by the DS3903 with the R/W bit set to high, the current address data word is clocked out. The master does not respond with a zero, but does generate a stop condition afterwards. Random Address Read A random read requires a dummy byte write sequence to load in the data word address. Once the device address and data address bytes are clocked in by the master, and acknowledged by the DS3903, the master must generate another start condition. The master now initiates a current address read by sending the device address with the R/W bit set high. The DS3903 acknowledges the device address and serially clocks out the data byte. Sequential Address Read Sequential reads are initiated by either a current address read or a random address read. After the mas- ter receives the first data byte, the master responds with an acknowledge. As long as the DS3903 receives this acknowledge after a byte is read, the master can clock out additional data words from the DS3903. After reaching address FFh, it resets to address 00h. The sequential read operation is terminated when the master initiates a stop condition. The master does not respond with a zero. For a more detailed description of 2-wire theory of operation, see the following section. 2-Wire Serial Port Operation The 2-wire serial port interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a trans- mitter, and a device receiving data as a receiver. The device that controls the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the start and stop con- ditions. The DS3903 operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines, SDA and SCL. The following I/O terminals control the 2-wire serial port: SDA, SCL, and A0. Timing diagrams for the 2-wire serial port can be found in Figures 2 and 3. Timing information for the 2- wire serial port is provided in the AC Electrical Characteristics table for 2-wire serial communications.

Triple 128-Position Nonvolatile Digital Potentiometer The following bus protocol has been defined: Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as con- trol signals. Accordingly, the following bus conditions have been defined: Bus Not Busy: Both data and clock lines remain high. Start Data Transfer: A change in the state of the data line from high to low while the clock is high defines a start condition. Stop Data Transfer: A change in the state of the data line from low to high while the clock line is high defines the stop condition. Data Valid: The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line can be changed during the low period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS3903 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the stop condition. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the com- mand/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The mas- ter returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge can be returned. The master device generates all serial clock pulses and the start and stop conditions. A transfer is ended with a stop condition or with a repeated start condition. Since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. The DS3903 can operate in the following three modes: 1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL, respectively. After each byte is received, an acknowledge bit is trans- mitted. Start and stop conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after the slave (device) address and direction bit has been received. 2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS3903 while the serial clock is input on SCL. Start and stop conditions are recognized as the beginning and end of a serial transfer. 3) Slave Address: Command/control byte is the first byte received following the start condition from the master device. The command/control byte consists of a 6-bit control code. For the DS3903, this is set as 101000 binary for read/write operations. The next bit of the command/control byte is the device select bit or slave address (A0). It is used by the master device to select which of two devices is to be accessed. When reading or writing the DS3903, the device-select bits must match the device-select pin (A0). The last bit of the command/control byte (R/W) defines the operation to be performed. When set to a ‘1’, a read operation is selected, and when set to a ‘0’, a write operation is selected. Following the start condition, the DS3903 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving the 101000 control code,

Triple 128-Position Nonvolatile Digital Potentiometer Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. the appropriate device address bit, and the read/write bit, the slave device outputs an acknowledge signal on the SDA line. Applications Information Power-Supply Decoupling To achieve the best results when using the DS3903, decouple the power supply with a 0.01µF or 0.1µF capacitor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount components mini- mize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high- frequency response for decoupling applications. Write Protection The write-protect pin has an internal pullup resistor. To be able to adjust the potentiometers’ position, this pin must be grounded. This pin can be left floating or con- nected to V CC to write protect the potentiometer posi- tions. Wiper Resistance and Wiper Current Limit Two substantial differences between digital poten- tiometers and mechanical potentiometers are the wiper resistance and the wiper current limit. The wiper resis- tance (R W) is a result of the interconnecting materials on the IC between the internal resistive elements and the wiper pin. This can be modelled by using an ideal potentiometer, with a resistance of R W connected between the ideal wiper and wiper terminal of the digi- tal potentiometer. One final note about the wiper resis- tance is that it has a high temperature coefficient (approximately +3000PPM), which can be noticeable in certain circuit configurations. The wiper current limit (I W) is also due to the intercon- necting materials between the internal resistive ele- ments and the wiper terminal. While it may be possible to exceed this value for a short period without prob- lems, exceeding the wiper current limit is a long-term reliability problem. Both characteristics can be minimized in designs by connecting the wiper terminal to high-impedance loads. This reduces both the current through the wiper and the voltage drop across the wiper resistance. Using a Potentiometer as a Variable Resistor There are two ways to make a digital potentiometer into a variable resistor. The first is to short the wiper terminal to the high- or low-side terminal. This places wiper resistance in parallel with the resistance from the wiper to the high or low side of the potentiometer. The advan- tage of this method is that it reduces the current through the wiper, which is advantageous if the current is approaching the wiper current limit. The disadvan- tage is that the wiper resistance makes the resistance versus position nonlinear, particularly for low-resistance values. The second way is to attach the wiper terminal, and either the low- or high-side terminal. The unattached terminal is connected to the wiper by the resistance internal to the part, and stays at the same voltage as the wiper. This method provides a linear resistance ver- sus position function, but it limits the current through the resistance to I W since there is no current load shar- ing between the wiper resistance and the paralleled resistive elements. Both configurations are heavily influenced by the wiper resistance, particularly over temperature, where its tem- perature coefficient noticeably affects the resistor’s value. Chip Information TRANSISTOR COUNT: 10,793 SUBSTRATE CONNECTED TO GROUND

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