DS3884A

DS3884A NSC | Alldatasheet

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n Fast propagation delay (3 ns typ) n 6-bit BTL transceiver n Selective receiver glitch filtering (FR1–FR3) n Meets 1194.1 Standard on Backplane Transceiver Logic (BTL) n Supports live insertion n Glitch free power-up/down protection n Typically less than 5 pF bus-port capacitance n Low Bus-port voltage swing (typically 1V) at 80 mA n TTL compatible driver and control inputs n Separate TTL I/O n Open collector bus-port outputs allow Wired-OR connection n Controlled rise and fall time to reduce noise coupling to adjacent lines n Built in Bandgap reference with separate QVCC and QGND pins for precise receiver thresholds n Exceeds 2 kV ESD testing (Human Body Model) n Individual Bus-port ground pins n Product offered in PQFP package styles Connection Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. DS011460-1 Order Number DS3884AVF See NS Package VF44B August 2000 DS3884A BTL Handshake Transceiver © 2000 National Semiconductor Corporation DS011460 www.national.com

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Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage 6.5V Control Input Voltage 6.5V Driver Input and Receiver Output 5.5V Receiver Input Current ±15 mA Bus Termination Voltage 2.4V Power Dissipation at 25˚C PQFP 1.3W Derate PQFP Package 11.1 mW/˚C Storage Temperature Range −65˚C to +150˚C Lead Temperature (Soldering, 4 seconds): 260˚C Recommended Operating Conditions Supply Voltage, VCC 4.5V–5.5V Bus Termination Voltage (VT) 2.06V–2.14V Operating Free Air Temperature 0˚C to 70˚C TA = 0 to +70˚C, VCC =5 V ±10% Symbol Parameter Conditions Min Typ Max Units DRIVER AND CONTROL INPUT: (Dn, DE*, PS1 and PS2) VIH Minimum Input High Voltage 2.0 V VIL Maximum Input Low Voltage 0.8 V II Input Leakage Current V IN =V CC = 5.5V 100 µA IIH Input High Current V IN = 2.4V 40 µA IIL Input Low Current V IN = 0.5V −100 µA VCL Input Diode Clamp Voltage I CLAMP = −12 mA −1.2 V DRIVER OUTPUT/RECEIVER INPUT: (Bn) VOLB Output Low Bus Voltage Dn = 2.4V, DE * = 0V, 0.75 1.0 1.1 V (Note 5) I OL =8 0m A IOLBZ Output Low Bus Current Dn = 0.5V, DE * = 2.4V, Bn = 0.75V 100 µA IOHBZ Output High Bus Current Dn = 0.5V, DE * = 2.4V, Bn = 2.1V 100 µA IOLB Output Low Bus Current Dn = 0.5V, DE * = 0V, Bn = 0.75V 220 µA IOHB Output High Bus Current Dn = 0.5V, DE * = 0V, Bn = 2.1V 350 µA VTH Receiver Input Threshold DE * = 2.4V 1.47 1.55 1.62 V VCLP Positive Clamp Voltage V CC = Max or 0V, IBn = 1 mA 2.4 3.4 4.5 V VCC = Max or 0V, IBn = 10 mA 2.9 3.9 5.0 V VCLN Negative Clamp Voltage I CLAMP = −12 mA −1.2 V RECEIVER OUTPUT: (FRn and Rn) VOH Voltage Output High Bn = 1.1V, DE * = 2.4V, IOH = −2 mA 2.4 3.2 V VOL Voltage Output Low Bn = 2.1V, DE * = 2.4V, IOL = 24 mA 0.35 0.5 V Bn = 2.1V, DE* = 2.4V, IOL = 8 mA 0.35 0.4 V IOS Output Short Circuit Current Bn = 1.1V, DE* = 2.4V (Note 4) −40 −70 −100 mA SUPPLY CURRENT I CC Supply Current: Includes VCC ,D E * = 0.5V, All Dn = 2.4V 50 70 mA QV CC and LI DE * = 2.4V, All Bn = 2.1V 50 70 mA ILI Live Insertion Current DE * = 2.4V, All Dn = 0.5V 1 3 mA DE * = 0.5V, All Dn = 2.4V 2 5 mA Note 1:“Absolute Maximum Ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provide conditions for actual device operation. Note 2: All input and/or output pins shall not exceed VCC plus 0.5V and shall not exceed the absolute maximum rating at anytime, including power-up and power-down. This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QVCC and VCC . There is a diode between each input and/or output to VCC which is forward biased when incorrect sequencing is applied. Alternatively, a current limiting resistor can be used when pulling-up the inputs to prevent damage. The current into any input/output pin shall be no greater than 50 mA. Exception, LI and Bn pins do not have power sequencing requirements with respect to VCC and QVCC . Furthermore, the difference between VCC and QVCC should never be greater than 0.5V at any time including power-up. Note 3:All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. All typical values are specified under these conditions.: VCC = 5V and TA = 25˚C unless otherwise stated. Note 4:Only one output should be shorted at a time, and duration of the short should not exceed one second. Note 5: Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package. DS3884A www.national.com3

TA = 0˚C to +70˚C, VCC =5 V ±10% Symbol Parameter Conditions Min Typ Max Units DRIVER t PHL Dn to Bn Prop. Delay DE * = 0 V 135 n s tPLH (Figure 1,Figure 2) 135 n s tPHL DE * to Bn Enable Time Dn = 3V 2 4 6 ns tPLH Disable Time ( Figure 1,Figure 3) 246 n s tr Transition Time — Rise/Fall ( Figure 1,Figure 2) 1 2 3.5 ns tf 20% to 80% 1 2 3.5 ns SR Skew Rate is Calculated (Note 11) 0.5 V/ns from 1.3V to 1.8V tskew Skew between Drivers in (Note 7) 1 3 ns the Same Package RECEIVER t PHL Bn to Rn Prop. Delay DE * = 3 V 245 n s tPLH (Figure 4,Figure 5) 246 n s tskew Skew between Receivers in (Note 7) 1 3 ns Same Package FILTERED RECEIVER t PHL Bn to FRn Prop. Delay PS1 = 0V PS2 = 0V DE * = 3V 6 12 16 ns (Figure 4,Figure 5), REXT =1 3kΩ P S 1=0 V P S 2=3 V D E* = 3 V 1 11 62 1 n s (Figure 4,Figure 5), REXT =1 3kΩ P S 1=3 V P S 2=0 V D E* = 3 V 1 52 12 7 n s (Figure 4,Figure 5), REXT =1 3kΩ P S 1=3 V P S 2=3 V D E* = 3 V 2 53 34 5 n s (Figure 4,Figure 5), REXT =1 3kΩ tPLH Bn to FRn Prop. Delay DE * =3 V(Figure 4,Figure 5) (Note 8) 257 n s R EXT =1 3kΩ tGR Glitch Rejection PS1 = 0V PS2 = 0V DE * =3 V 5 9 1 6 n s (Figure 4,Figure 6), REXT =1 3kΩ P S 1=0 V P S 2=3 V D E* = 3 V 1 01 31 8 n s (Figure 4,Figure 6), REXT =1 3kΩ P S 1=3 V P S 2=0 V D E* = 3 V 1 41 82 4 n s (Figure 4,Figure 6), REXT =1 3kΩ P S 1=3 V P S 2=3 V D E* = 3 V 2 43 14 2 n s (Figure 4,Figure 6), REXT =1 3kΩ FILTERED RECEIVER TIMING REQUIREMENTS t s PSn to Bn Set-Up Time ( Figure 7), REXT =1 3kΩ 250 ns PARAMETERS NOT TESTED Coutput Capacitance at Bn (Note 9) 5 pF t NR Noise Rejection (Note 10) 1 ns Note 6:Input waveforms shall have a rise/fall time of 3 ns. Note 7:tskew is an absolute value defined as differences seen in propagation delays between drivers in the same package with identical load conditions. Note 8:Filtered receiver tPLH is independent of filter setting. Note 9:The parameter is tested using TDR techniques described in P1194.0 BTL Backplane Design Guide. Note 10: This parameter is tested during device characterization. The measurements revealed that the part will reject 1 ns pulse width. Note 11:Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster than 0.5V/ns, measured between 1.3V and 1.8V (approximately20% to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5Ω tied to +2.1V DC. DS3884A www.national.com 4

Pin Name Number of Input/ Description Pins Output B1–B6 6 I/O BTL receiver input and driver output B1GND–B6GND 6 NA Driver output ground reduces bounce due to high current switching of driver outputs (Note 12) DE * 1 I Driver Enable Low D1–D6 6 I TTL Driver Input FR1–FR3 3 O TTL Filtered Receiver Output GND 3 NA Ground reference for switching circuits. (Note 12) LI 1 NA Power supply for live insertion. Boards that require live insertion should connect LI to the live insertion pin on the connector. (Note 13) NC 4 NA No Connect PS1, PS2 2 I Pulse Width Selection pin determines glitch filter setting (Note 14) R1–R6 6 O TTL Receiver Output REXT 1 NA External Resistor pin. External resistor is used for internal biasing of filter circuitry. The 13 kΩ resistor shall be connected between REXT and GND. The resistor shall have a tolerance of 1% and a temperature coefficient of 100 ppm/˚C or better. QGND 2 NA Ground reference for receiver input bandgap reference and non-switching circuits (Note 12) QV CC 1N A V CC supply for bandgap reference and non-switching circuits (Note 13) VCC 2N A V CC supply for switching circuits (Note 13) Note 12:the multiplicity of grounds reduces the effective inductance of bonding wires and leads, which then reduces the noise caused by transients on the ground path. The various ground pins can be tied together provided that the external ground has low inductance (i.e., ground plane with power pins and many signal pins connected to the backplane ground). If the external ground floats considerably during transients, precautionary steps should be taken to prevent QGND from moving with reference to the backplane ground. The receiver threshold should have the same ground reference as the signal coming from the backplane. A voltage offset between their grounds will degrade the noise margin. Note 13:The same considerations for ground are used for VCC in reducing lead inductance (see Note 12). QVCC and VCC should be tied together externally. If live insertion is not supported, the LI pin can be tied together with QVCC and VCC . Note 14: See AC characteristics for filter setting. DS3884A www.national.com5

Application Information(Continued) In Wired-OR applications, the glitch generated as drivers are released from the bus, is dependent upon the backplane and parasitic wiring components causing the characteristics of the glitch to vary in pulse width and amplitude. To accommo- date this variation the DS3884A features two pins defined as PS1 and PS2 which allow selection of a 5 ns, 10 ns, 14 ns and 24 ns filter setting to optimize glitch filtering for a given situation. The REXT pin is issued in conjunction with the fil- tering circuitry and requires a 13 kΩ resistor to ground. For additional information on Wired-OR glitch, reference Applica- tion Note AN-774. The DS3884A driver output configuration is an NPN open collector which allows Wired-OR connection on the bus. Each driver output incorporates a Schottky diode in series with its collector to isolate the transistor output capacitance from the bus thus reducing the bus loading in the inactive state. The combined output capacitance of the driver and re- ceiver input is typically less than 5 pF. The driver also has high sink current capability to comply with the bus loading re- quirements defined within IEEE 1194.1 BTL specification. Backplane Transceiver Logic (BTL) is a signaling standard that was invented and first introduced by National Semicon- ductor, then developed by the IEEE to enhance the perfor- mance of backplane buses. BTL compatible transceivers feature low output capacitance drivers to minimize bus load- ing, a 1V nominal signal swing for reduced power consump- tion and receivers with precision thresholds for maximum noise immunity. The BTL standard eliminates settling time delays that severely limit TTL bus performance, and thus provide significantly higher bus transfer rates. The back- plane bus is intended to be operated with termination resis- tors (selected to match the bus impedance) connected to 2.1V at both ends. The low voltage is typically 1V. Separate ground pins are provided for each BTL output to minimize induced ground noise during simultaneous switch- ing. The device’s unique driver circuitry meets a maximum slew rate of 0.5V/ns which allows controlled rise and fall times to reduce noise coupling to adjacent lines. The transceiver’s high impedance control and driver inputs are fully TTL compatible. The receiver is a high speed comparator that utilizes a band- gap reference for precision threshold control allowing maxi- mum noise immunity to the BTL 1V signaling level. Separate QV CC and QGND pins are provided to minimize the effects of high current switching noise. Output pins FR1–FR3 are the filtered outputs and R1–R6 are the unfil- tered outputs. All receiver outputs are fully TTL compatible. The DS3884A supports live insertion as defined for Future- bus+ through the LI (Live Insertion) pin. To implement live in- sertion the LI pin should be connected to the live insertion power connector. If this function is not supported the LI pin must be tied to the V CC pin. The DS3884A also provides power up/down glitch free protection during power sequenc- ing. The DS3884A has two types of power connections in addi- tion to the LI pin. They are the Logic V CC (VCC ) and the Quiet VCC (QVCC ). There are two VCC pins on the DS3884A that provide the supply voltage for the logic and control circuitry. Multiple connections are provided to reduce the effects of package inductance and thereby minimize switching noise. As these pins are common to the V CC bus internal to the de- vice, a voltage difference should never exist between these pins and the voltage difference between V CC and QV CC should never exceed±0.5V because of ESD circuitry. Addi- tionally, the ESD circuitry between the VCC pins and all other pins except for BTL I/O’s and LI pins requires that any volt- age on these pins should not exceed the voltage on V CC + 0.5V. There are three different types of ground pins on the DS3884A. They are the logic ground (GND), BTL grounds (B1GND–B6GND) and the Bandgap reference ground (QGND). All of these ground reference pins are isolated within the chip to minimize the effects of high current switch- ing transients. For optimum performance the QGND should be returned to the connector through a quiet channel that does not carry transient switching current. The GND and B1GND–B6GND should be connected to the nearest back- plane ground pin with the shortest possible path. Since many different grounding schemes could be imple- mented and ESD circuitry exist on the DS3884A, it is impor- tant to note that any voltage difference between ground pins, QGND, GND or B1GND–B6GND should not exceed ±5V in- cluding power up/down sequencing. Additional transceivers included in the Futurebus+ / BTL family are; the DS3883A BTL 9-bit Transceiver, and the DS3886A BTL 9-bit Latching Data Transceiver featuring edge triggered latches in the driver which may be bypassed during a fall-through mode and a transparent latch in the re- ceiver. DS3884A www.national.com7

Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com 44-Pin PQFP Order Number DS3884AVF DS3884A BTL Handshake Transceiver National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.