DS3883

DS3883A NSC | Alldatasheet

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n 9-bit Inverting BTL transceiver meets IEEE 1194.1 standard on Backplane Transceiver Logic (BTL) n Supports live insertion n Glitch free power-up/down protection n Typically less than 5 pF bus-port capacitance n Low bus-port voltage swing (typically 1V) at 80 mA n Open collector bus-port output allows Wired-OR n Controlled rise and fall time to reduce noise coupling n TTL compatible driver and control inputs n Built in bandgap reference with separate QVCC and QGND pins for precise receiver thresholds n Exceeds 2 kV ESD (Human Body Model) n Individual bus-port ground pins minimize ground bounce n Tight skew (1 ns typical) TRI-STATE® is a registered trademark of National Semiconductor Corporation. July 1998 DS3883A BTL 9-Bit Data Transceiver © 1999 National Semiconductor Corporation DS010719 www.national.com

See NS Package Number VF44B www.national.com 2

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage 6.5V Control Input Voltage 6.5V Driver Input and Receiver Output 5.5V Receiver Input Current ±15 mA Bus Termination Voltage 2.4V Power Dissipation at 25˚C PQFP (VF44B) 1.3W Derate PQFP Package (VF44B) 11.1 mW/˚C Storage Temperature Range −65˚C to +150˚C Lead Temperature (Soldering, 4 seconds) 260˚C Recommended Operating Conditions Min Max Units Supply Voltage, VCC 4.5 5.5 V Bus Termination Voltage (VT) 2.06 2.14 V Operating Free Air Temperature 0 70 ˚C TA = 0˚C to +70˚C, VCC = 5V ±10% Symbol Parameter Conditions Min Typ Max Units DRIVER AND CONTROL INPUT (CD, T/R , An) VIH Minimum Input High Voltage 2.0 V VIL Maximum Input Low Voltage 0.8 V II Input Leakage Current V IN = V CC = 5.5V 250 µA IIH Input High Current V IN = 2.4V, AN= CD = 0.5V, T/R= 2.4V 40 µA IIL Input Low Current V IN = 0.5V, AN= CD = 0.5V, T/R= 2.4V −100 µA VCL Input Diode Clamp Voltage I CLAMP = −12 mA −1.2 V DRIVER OUTPUT/RECEIVER INPUT (Bn) (Note 5) I OL = 80 mA IOFF Output Off Low Current An = 0.5V, T/R= 2.4V, Bn= 0.75V, CD= 0.5V −200 µA Output Off High Current An = 0.5V, T/R= 2.4V, Bn= 2.1V, CD= 0.5V 200 µA Output Off Low Current — An = 0.5V, T/R= CD = 2.4V, Bn= 0.75V −50 µA Chip Disabled Output Off Low Current — An = 0.5V, T/R= CD = 2.4V, Bn= 2.1V 50 µA Chip Disabled VTH Receiver Input Threshold T/R = CD = 0.5V 1.47 1.55 1.62 V VCLP Positive Clamp Voltage V CC = Max or 0V, IBn = 1 mA, CD = T/R = 0V 2.4 3.4 4.5 V An = 0V VCC = Max or 0V, IBn = 10 mA, CD = T/R = 0V 2.9 3.9 5.0 V An = 0V VCLN Negative Clamp Voltage I CLAMP = −12 mA, CD = T/R = 0.5V −1.2 V RECEIVER OUTPUT (An) VOH Voltage Output High Bn = 1.1V, T/R= CD = 0.5V, IOH = −2 mA 2.4 3.2 V VOL Voltage Output Low T/R = CD = 0.5V, Bn= 2.1V, IOL = 24 mA 0.35 0.5 V T/R = CD = 0.5V, Bn= 2.1V, IOL = 8m A 0.35 0.4 V IOZ TRI-STATE Leakage Current An = 2.4V, CD= 2.4V, T/R= 0.5V 10 µA An = 0.5V, CD=2.4V, T/R= 0.5V −10 µA IOS Output Short Circuit Current Bn= 1.1V, T/R= CD = 0.5V (Note 4) −40 −70 −100 mA SUPPLY CURRENT I CC Supply Current: Includes T/R = All An Inputs= 2.4V, CD= 0.5V 62 mA VCC ,Q VCC and LI CD = T/R = 0.5V, All Bn Inputs= 2.1V 53 mA ILI Live Insertion Current T/R = CD = An = 0.5V, Bn= Open, 2.2 mA VCC = QV CC = 5.5V T/R = All An= 2.4V, CD= 0.5V, Bn= Open 4.5 mA VCC = QV CC = 5.5V www.national.com3

Note 1:“Absolute Maximum Ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All input and/or output pins shall not exceed VCC + 0.5V and shall not exceed the absolute maximum rating at any time, including power-up and power-down. This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QVCC and VCC . There is a diode between each input and/or output to VCC which is forward biased when incorrect sequencing is applied. LI and Bn pins do not have power sequencing requirements with re- spect to VCC and QVCC . Note 3:All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. All typical values are specified under these conditions: VCC = 5V and TA = 25˚C, unless otherwise stated. Note 4:Only one output should be shorted at a time, and duration of the short should not exceed one second. Note 5:Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package. TA = 0˚C to +70˚C, VCC = 5V ±10% Symbol Parameter Conditions Min Typ Max Units DRIVER t PHL An to Bn Propagation Delay CD = 0V, T/ R= 3V 1 3.5 6 ns tPLH (Figure 1and Figure 2) 1 3.5 6 ns tPHL CD to Bn Enable Time T/R = An = 3V 369n s tPLH Disable Time ( Figure 1and Figure 3) 2.5 5 8 ns tPHL T/R to Bn Enable Time ( Figure 8and Figure 9) 9 13.5 18 ns tPLH Disable Time CD = 0V 2 6 10 ns tr Transition Time — Rise/Fall ( Figure 1and Figure 2) 1 2.5 4.5 ns tf 20% to 80% CD = 0V, T/R= 3V (Note 10) 1 2 4.5 ns SR Slew Rate is Calculated ( Figure 1and Figure 2) (Note 10) 0.5 V/ns from 1.3V to 1.8V CD = 0V T/R = 3V tSKEW An to Bn Skew (Same Package) (Note 7) 1 3.5 ns RECEIVER t PHL Bn to An CD = T/ R= 0V 247n s tPLH (Figure 4and Figure 5) 1.5 4.5 7.5 ns tPLZ CD to An Disable Time Bn = 2.1V, T/R= 0V 4 8 12 ns tPZL Enable Time ( Figure 6and Figure 7) 2.5 6 9 ns tPHZ Disable Time Bn = 1.1V, T/R= 0V 3 6.5 10 ns tPZH Enable Time ( Figure 6and Figure 7)2 6 1 0 n s tPLZ T/R to An Disable Time CD = 0V Bn = 2.1V 3 7 12 ns tPZL Enable Time ( Figure 8and Figure 9) 4 10 16 ns tPHZ Disable Time Bn = 1.1V, CD= 0V 2 6.5 10 ns tPZH Enable Time ( Figure 6and Figure 7)3 7 1 1 n s tSKEW Bn to An Skew (Same Package) (Note 7) 1 3.5 ns PARAMETERS NOT TESTED C output BTL Output Capacitance (Note 8) 5 pF tNR Noise Rejection (Note 9) 1 ns Note 6:Input waveforms shall have a rise/fall time of 3 ns. Propagation delays are measured with a single output switching. Note 7:tSKEW is an absolute value defined as differences seen in propagation delays between drivers in the same package with identical load conditions. Note 8:The parameter is tested using TDR techniques described in 1194.0 BTL backplane Design Guide. Note 9: This parameter is tested during device characterization. The measurement revealed that the part will reject 1 ns pulse widths. Note 10:Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster than 0.5 V/ns, measured between 1.3V and 1.8V (approximately20% to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5Ω tied to +2.1V DC. www.national.com 4

Pin Name Number Input/ Description of Pins Output A0–A8 9 I/O TTL TRI-STATE receiver output and driver input B0–B8 9 I/O BTL receiver input and driver output B0GND–B8GND 9 NA Parallel driver grounds reduce ground bounce due to high current switching of driver outputs. (Note 11) CD 1 I Chip Disable GND 2 NA Ground for switching circuits. (Note 11) LI 1 NA Power supply for live insertion. Boards that require live insertion should connect LI to the live insertion pin on the connector. (Note 12) NC 8 NA No Connect QGND 1 NA Ground for receiver input bandgap reference and non-switching circuits. (Note 11) QV CC 1N A V CC supply for bandgap reference and non-switching circuits. (Note 12) T/R 1 I Transmit/Receive — transmit (An to Bn), receive (Bn to An) VCC 2N A V CC supply for switching circuits. (Note 12) Note 11:The multiplicity of parallel ground paths reduces the effective inductance of bonding wires and leads, which then reduces the noise caused by transients on the ground path. The various ground pins can be tied together provided that the external ground has low inductance. (i.e., ground plane with power pins and many signal pins connected to the backplane ground.) If the external ground floats considerably during transients, precautionary steps should be taken to prevent QGND from moving with reference to the backplane ground. The receiver threshold should have the same ground reference as the signal coming from the backplane. A volt- age offset between their grounds will degrade the noise margin. Note 12:The same considerations for ground are used for VCC in reducing lead inductance (see (Note 11) ). QVCC and VCC should be tied together externally. If live insertion is not supported, the LI pin can be tied together with QVCC and VCC . CD T/R An Bn (BTL) HXZ H LLL H LLH L LHH L LHL H X = High or low logic state Z = High impedance state L = Low state H = High state Package Thermal Characteristics Linear Feet per Minute Air Flow (LFPM) θJA (˚C/W) 44-Pin PQFP 08 2 225 68 500 60 900 53 Note 13: The above values are typical values and are different from the Ab- solute Maximum Rating values, which include guardbands. www.national.com5

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Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Note:All dimensions in millimeters 44-Lead Plastic Quad Flatpak Order Number DS3883AVF DS3883A BTL 9-Bit Data Transceiver National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.