DS3882_10 MAXIM | Alldatasheet
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♦ Dual-Channel CCFL Controllers for Backlighting LCD Panels and Instrument Clusters in Automotive Navigation/Infotainment Applications ♦ Minimal External Components Required ♦ I 2C Interface ♦ Per-Channel Lamp-Fault Monitoring for Lamp- Open, Lamp-Overcurrent, Failure to Strike, and Overvoltage Conditions ♦ Status Register Reports Fault Conditions ♦ Accurate (±5%) Independent On-Board Oscillators for Lamp Frequency (40kHz to 100kHz) and DPWM Burst-Dimming Frequency (22.5Hz to 440Hz) ♦ Lamp and DPWM Frequencies can be Synchronized with External Sources to Reduce Visual LCD Artifacts in Video Applications ♦ Optional Spread-Spectrum Lamp Clock Reduces EMI ♦ Lamp Frequency can be Stepped Up or Down to Move EMI Spurs Out of Band ♦ Lamp Current Overdrive Mode with Automatic Turn-Off Quickly Warms Lamp in Cold Temperatures ♦ Analog and Digital Brightness Control ♦ 300:1 Dimming Range Possible Using the Digital Brightness Control Option ♦ Programmable Soft-Start Minimizes Audible Transformer Noise ♦ On-Board Nonvolatile (NV) Memory Allows Device Customization ♦ 8-Byte NV User Memory for Storage of Serial Numbers and Date Codes ♦ Low-Power Standby Mode ♦ 4.75V to 5.25V Single-Supply Operation ♦ Temperature Range: -40°C to +105°C ♦ 28-Pin TSSOP Package DS3882 Dual-Channel Automotive CCFL Controller OVD2 LCM2 GB2 GA2SCL SDA FAULT TOP VIEW VCC PDN LCOBRIGHT LOSC
218 GNDPSYNC
209 STEPPOSC
1910 N.C.A1
1811 OVD1GND_S
1712 LCM1SVML
1613 GB1SVMH
1514 GA1VCC
19-5666; Rev 2; 12/10 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel.
Ordering Information
Typical Operating Circuit appears at end of data sheet. PART TEMP RANGE PIN-PACKAGE DS3882E+C -40°C to +105°C 28 TSSOP DS3882E+T&R/C -40°C to +105°C 28 TSSOP
Dual-Channel Automotive CCFL Controller ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +105°C) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on VCC, SDA, and Voltage Range on Leads Other than VCC, SDA, and Continuous Power Dissipation (TA = +70°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC (Note 1) 4.75 5.25 V Input Logic 1 V IH 2.0 VCC + 0.3 V Input Logic 0 V IL -0.3 1.0 V SVML/H Voltage Range V SVM -0.3 VCC + 0.3 V BRIGHT Voltage Range V BRIGHT -0.3 VCC + 0.3 V LCM Voltage Range V LCM (Note 2) -0.3 VCC + 0.3 V OVD Voltage Range V OVD (Note 2) -0.3 VCC + 0.3 V Gate-Driver Output Charge Loading QG 20 nC
ELECTRICAL CHARACTERISTICS
(VCC = +4.75V to +5.25V, TA = -40°C to +105°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current I CC G A , G B l oad ed w i th 600p F, 2 channel s acti ve 12 mA Input Leakage (Digital Pins) I L -1.0 +1.0 µA Power-Down Current I PDN 2m A Output Leakage (SDA, FAULT)I LO High impedance -1.0 +1.0 µA Low-Level Output Voltage (LSYNC, PSYNC) VOL IOL = 4mA 0.4 V VOL1 IOL1 = 3mA 0.4Low-Level Output Voltage (SDA, FAULT) VOL2 IOL2 = 6mA 0.6 V Low-Level Output Voltage (GA, GB) VOL3 IOL3 = 4mA 0.4 V High-Level Output Voltage (LSYNC, PSYNC) VOH IOH = -1mA 2.4 V
Dual-Channel Automotive CCFL Controller ELECTRICAL CHARACTERISTICS (continued) (VCC = +4.75V to +5.25V, TA = -40°C to +105°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS High-Level Output Voltage (GA, GB) VOH1 IOH1 = -1mA VCC - 0.4 V UVLO Threshold: VCC Rising V UVLOR 4.3 V UVLO Threshold: VCC Falling V UVLOF 3.7 V UVLO Hysteresis V UVLOH 200 mV SVML/H Threshold: Rising V SVMR 2.03 2.08 2.15 V SVML/H Threshold: Falling V SVMF 1.95 2.02 2.07 V LCM and OVD DC Bias Voltage V DCB 1.1 V LCM and OVD Input Resistance R DCB 50 k Ω Lamp Off Threshold V LOT (Note 3) 0.22 0.25 0.28 V Lamp Over Current V LOC (Note 3) 2.2 2.5 2.8 V Lamp Regulation Threshold V LRT (Notes 3, 4) 0.9 1.0 1.1 V OVD Threshold V OVDT (Note 3) 0.9 1.0 1.1 V Lamp Frequency Source Frequency Range fLFS:OSC 40 100 kHz Lamp Frequency Source Frequency Tolerance fLFS:TOL LOSC resistor ±2% over temperature -5 +5 % Lamp Frequency Receiver Frequency Range fLFR:OSC 40 100 kHz Lamp Frequency Receiver Duty Cycle fLFR:DUTY 40 60 % DPWM Source (Resistor) Frequency Range fDSR:OSC 22.5 440.0 Hz DPWM Source (Resistor) Frequency Tolerance fDSR:TOL POSC resistor ±2% over temperature -5 +5 % DPWM Source (Ext. Clk) Frequency Range fDSE:OSC 22.5 440.0 Hz DPWM Source (Ext. Clk) Duty Cycle fDFE:DUTY 40 60 % DPWM Receiver Min Pulse Width tDR:MIN (Note 5) 25 µs BRIGHT Voltage: Minimum Brightness VBMIN 0.5 V BRIGHT Voltage: Maximum Brightness VBMAX 2.0 V Gate Driver Output Rise/Fall Time t R / tF CL = 600pF 100 ns GAn and GBn Duty Cycle (Note 6) 44 %
Dual-Channel Automotive CCFL Controller Note 1: All voltages are referenced to ground unless otherwise noted. Currents into the IC are positive, out of the IC negative. Note 2: During fault conditions, the AC-coupled feedback values are allowed to be below the absolute max rating of the LCM or OVD pin for up to 1 second. Note 3: Voltage with respect to VDCB. Note 4: Lamp overdrive and analog dimming (based on reduction of lamp current) are disabled. Note 5: This is the minimum pulse width guaranteed to generate an output burst, which generates the DS3882’s minimum burst duty cycle. This duty cycle may be greater than the duty cycle of the PSYNC input. Once the duty cycle of the PSYNC input is greater than the DS3882’s minimum duty cycle, the output’s duty cycle tracks the PSYNC’s duty cycle. Leaving PSYNC low (0% duty cycle) disables the GAn and GBn outputs in DPWM receiver mode. Note 6: This is the maximum lamp frequency duty cycle that is generated at any of the GAn or GBn outputs with spread-spectrum modulation disabled. Note 7: I 2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I 2C stan- dard-mode timing. Note 8: After this period, the first clock pulse can be generated. Note 9: CB—total capacitance allowed on one bus line in picofarads. Note 10: EEPROM write time applies to all the EEPROM memory. EEPROM write begins after a stop condition occurs. Note 11: Guaranteed by design. I2C AC ELECTRICAL CHARACTERISTICS (See Figure 9) (VCC = +4.75V to +5.25V, TA = -40°C to +105°C, timing referenced to V IL(MAX) and VIH(MIN).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency f SCL (Note 7) 0 400 kHz Bus Free Time Between Stop and Start Conditions tBUF 1.3 µs Hold Time (Repeated) Start Condition tHD:STA (Note 8) 0.6 µs Low Period of SCL t LOW 1.3 µs High Period of SCL t HIGH 0.6 µs Data Hold Time t HD:DAT 0 0.9 µs Data Setup Time t SU:DAT 100 ns Start Setup Time t SU:STA 0.6 µs SDA and SCL Rise Time t R (Note 9) 20+ 0.1CB 300 ns SDA and SCL Fall Time t F (Note 9) 20+ 0.1CB 300 ns Stop Setup Time t SU:STO 0.6 µs SDA and SCL Capacitive Loading CB (Note 9) 400 pF EEPROM Write Time t W (Note 10) 20 30 ms NONVOLATILE MEMORY CHARACTERISTICS (VCC = +4.75V to 5.25V) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM Write Cycles +85°C (Note 11) 30,000
Dual-Channel Automotive CCFL Controller ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3882 toc01 SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 4.0 4.75 5.25 DPWM = 10% DPWM = 50% DPWM = 100% SVML< 2V fLF:OSC = 64kHzGATE QC = 3.5nC ACTIVE SUPPLY CURRENT vs. TEMPERATURE DS3882 toc02 TEMPERATURE (°C) SUPPLY CURRENT (mA) 32.5 5.7 5.9 6.1 6.3 6.5 6.7 6.9 7.1 7.3 7.5 5.5 -40.0 105 VCC = 4.75V VCC = 5.0V VCC = 5.25V DPWM = 100% fLF:OSC = 64kHz GATE QC = 3.5nC INTERNAL FREQUENCY CHANGE vs. TEMPERATURE DS3882 toc03 TEMPERATURE (°C) FREQUENCY CHANGE (%) 32.5 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 1.0 -1.0 -40.0 10 5 DPWM FREQUENCY LAMP FREQUENCY TYPICAL OPERATION AT 11V DS3882 toc0410μs 5.0V GA 10μs 5.0V GB 10μs 2.00V LCM 10μs 2.00V OVD TYPICAL OPERATION AT 13V DS3882 toc0510μs 5.0V GA 10μs 5.0V GB 10μs 2.00V LCM 10μs 2.00V OVD TYPICAL OPERATION AT 16V DS3882 toc0610μs 5.0V GA 10μs 5.0V GB 10μs 2.00V LCM 10μs 2.00V OVD TYPICAL STARTUP WITH SVM DS3882 toc072ms 5.0V SVML 2ms 5.0V GB 2ms 2.00V LCM 2ms 2.00V OVD BURST DIMMING AT 150Hz AND 10% DS3882 toc08 1ms 5.0V GA 1ms 5.0V GB 1ms 2.00V LCM 1ms 2.00V OVD BURST DIMMING AT 150Hz AND 50% DS3882 toc09 1ms 5.0V GA 1ms 5.0V GB 1ms 2.00V LCM 1ms 2.00V OVD Typical Operating Characteristics (VCC = 5.0V, TA = +25°C, unless otherwise noted.)
Dual-Channel Automotive CCFL Controller Typical Operating Characteristics (continued) (VCC = 5.0V, TA = +25°C, unless otherwise noted.) SOFT-START AT VINV = 16V DS3882 toc1050μs 5.0V GA 50μs 5.0V GB 50μs 2.00V LCM 50μs 2.00V OVD LAMP STRIKE—EXPANDED VIEW DS3882 toc111ms 5.0V GA 1ms 5.0V GB 1ms 2.00V LCM 1ms 2.00V OVD AUTO RETRY DISABLED DS3882 toc120.5s 5.0V GA 0.5s 5.0V GB 0.5s 2.00V LCM 0.5s
2.00 OVD
STAGGERED BURST DIMMING START DS3882 toc130.2ms 2.00V GA1 0.2ms 2.00V GA2 AUTORETRY DISABLED DS3882 toc140.1s 5.0V GA 0.1s 5.0V GB 0.1s 2.00V LCM 0.1s 2.00V OVD LAMP OPENED
Dual-Channel Automotive CCFL Controller Pin Description PINS BY CHANNEL (n) FUNCTIONNAME CH 1 CH 2 GAn 15 25 MOSFET A Gate Drive. Connect directly to logic-level mode n-channel MOSFET. Leave open if channel is unused. GBn 16 26 MOSFET B Gate Drive. Connect directly to logic-level mode n-channel MOSFET. Leave open if channel is unused. LCMn 17 27 Lamp Current Monitor Input. Lamp current is monitored by a resistor placed in series with the low-voltage side of the lamp. Leave open if channel is unused. OVDn 18 28 Overvoltage Detection. Lamp voltage is monitored by a capacitor divider placed on the high-voltage side of the transformer. Leave open if channel is unused. NAME PIN FUNCTION FAULT 1 Active-Low Fault Output. This open-drain pin requires external pullup resistor to realize high logic levels. A0 2 Address Select Input. Determines I 2C slave address. SDA 3 Serial-Data Input/Output. I2C bidirectional data pin, which requires a pullup resistor to realize high logic levels. SCL 4 Serial Clock Input. I 2C clock input. LSYNC 5 Lamp Frequency Input/Output. This pin is the input for an externally sourced lamp frequency when the DS3882 is configured as a lamp frequency receiver. If the DS3882 is configured as a lamp frequency source (i.e., the lamp frequency is generated internally), the frequency is output on this pin for use by other lamp frequency receiver DS3882s. LOSC 6 Lamp Oscillator Resistor Adjust. A resistor to ground on this pin sets the frequency of the internal lamp oscillator. BRIGHT 7 Analog Brightness Control Input. Used to control the DPWM dimming feature. Ground if unused. PSYNC 8 DPWM Input/Output. This pin is the input for an externally generated DPWM signal when the DS3882 is configured as a DPWM receiver. If the DS3882 is configured as a DPWM source (i.e., the DPWM signal is generated internally), the DPWM signal is output on this pin for use by other DPWM receiver DS3882s.
Dual-Channel Automotive CCFL Controller Pin Description (continued) NAME PIN FUNCTION POSC 9 DPWM Oscillator Resistor Adjust. A resistor to ground on this lead sets the frequency of the DPWM oscillator. This lead can optionally accept a 22.5Hz to 440Hz clock that will become the source timing of the internal DPWM signal. A1 10 Address Select Input. Determines I 2C slave address. GND_S 11 I 2C Interface Ground Connection. GND_S must be at the same potential as GND. SVML 12 Low-Supply Voltage Monitor Input. Used to monitor the inverter voltage for undervoltage conditions. SVMH 13 High-Supply Voltage Monitor Input. Used to monitor the inverter voltage for overvoltage conditions. VCC 14, 24 Power-Supply Connections. Both pins must be connected. N.C. 19 No Connection. Do not connect any signal to this pin. STEP 20 Lamp Frequency Step Input. This active-high digital input moves the lamp oscillator frequency up or down by 1%, 2%, 3%, or 4% as configured in the EMIC register. This pin is logically ORed with the STEPE bit in the EMIC register. GND 21 Ground Connection LCO 22 Lamp Current Overdrive Enable Input. A high digital level at this input enables the lamp current overdrive circuit. The amount of overdrive current is configured by the LCOC register. When this input is low, the lamp current is set to its nominal level. This pin is logically ORed with the LCOE bit in the LCOC register. PDN 23 Lamp On/Off Control Input. A low digital level at this input turns the lamp on. A high digital level turns the lamps off, clears the fault logic, and places the device into the power-down mode. The high-to-low transition on this input issues a controller reset, which clears the fault logic and reinitiates a lamp strike. This pin is logically ORed with the PDNE bit in the CR2 register.
8 BYTE USER MEMORY
Figure 1. Functional Diagram
duces near-sinusoidal waveforms. which maximizes the lamp’s brightness and lifetime. cussed on the following pages of this data sheet. configuration/status registers as well as user memory. gramming, contact the factory.
512 X LAMP FREQUENCY
64 LAMP CYCLE
Figure 2. Per Channel Logic Diagram
The DS3882 incorporates SRAM-shadowed EEPROM memory locations for all memory that needs to be retained during power cycling. At power-up, SEEB (bit 7 of the BLC register) is low which causes the shadowed locations to act as ordinary EEPROM. Setting SEEB high disables the EEPROM write function and causes the shadowed locations to function as ordinary SRAM cells. This allows an infinite number of write cycles with- out causing EEPROM damage and also eliminates the EEPROM write time, t W from the write cycle. Because memory changes made when SEEB is set high are not written to EEPROM, these changes are not retained through power cycles, and the power-up EEPROM values are the last values written with SEEB low. Channel Phasing The lamp-frequency MOSFET gate turn-on times are out of phase between the two channels during the burst period. This reduces the inrush current that would result from all lamps switching simultaneously, and hence eases the design requirements for the DC sup- ply. It is important to note that it is the lamp-frequency signals that are phased, not the DPWM (burst) signals. Lamp Dimming Control The DS3882 provides two independent methods of lamp dimming that can be combined to achieve a dim- ming ratio of 300:1 or greater. The first method is “burst” dimming, which uses a digital pulse-width-mod- ulated (DPWM) signal (22.5Hz to 440Hz) to control the lamp brightness. The second is “analog” dimming, which is accomplished by adjusting the lamp current. Burst dimming provides 128 linearly spaced brightness steps. Analog dimming provides smaller substeps that allow incremental brightness changes between burst dimming steps. This ability is especially useful for low- brightness dimming changes, where using burst dim- ming alone would cause visible brightness step changes. Analog dimming also allows the brightness to be reduced below the minimum burst dimming level, which provides for the maximum dimming range. Burst dimming can be controlled using a user-supplied analog voltage on the BRIGHT pin or through the I interface. Analog dimming can only be controlled through the I 2C interface. Therefore, for applications that require the complete dimming range and resolution capa- bility of the DS3882, I 2C dimming control must be used. Burst Dimming Burst dimming increases/decreases the brightness by adjusting (i.e., modulating) the duty cycle of the DPWM signal. During the high period of the DPWM cycle, the lamps are driven at the selected lamp frequency (40kHz to 100kHz) as shown in Figure 6. This part of the cycle is called the “burst” period because of the lamp frequency burst that occurs during this time. During the low period of the DPWM cycle, the controller disables the MOSFET gate drivers so the lamps are not driven. This causes the current to stop flowing in the lamps, but the time is short enough to keep the lamps from de-ionizing. The DS3882 can generate its own DPWM signal inter- nally (set DPSS = 0 in CR1), which can then be sourced to other DS3882s if required, or the DPWM sig- nal can be supplied from an external source (set DPSS = 1 in CR1). To generate the DPWM signal internally, the DS3882 requires a clock (referred to as the dim- ming clock) to set the DPWM frequency. The user can supply the dimming clock by setting POSCS = 1 in CR1 and applying an external 22.5Hz to 440Hz signal at the POSC pin, or the dimming clock can be generated by the DS3882’s internal oscillator (set POSCS = 0 in CR1), in which case the frequency is set by an external resistor at the POSC pin. These two dimming clock options are shown in Figure 3. Regardless of whether the dimming clock is generated internally or sourced externally, the POSCR0 and POSCR1 bits in CR2 must be set to match the desired dimming clock frequency. The internally generated DPWM signal can be provided at the PSYNC I/O pin (set RGSO = 0 in CR1) for sourc- ing to other DS3882s, if any, in the circuit. This allows all DS3882s in the system to be synchronized to the same DPWM signal. A DS3882 that is generating the DPWM signal for other DS3882s in the system is referred to as the DPWM source. When bringing in an externally generated DPWM signal, either from another DS3882 acting as a DPWM source or from some other user-provided source, it is input into the PSYNC I/O pin of the DS3882, and the receiving DS3882 is referred to a DPWM receiver. In this mode, the BRIGHT and POSC inputs are disabled and should be grounded (see Figure 5). When the DPWM signal is generated internally, its duty cycle (and, thus, the lamp brightness) is controlled either by a user-supplied analog voltage at the BRIGHT input or through the I 2C interface by varying the 7-bit PWM code in the BPWM register. When using the BRIGHT pin to control burst dimming, a voltage of less than 0.5V causes the DS3882 to operate with the mini- mum burst duty cycle, providing the lowest brightness setting, while any voltage greater than 2.0V causes a 100% burst duty cycle (i.e., lamps always being dri- ven), which provides the maximum brightness. For voltages between 0.5V and 2V, the duty cycle varies linearly between the minimum and 100%. Writing a DS3882 Dual-Channel Automotive CCFL Controller
Figure 5. Frequency Configuration Options for Designs Using Multiple DS3882s
chronization for all DS3882s in the system. result from current surges in the transformer primary. duty cycles range from 0% to 19% in ~3% increments. repeats twice to make up the 16 soft-start lamp cycles. A 16 LAMP CYCLE PERIOD RESULTS IN A LINEAR RAMP IN LAMP CURRENT. Figure 6. Digital PWM Dimming and Soft-Start
where K = 1600kΩ • kHz for lamp frequency calculations. Detailed Register Descriptions section. parators (see Figure 7), both having 2V thresholds. circuitry to operate or to drive the external MOSFETs. disabled until it is reset by a user or host control event. Figure 7. Setting the SVM Threshold Voltage
Figure 8 shows a flowchart of how the DS3882 controls and monitors each lamp. The steps are as follows: 1) Supply Check—The lamps do not turn on unless the DS3882 supply voltage is above 4.3V and the volt- age at the supply voltage monitors, SVML and SVMH, are respectively above 2.0V and below 2.0V. 2) Strike Lamp—When both the DS3882 and the DC inverter supplies are at acceptable levels, the DS3882 attempts to strike each enabled lamp. The DS3882 slowly ramps up the MOSFET gate duty cycle until the lamp strikes. The controller detects that the lamp has struck by detecting current flow in the lamp, detected by the LCMn pin. If during the strike ramp, the maximum allowable voltage is reached on the OVDn pin, the controller stops increasing the MOSFET gate duty cycle to keep from overstressing the system. The DS3882 goes into a fault handling state (step 4) if the lamp has not struck after the timeout period as defined by the LST0 and LST1 control bits in the SSP1 register. If an overvolt- age event is detected during the strike attempt, the DS3882 disables the MOSFET gate drivers and go into the fault handling state. 3) Run Lamp—Once the lamp is struck, the DS3882 adjusts the MOSFET gate duty cycle to optimize the lamp current. The gate duty cycle is always con- strained to keep the system from exceeding the maximum allowable lamp voltage. The lamp current sampling rate is user-selectable using the LSR0 and LSR1 bits in CR2. If lamp current ever drops below the lamp out reference point for the period as defined by the LST0 and LST1 control bits in the SSP1 register, then the lamp is considered extinguished. In this case, the MOSFET gate drivers are disabled and the device moves to the fault handling stage. 4) Fault Handling—During fault handling, the DS3882 performs an optional (user-selectable) automatic retry to attempt to clear all faults except a lamp over- current. The automatic retry makes 14 additional attempts to rectify the fault before declaring the channel in a fault state and permanently disabling the channel. Between each of the 14 attempts, the controller waits 1024 lamp cycles. In the case of a lamp overcurrent, the DS3882 instantaneously declares the channel to be in a fault state and per- manently disables the channel. The DS3882 can be configured to disable all channels if one or more channels enter a fault state or it can be configured to disable only the channel where the fault occurred. Once a fault state is entered, the channel remains in that state until one of the following occurs:
- V CC drops below the UVLO threshold.
- The SVML or SVMH thresholds are crossed.
- The PDN pin goes high.
- The PDNE software bit is written to a logic 1.
- The channel is disabled by the CH1D or CH2D control bit. Dual-Channel Automotive CCFL Controller
Figure 8. Fault-Handling Flowchart
lation rate (through FS0/1/2) for the application. in brightness when the overdrive is no longer needed. 21 minutes (if a 50kHz lamp frequency is used). The DS3882’s register map is shown in Table 1. Table 1. Register Map Note 1: E0h–E3h are SRAM locations, and F0h–FFh are SRAM-shadowed EEPROM. Note 2: Altering DS3882 configuration during active CCFL operation can cause serious adverse effects. Note 3: The BPWM, BLC, and LCOC registers control both channels of the DS3882.
Table 2. Status Register 1 (SR1) [SRAM, E0h]
0 R 0 FAULT_RT
condition. This bit is cleared when read, regardless of the current state of fault. 2 R 0 STO_L Lamp Strike Timeout—Latched. A latched bit that is set when the lamp fails to strike. This bit is cleared when read. at least 64 lamp cycles. This bit is cleared when read. detected. This bit is cleared when read. Note 1: Writing to this register has no effect on it. Note 2: See Figure 8 for more details on how the status bits are set.
- VCC drops below the UVLO threshold
- the SVML or SVMH thresholds are crossed
- the PDN hardware pin goes high
- the PDNE software bit is written to a logic 1
- the channel is disabled by the CH1D control bit
Table 3. Status Register 2 (SR2) [SRAM, E1h] condition. This bit is cleared when read regardless of the current state of fault. 2 R 0 STO_L Lamp Strike Time Out—Latched. A latched bit that is set when the lamp fails to strike. This bit is cleared when read. for at least 64 lamp cycles. This bit is cleared when read. detected. This bit is cleared when read. 6 R 0 RSVD Reserved. Could be either 0 or 1 when read. 7 R 0 RSVD Reserved. Could be either 0 or 1 when read. Note 1: Writing to this register has no effect on it. Note 2: See Figure 8 for more details on how the status bits are set.
- VCC drops below the UVLO threshold
- the SVML or SVMH thresholds are crossed
- the PDN hardware pin goes high
- the PDNE software bit is written to a logic 1
- the channel is disabled by the CH2D control bit
Table 4. Brightness Lamp Current Register (BLC) [SRAM, E3h]
0 R/W 0 LC0
1 R/W 0 LC1
2 R/W 0 LC2
3 R/W 0 LC3
4 R/W 0 LC4
bits are used for fine adjustment of the lamp brightness.
5 R/W 0 CH1D
6 R/W 0 CH2D
Channel 2 Disable. Useful for dimming in two lamp applications.
7 R/W 0 SEEB
Dual-Channel Automotive CCFL Controller Table 5a. Soft-Start Protocol Registers (SSPx) [Shadowed-EEPROM, F0h, F1h, F2h, F3h] MSB LSBSSP# ADDR FACTORY DEFAULT 7 654 3 2 1 0 SSP1 F0h 21h LST1 Lamp Cycles 3 and 4 LST0 Lamp Cycles 1 and 2 SSP2 F1h 43h RSVD Lamp Cycles 7 and 8 RSVD Lamp Cycles 5 and 6 SSP3 F2h 65h RSVD Lamp Cycles 11 and 12 RSVD Lamp Cycles 9 and 10 SSP4 F3h 77h RSVD Lamp Cycles 15 and 16 RSVD Lamp Cycles 13 and 14 Table 5b. MOSFET Duty Cycle (MDC)⎯Codes for Soft-Start Settings BIT R/W NAME FUNCTION
0 R/W MDC0
MDC0/1/2: These bits determine a MOSFET duty cycle that will repeat twice in the 16 lamp cycle soft-start.
1 R/W MDC1
MDC CODE MOSFET DUTY CYCLE MDC CODE MOSFET DUTY CYCLE 0h Fixed at 0% 4h Fixed at 13%2 R/W MDC2 1h Fixed at 3% 5h Fixed at 16% 2h Fixed at 6% 6h Fixed at 19% 3h Fixed at 9% 7h Most Recent Value3 R/W LST0 / RSVD 4 R/W MDC0 LST0/1: These bits select strike and lamp-out timeout. LST0 and LST1 control fault behavior for all lamps.
5 R/W MDC1 LST1 LST0 STRIKE AND LAMP-OUT TIMEOUT
(LAMP FREQUENCY CYCLES) EXAMPLE TIMEOUT IF LAMP FREQUENCY IS 50kHz 0 0 32,768 0.66 Seconds6 R/W MDC2 0 1 65,536 1.31 Seconds 1 0 98,304 1.97 Seconds7 R/W LST1 / RSVD 1 1 Reserved —
Table 6. Control Register 1 (CR1) [Shadowed-EEPROM, F4h]
0 R/W 0 LOCE
0 = Lamp overcurrent detection disabled. 1 = Lamp overcurrent detection enabled.
1 R/W 0 POSCS
1 = POSC input is a 22.5Hz to 440Hz clock.
2 R/W 0 LFSS
0 = Lamp frequency generated internally and sourced from the LSYNC output. 1 = Lamp frequency generated externally and supplied to the LSYNC input.
3 R/W 0 DPSS
0 = DPWM signal generated internally and sourced from the PSYNC output. 1 = DPWM signal generated externally and supplied to the PSYNC input.
4 R/W 0 RGSO
0 = Source DPWM at the PSYNC output. 1 = Source internal ramp generator at the PSYNC output.
5 R/W 0 ARD
0 = Autoretry function enabled. 1 = Autoretry function disabled.
6 R/W 0 FRS
0 = Disable only the malfunctioning channel. 1 = Disable both channels upon fault detection on any channel.
7 R/W 0 DPD
Table 7. Control Register 2 (CR2) [Shadowed-EEPROM, F5h]
0 R/W 0 UMWP
1 R/W 0 POSCR0
2 R/W 0 POSCR1
Lamp Sample Rate Select. Determines the feedback sample rate of the LCM inputs.
3 R/W 1 LSR0
5 — 0 RSVD Reserved. This bit should be set to zero. 6 — 0 RSVD Reserved. This bit should be set to zero.
7 R/W 0 PDNE
Table 8. EMI Control Register (EMIC) [Shadowed-EEPROM, F6h]
2 R/W 0 SSM
1 = Pseudorandom modulation. 3 ⎯⎯ RSVD Reserved. This bit should be set to zero.
4 R/W 0 STEPE
Lamp Frequency Step Enable. Logically ORed with the Step Invoked. 0 = Lamp operates at nominal frequency.
5 R/W 0 FS0
Table 9. Lamp Current Overdrive Control Register (LCOC) [Shadowed-EEPROM, F7h]
3 R/W 0 LCOE
Lamp Current Overdrive Enable. Logically ORed with the LCO pin. 0 = Lamp operated with nominal current setting.
4 R/W 0 TO0
5 R/W 0 TO1
6 R/W 0 TO2
7 R/W 0 TO3
clock pulses, start, and stop conditions. master to initiate a new data transfer with a slave. shifted into the device during the rising edge of the SCL. forms a NACK by transmitting a one during the 9th bit. the device is not receiving data. acknowledgement is read using the bit-read definition. NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN). Figure 9. I2C Timing Diagram
memory location where the slave is to store the data. all byte write operations. See Figure 11 for more detail. the stop condition to write the contents to EEPROM. elapse before attempting to write again to the DS3882. are performed at room temperature. Figure 10. DS3882’s Slave Address Byte
28% to 35% duty cycle during steady state operation. open-circuit voltage that is used to strike the lamp. inverter supply, 438mm x 2.2mm lamp design. available in 8-pin SO packages. 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. Figure 11. I2C Communications Examples
Table 10. Transformer Specifications (as Used in the Typical Operating Circuit) Note 1: Primary should be Bifilar wound with center tap connection. Note 2: Turns ratio is defined as secondary winding divided by the sum of both primary windings. Table 11. Resistor and Capacitor Selection Guide 105kΩ 1 — See the Setting the SVM Threshold Voltage section. Configuration section to determine value. Configuration section to determine value. R7, R8 1/Chan 140 Ω 1 — See the Setting the RMS Lamp Current section. for V D C B to r each i ts nor m al op er ati ng l evel . C2 1/Chan 10pF 5 ±1000ppm/°C 2kV to 4kV breakdown voltage required. for V D C B to r each i ts nor m al op er ati ng l evel . C7 2/DS3882 0.1µF 10 X7R Place close to V CC and GND on DS3882.
Dual-Channel Automotive CCFL Controller INVERTER SUPPLY VOLTAGE (VINV) (8V TO 16V) GA1 LAMP CURRENT MONITOR CCFL LAMP GB1 OVD1 VCC VCCVCC VCC BRIGHT SVMH LAMP BRIGHTNESS TRANSFORMERDUAL POWER MOSFET DEVICE SUPPLY VOLTAGE (5V ±5%) OVERVOLTAGE DETECTION LCM1 GND LAMP FREQUENCY INPUT/OUTPUT LSYNC SCL SDA I2C CONFIGURATION AND CONTROL PORT FAULT PSYNCDPWM SIGNAL INPUT/OUTPUT LOSC POSC LCO PDNLAMP ON/OFF LAMP CURRENT OVERDRIVE ENABLE SVMLA0 HARDWARE CONTROL STEP LAMP FREQUENCY STEP GND_S R1 R2 R9 R10 R11 R3 R4 R5 R6 GA2 LAMP CURRENT MONITOR CCFL LAMP GB2 OVD2 TRANSFORMERDUAL POWER MOSFET OVERVOLTAGE DETECTION LCM2 DS3882 Typical Operating Circuit Power-Supply Decoupling To achieve best results, it is highly recommended that a decoupling capacitor is used on the IC power-supply pin. Typical values of decoupling capacitors are 0.01µF or 0.1µF. Use a high-quality, ceramic, surface- mount capacitor, and mount it as close as possible to the V CC and GND pins of the IC to minimize lead inductance. Chip Information SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages . Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
28 TSSOP
(173 mils) U28+2 21-0066 90-0171
Dual-Channel Automotive CCFL Controller Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Maxim Integrated Products, Inc.
Revision History
0 3/06 Initial release — 1 8/07 Updated Table 5b to change bit 7 LST[1:0] at 1:1 from 131,072 lamp frequency cycles to reserved 21 2 12/10 Updated the Ordering Information table part numbers; added the continuous power dissipation numbers for a single-layer board and the lead and soldering temperature information to the Absolute Maximum Ratings section; added the Package Information table 1, 2, 30