DS3881

DS3881 MAXIM | Alldatasheet

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Technical content

Features

o Single-Channel CCFL Controller for Backlighting LCD Panels and Instrument Clusters in Automotive Navigation/Infotainment Applications o Minimal External Components Required o I 2C Interface o Per-Channel Lamp-Fault Monitoring for Lamp- Open, Lamp-Overcurrent, Failure to Strike, and Overvoltage Conditions o Status Register Reports Fault Conditions o Accurate (±5%) Independent On-Board Oscillators for Lamp Frequency (40kHz to 100kHz) and DPWM Burst-Dimming Frequency (22.5Hz to 440Hz) o Lamp and DPWM Frequencies can be Synchronized with External Sources to Reduce Visual LCD Artifacts in Video Applications o Spread-Spectrum Lamp Clock Reduces EMI o Lamp Frequency can be Stepped Up or Down to Move EMI Spurs Out of Band o Lamp Current Overdrive Mode with Automatic Turn-Off Quickly Warms Lamp in Cold Temperatures o Analog or Digital Brightness Control o 300:1 Dimming Range Possible Using the Digital Brightness Control Option o Programmable Soft-Start Minimizes Audible Transformer Noise o On-Board Nonvolatile (NV) Memory Allows Device Customization o 8-Byte NV User Memory for Storage of Serial Numbers and Date Codes o Low-Power Standby Mode o 4.75V to 5.25V Single-Supply Operation o Temperature Range: -40°C to +105°C o 24-Pin TSSOP Package DS3881 Single-Channel Automotive CCFL Controller GB1 GA1SCL SDA A0 FAULT TOP VIEW VCC PDN LCOBRIGHT LOSC GNDPSYNC STEPPOSC N.C.A1 OVD1GND_S LCM1SVML 13SVMH VCC LSYNC TSSOP DS3881 Pin Configuration Rev 0; 3/06 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. +Denotes lead-free package.

Ordering Information

Typical Operating Circuit appears at end of data sheet. PART TEMP RANGE PIN-PACKAGE DS3881E+ -40°C to +105°C 24 TSSOP (173 mils) DS3881E+T&R -40°C to +105°C 24 TSSOP (173 mils) *Purchase of I 2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips.

Single-Channel Automotive CCFL Controller ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +105°C) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on VCC, SDA, and Voltage Range on Leads Other than VCC, SDA, and PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC (Note 1) 4.75 5.25 V Input Logic 1 V IH 2.0 VCC + 0.3 V Input Logic 0 V IL -0.3 1.0 V SVML/H Voltage Range V SVM -0.3 VCC + 0.3 V BRIGHT Voltage Range VBRIGHT -0.3 VCC + 0.3 V LCM Voltage Range V LCM (Note 2) -0.3 VCC + 0.3 V OVD Voltage Range V OVD (Note 2) -0.3 VCC + 0.3 V Gate-Driver Output Charge Loading QG 20 nC

ELECTRICAL CHARACTERISTICS

(VCC = +4.75V to +5.25V, TA = -40°C to +105°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current I CC GA, GB loaded with 600pF 12 mA Input Leakage (Digital Pins) I L -1.0 +1.0 µA Power-Down Current I PDN 1m A Output Leakage (SDA, FAULT)I LO High impedance -1.0 +1.0 µA Low-Level Output Voltage (LSYNC, PSYNC) VOL IOL = 4mA 0.4 V VOL1 IOL1 = 3mA 0.4Low-Level Output Voltage (SDA, FAULT) VOL2 IOL2 = 6mA 0.6 V Low-Level Output Voltage (GA1, GB1) VOL3 IOL3 = 4mA 0.4 V High-Level Output Voltage (LSYNC, PSYNC) VOH IOH = -1mA 2.4 V

Single-Channel Automotive CCFL Controller ELECTRICAL CHARACTERISTICS (continued) (VCC = +4.75V to +5.25V, TA = -40°C to +105°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS High-Level Output Voltage (GA, GB) VOH1 IOH1 = -1mA VCC - 0.4 V UVLO Threshold: VCC Rising VUVLOR 4.3 V UVLO Threshold: VCC Falling VUVLOF 3.7 V UVLO Hysteresis VUVLOH 200 mV SVML/H Threshold: Rising V SVMR 2.03 2.08 2.15 V SVML/H Threshold: Falling V SVMF 1.95 2.02 2.07 V LCM and OVD DC Bias Voltage V DCB 1.1 V LCM and OVD Input Resistance R DCB 50 k Ω Lamp Off Threshold V LOT (Note 3) 0.22 0.25 0.28 V Lamp Over Current V LOC (Note 3) 2.2 2.5 2.8 V Lamp Regulation Threshold V LRT (Notes 3, 4) 0.9 1.0 1.1 V OVD Threshold V OVDT (Note 3) 0.9 1.0 1.1 V Lamp Frequency Source Frequency Range fLFS:OSC 40 100 kHz Lamp Frequency Source Frequency Tolerance fLFS:TOL LOSC resistor ±2% over temperature -5 +5 % Lamp Frequency Receiver Frequency Range fLFR:OSC 40 100 kHz Lamp Frequency Receiver Duty Cycle fLFR:DUTY 40 60 % DPWM Source (Resistor) Frequency Range fDSR:OSC 22.5 440.0 Hz DPWM Source (Resistor) Frequency Tolerance fDSR:TOL POSC resistor ±2% over temperature -5 +5 % DPWM Source (Ext. Clk) Frequency Range fDSE:OSC 22.5 440.0 Hz DPWM Source (Ext. Clk) Duty Cycle fDFE:DUTY 40 60 % DPWM Receiver Min Pulse Width tDR:MIN (Note 5) 25 µs BRIGHT Voltage: Minimum Brightness VBMIN 0.5 V BRIGHT Voltage: Maximum Brightness VBMAX 2.0 V Gate Driver Output Rise/Fall Time tR / tF CL = 600pF 100 ns GA1 and GB1 Duty Cycle (Note 6) 44 %

Single-Channel Automotive CCFL Controller Note 1: All voltages are referenced to ground unless otherwise noted. Currents into the IC are positive, out of the IC negative. Note 2: During fault conditions, the AC-coupled feedback values are allowed to be below the absolute max rating of the LCM1 or OVD1 pin for up to 1 second. Note 3: Voltage with respect to VDCB. Note 4: Lamp overdrive and analog dimming (based on reduction of lamp current) are disabled. Note 5: This is the minimum pulse width guaranteed to generate an output burst, which will generate the DS3881 ’s minimum burst duty cycle. This duty cycle may be greater than the duty cycle of the PSYNC input. Once the duty cycle of the PSYNC input is greater than the DS3881 ’s minimum duty cycle, the output ’s duty cycle will track the PSYNC ’s duty cycle. Leaving PSYNC low (0% duty cycle) disables the GA1 and GB1 outputs in DPWM receiver mode. Note 6: This is the maximum lamp frequency duty cycle that will be generated at GA1 or GB1 outputs with spread-spectrum modu- lation disabled. Note 7: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard- mode timing. Note 8: After this period, the first clock pulse can be generated. Note 9: CB— total capacitance allowed on one bus line in picofarads. Note 10: EEPROM write time applies to all the EEPROM memory. EEPROM write begins after a stop condition occurs. Note 11: Guaranteed by design. I2C AC ELECTRICAL CHARACTERISTICS (See Figure 9) (VCC = +4.75V to +5.25V, TA = -40°C to +105°C, timing referenced to VIL(MAX) and VIH(MIN).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency f SCL (Note 7) 0 400 kHz Bus Free Time Between Stop and Start Conditions tBUF 1.3 µs Hold Time (Repeated) Start Condition tHD:STA (Note 8) 0.6 µs Low Period of SCL t LOW 1.3 µs High Period of SCL t HIGH 0.6 µs Data Hold Time tHD:DAT 0 0.9 µs Data Setup Time tSU:DAT 100 ns Start Setup Time t SU:STA 0.6 µs SDA and SCL Rise Time t R (Note 9) 20+ 0.1CB 300 ns SDA and SCL Fall Time t F (Note 9) 20+ 0.1CB 300 ns Stop Setup Time tSU:STO 0.6 µs SDA and SCL Capacitive Loading CB (Note 9) 400 pF EEPROM Write Time t W (Note 10) 20 30 ms NONVOLATILE MEMORY CHARACTERISTICS (VCC = +4.75V to +5.25V) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM Write Cycles +85 °C (Note 11) 30,000

Single-Channel Automotive CCFL Controller ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3881 toc01 SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 4.5 5.0 5.5 6.0 6.5 7.0 4.0 4.75 5.25 DPWM = 10% DPWM = 50% DPWM = 100% SVML< 2V fLF:OSC = 64kHzGATE QC = 3.5nC ACTIVE SUPPLY CURRENT vs. TEMPERATURE DS3881 toc02 TEMPERATURE (°C) SUPPLY CURRENT (mA) 32.5 5.5 6.0 6.5 7.0 5.0 -40.0 105 VCC = 4.75V VCC = 5.0V VCC = 5.25V DPWM = 100% fLF:OSC = 64kHz GATE QC = 3.5nC INTERNAL FREQUENCY CHANGE vs. TEMPERATURE DS3881 toc03 TEMPERATURE (°C) FREQUENCY CHANGE (%) 32.5 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 1.0 -1.0 -40.0 105 DPWM FREQUENCY LAMP FREQUENCY TYPICAL OPERATION AT 11V DS3881 toc0410µs 5.0V GA 10µs 5.0V GB 10µs 2.00V LCM 10µs 2.00V OVD TYPICAL OPERATION AT 13V DS3881 toc0510µs 5.0V GA 10µs 5.0V GB 10µs 2.00V LCM 10µs 2.00V OVD TYPICAL OPERATION AT 16V DS3881 toc0610µs 5.0V GA 10µs 5.0V GB 10µs 2.00V LCM 10µs 2.00V OVD TYPICAL STARTUP WITH SVM DS3881 toc072ms 5.0V SVML 2ms 5.0V GB 2ms 2.00V LCM 2ms 2.00V OVD BURST DIMMING AT 150Hz AND 10% DS3881 toc08 1ms 5.0V GA 1ms 5.0V GB 1ms 2.00V LCM 1ms 2.00V OVD BURST DIMMING AT 150Hz AND 50% DS3881 toc09 1ms 5.0V GA 1ms 5.0V GB 1ms 2.00V LCM 1ms 2.00V OVD Typical Operating Characteristics (VCC = 5.0V, TA = +25°C, unless otherwise noted.)

Single-Channel Automotive CCFL Controller Typical Operating Characteristics (continued) (VCC = 5.0V, TA = +25°C, unless otherwise noted.) SOFT-START AT VINV = 16V DS3881 toc1050µs 5.0V GA 50µs 5.0V GB 50µs 2.00V LCM 50µs 2.00V OVD LAMP STRIKE—EXPANDED VIEW DS3881 toc111ms 5.0V GA 1ms 5.0V GB 1ms 2.00V LCM 1ms 2.00V OVD LAMP STRIKE WITH OPEN LAMP, AUTO RETRY DISABLED DS3881 toc120.5s 5.0V GA 0.5s 5.0V GB 0.5s 2.00V LCM 0.5s

2.00 OVD

LAMP OUT (LAMP OPENED), AUTO-RETRY DISABLED DS3881 toc130.1s 5.0V GA 0.1s 5.0V GB 0.1s 2.00V LCM 0.1s 2.00V OVD LAMP OPENED

Single-Channel Automotive CCFL Controller Pin Description PIN NAME FUNCTION 1, 9 A0, A1 Address Select Input. Determines I2C slave address. 2 SDA S er i al D ata Inp ut / O utp ut. I2C b i d i r ecti onal d ata p i n, w hi ch r eq ui r es a p ul l up r esi stor to r eal i ze hi g h l og i c l evel s. 3 SCL Serial Clock Input. I 2C clock input.

4 LSYNC

Lamp Frequency Input/Output. This pin is the input for an externally sourced lamp frequency when the DS3881 is configured as a lamp frequency receiver. If the DS3881 is configured as a lamp frequency source (i.e., the lamp frequency is generated internally), the frequency is output on this pin for use by other lamp frequency receiver DS3881s. 5 LOSC Lam p Osci l l ator Resi stor Ad j ust. A r esi stor to g r ound on thi s l ead sets the fr eq uency of the i nter nal l am p osci l l ator . 6 BRIGHT Analog Brightness Control Input. Used to control the DPWM dimming feature. Ground if unused.

7 PSYNC

D P W M Inp ut/Outp ut. Thi s p i n i s the i np ut for an exter nal l y g ener ated D P WM si g nal w hen the D S 3881 i s confi g ur ed as a D P WM r ecei ver . If the D S 3881 i s confi g ur ed as a D P WM sour ce ( i .e., the D P WM si g nal i s g ener ated i nter nal l y) , the D P WM si g nal i s outp ut on thi s p i n for use b y other D P WM r ecei ver D S 3881s.

8 POSC

DPWM Oscillator Resistor Adjust. A resistor to ground on this lead sets the frequency of the DPWM oscillator. This lead can optionally accept a 22.5Hz to 440Hz clock that will become the source timing of the internal DPWM signal. 10 GND_S I2C Interface Ground Connection. GND_S must be at the same potential as GND. 11 SVML Low-Supply Voltage Monitor Input. Used to monitor the inverter voltage for undervoltage conditions. 12 SVMH High-Supply Voltage Monitor Input. Used to monitor the inverter voltage for overvoltage conditions. 13, 21 V CC Power Supply Connections. Both pins must be connected. 14 LCM1 Lamp Current Monitor Input. Lamp current is monitored by a resistor placed in series with the low voltage side of the lamp. 15 OVD1 Overvoltage Detection. Lamp voltage is monitored by a capacitor divider placed on the high voltage side of the transformer. 16 N.C. No Connection. Do not connect any signal to this pin.

17 STEP

Lamp Frequency Step Input. This active-high digital input moves the lamp oscillator frequency up or down by either 1%, 2%, 3%, or 4% as configured in the EMIC register. This pin is logically ORed with the STEPE bit in the EMIC register.

18 GND Ground Connection

19 LCO

Lamp Current Overdrive Enable Input. A high digital level at this input enables the lamp current overdrive circuit. The amount of overdrive current is configured by the LCOC register. When this input is low, the lamp current is set to its nominal level. This pin is logically ORed with the LCOE bit in the LCOC register.

20 PDN

Lamp On/Off Control Input. A low digital level at this input turns the lamp on. A high digital level clears the fault logic, turns the lamp off, and places the device into the power-down mode. This pin is logically ORed with the PDNE bit in the CR2 register. 22, 23 GA1, GB1 MOSFET A and B Gate Drive. Connect directly to logic-level mode n-channel MOSFET. 24 FAULT Active-Low Fault Output. This open-drain pin requires external pullup resistor to realize high-logic levels.

8 BYTE USER MEMORY

Figure 1. Functional Diagram

duces near-sinusoidal waveforms. mizes the lamp’s brightness and lifetime. cussed on the following pages of this data sheet. configuration/status registers as well as user memory. gramming, contact the factory.

64 LAMP CYCLE

Figure 2. Per Channel Logic Diagram

Single-Channel Automotive CCFL Controller Shadowed EEPROM The DS3881 incorporates SRAM-shadowed EEPROM memory locations for all memory that needs to be retained during power cycling. At power-up, SEEB (bit 7 of the BLC register) is low, which causes the shadowed locations to act as ordinary EEPROM. Setting SEEB high disables the EEPROM write function and causes the shadowed locations to function as ordinary SRAM cells. This allows an infinite number of write cycles with- out causing EEPROM damage and also eliminates the EEPROM write time, t W from the write cycle. Because memory changes made when SEEB is set high are not written to EEPROM, these changes are not retained through power cycles, and the power-up EEPROM values are the last values written with SEEB low. Lamp Dimming Control The DS3881 provides two independent methods of lamp dimming that can be combined to achieve a dim- ming ratio of 300:1 or greater. The first method is “burst” dimming, which uses a digital pulse-width-mod- ulated (DPWM) signal (22.5Hz to 440Hz) to control the lamp brightness. The second is “analog ” dimming, which is accomplished by adjusting the lamp current. Burst dimming provides 128 linearly spaced brightness steps. Analog dimming provides smaller substeps that allow incremental brightness changes between burst dimming steps. This ability is especially useful for low- brightness dimming changes, where using burst dim- ming alone would cause visible brightness step changes. Analog dimming also allows the brightness to be reduced below the minimum burst dimming level, which provides for the maximum dimming range. Burst dimming can be controlled using a user-supplied analog voltage on the BRIGHT pin or through the I interface. Analog dimming can only be controlled through the I 2C interface. Therefore, for applications that require the complete dimming range and resolution capa- bility of the DS3881, I 2C dimming control must be used. Burst Dimming Burst dimming increases/decreases the brightness by adjusting (i.e., modulating) the duty cycle of the DPWM signal. During the high period of the DPWM cycle, the lamps are driven at the selected lamp frequency (40kHz to 100kHz) as shown in Figure 6. This part of the cycle is called the “burst” period because of the lamp frequency burst that occurs during this time. During the low period of the DPWM cycle, the controller disables the MOSFET gate drivers so the lamps are not driven. This causes the current to stop flowing in the lamps, but the time is short enough to keep the lamps from de-ionizing. The DS3881 can generate its own DPWM signal inter- nally (set DPSS = 0 in CR1), which can then be sourced to other DS3881s if required, or the DPWM sig- nal can be supplied from an external source (set DPSS = 1 in CR1). To generate the DPWM signal internally, the DS3881 requires a clock (referred to as the dim- ming clock) to set the DPWM frequency. The user can supply the dimming clock by setting POSCS = 1 in CR1 and applying an external 22.5Hz to 440Hz signal at the POSC pin, or the dimming clock can be generated by the DS3881 ’s internal oscillator (set POSCS = 0 in CR1), in which case the frequency is set by an external resistor at the POSC pin. These two dimming clock options are shown in Figure 3. Regardless of whether the dimming clock is generated internally or sourced externally, the POSC0 and POSC1 bits in CR2 must be set to match the desired dimming clock frequency. The internally generated DPWM signal can be provided at the PSYNC I/O pin (set RGSO = 0 in CR1) for sourc- ing to other DS3881s, if any, in the circuit. This allows all DS3881s in the system to be synchronized to the same DPWM signal. A DS3881 that is generating the DPWM signal for other DS3881s in the system is referred to as the DPWM source. When bringing in an externally generated DPWM signal, either from another DS3881 acting as a DPWM source or from some other user-provided source, it is input into the PSYNC I/O pin of the DS3881, and the receiving DS3881 is referred to a DPWM receiver. In this mode, the BRIGHT and POSC inputs are disabled and should be grounded (see Figure 5). When the DPWM signal is generated internally, its duty cycle (and, thus, the lamp brightness) is controlled either by a user-supplied analog voltage at the BRIGHT input or through the I 2C interface by varying the 7-bit PWM code in the BPWM register. When using the BRIGHT pin to control burst dimming, a voltage of less than 0.5V causes the DS3881 to operate with the mini- mum burst duty cycle, providing the lowest brightness setting, while any voltage greater than 2.0V causes a 100% burst duty cycle (i.e., lamps always being dri- ven), which provides the maximum brightness. For volt- ages between 0.5V and 2V, the duty cycle varies linearly between the minimum and 100%. Writing a non- zero PWM code to the BPWM register disables the BRIGHT pin and enables I 2C burst dimming control. Setting the 7-bit PWM code to 0000001b causes the DS3881 to operate with the minimum burst duty cycle, while a setting of 1111111b causes a 100% burst duty cycle. For settings between these two codes, the duty cycle varies linearly between the minimum and 100%.

Figure 5. Frequency Configuration Options for Designs Using Multiple DS3881s

result from current surges in the transformer primary. A 16 LAMP CYCLE PERIOD RESULTS IN A LINEAR RAMP IN LAMP CURRENT. Figure 6. Digital PWM Dimming and Soft-Start

• kHz for lamp frequency calculations. When calculating the resistor value for the dimming clock frequency, K will be one of four values as determined by the desired frequency and the POSCR0 and POSCR1 bit settings as shown in the Control Register 2 (CR2) Table 6 in the Detailed Register Descriptions section. Example: Selecting the resistor values to configure a DS3881 to have a 50kHz lamp frequency and a 160Hz dimming clock frequency: For this configuration, POSCR0 and POSCR1 must be programmed to 1 and 0, respectively, to select 90Hz to 220Hz as the dimming clock frequency range. This sets K for the dimming clock resistor (R POSC) calculation to 4kΩ• kHz. For the lamp frequency resistor (R LOSC ) calculation, K = 1600kΩ• kHz, which sets the lamp frequency K value regardless of the frequency. The formula above can now be used to calculate the resistor values for R LOSC and RPOSC as follows: Supply Monitoring The DS3881 has supply voltage monitors (SVMs) for both the inverter’s transformer DC supply (V INV) and its own VCC supply to ensure that both voltage levels are adequate for proper operation. The transformer supply is monitored for overvoltage conditions at the SVMH pin and undervoltage conditions at the SVML pin. External resistor-dividers at each SVM input feed into two com- parators (see Figure 7), both having 2V thresholds. Using the equation below to determine the resistor val- ues, the SVMH and SVML trip points (V TRIP) can be customized to shut off the inverter when the trans- former ’s supply voltage rises above or drops below specified values. Operating with the transformer ’s sup- ply at too low of a level can prevent the inverter from reaching the strike voltage and could potentially cause numerous other problems. Operating with the trans- former voltage at too high of a level can be damaging to the inverter components. Proper use of the SVMs can prevent these problems. If desired, the high and/or low SVMs can be disabled by connecting the SVMH pin to GND and the SVML pin to V CC. The VCC monitor is used as a 5V supply undervoltage lockout (UVLO) that prevents operation when the DS3881 does not have adequate voltage for its analog circuitry to operate or to drive the external MOSFETs. The V CC monitor features hysteresis to prevent V CC noise from causing spurious operation when V CC is near the trip point. This monitor cannot be disabled by any means. Fault Monitoring The DS3881 provides extensive fault monitoring. It can detect open-lamp, lamp overcurrent, failure to strike, and overvoltage conditions. The DS3881 can be con- figured to disable the output if the channel enters a fault state. Once a fault state has been entered, the FAULT output is asserted and the channel remains dis- abled until it is reset by a user or host control event. See Step 4, Fault Handling for more detail. The DS3881 can also be configured to automatically attempt to clear a detected fault (except lamp overcurrent) by re-strik- ing the lamp. Configuration bits for the fault monitoring options are located in CR1 and CR2. The DS3881 also has real-time status indicator bits located in the SR1 and SR2 register (SRAM) that assert whenever a corre- sponding fault occurs. V RR RTRIP . =    +20 12 R k kHz kHz k R k kHz kHz k LOSC POSC . . = • = = • = 1600 50 32 0 0 160 25 0 Ω Ω Ω Ω R K fOSC OSC SVML R1 2.0V VINV SVMH VTRIPVTRIP R12.0V VINV DS3881

Figure 7. Setting the SVM Threshold Voltage

Single-Channel Automotive CCFL Controller Figure 8 shows a flowchart of how the DS3881 controls and monitors each lamp. The steps are as follows: 1) Supply Check— The lamps do not turn on unless the DS3881 supply voltage is above 4.3V and the volt- age at the supply voltage monitors, SVML and SVMH, are respectively above 2.0V and below 2.0V. 2) Strike Lamp — When both the DS3881 and the DC inverter supplies are at acceptable levels, the DS3881 attempts to strike the lamp. The DS3881 slowly ramps up the MOSFET gate duty cycle until the lamp strikes. The controller detects that the lamp has struck by detecting current flow in the lamp, detected by the LCM1 pin. If during the strike ramp, the maximum allowable voltage is reached on the OVD1 pin, the controller stops increasing the MOS- FET gate duty cycle to keep from overstressing the system. The DS3881 goes into a fault handling state (step 4) if the lamp has not struck after the timeout period as defined by the LST0 and LST1 control bits in the SSP1 register. If an overvoltage event is detect- ed during the strike attempt, the DS3881 disables the MOSFET gate drivers and go into the fault handling state. 3) Run Lamp — Once the lamp is struck, the DS3881 adjusts the MOSFET gate duty cycle to optimize the lamp current. The gate duty cycle is always con- strained to keep the system from exceeding the maximum allowable lamp voltage. The lamp current sampling rate is user-selectable using the LSC0 and LSC1 bits in CR2. If lamp current ever drops below the lamp out reference point for the period as defined by the LST0 and LST1 control bits in the SSP1 register, then the lamp is considered extinguished. In this case, the MOSFET gate drivers are disabled and the device moves to the fault handling stage. 4) Fault Handling — During fault handling, the DS3881 performs an optional (user-selectable) automatic retry to attempt to clear all faults except a lamp over- current. The automatic retry makes 14 additional attempts to rectify the fault before declaring the channel in a fault state and permanently disabling the channel. Between each of the 14 attempts, the controller waits 1024 lamp cycles. In the case of a lamp overcurrent, the DS3881 instantaneously declares the channel to be in a fault state and per- manently disables the channel. Once a fault state is entered, the channel remains in that state until one of the following occurs:

• V CC drops below the UVLO threshold.
• The SVML or SVMH thresholds are crossed.
• The PDN pin goes high.
• The PDNE software bit is written to a logic 1.
• The channel is disabled by the CH1D control bit.

Figure 8. Fault-Handling Flowchart

lation rate (through FS0/1/2) for the application. in brightness when the overdrive is no longer needed. 21 minutes (if a 50kHz lamp frequency is used). The DS3881 ’s register map is shown in Table 1. Table 1. Register Map Note 1: E0h–E3h are SRAM locations, and F0h–FFh are SRAM-shadowed EEPROM. Note 2: Altering the DS3881 configuration during active CCFL operation can cause serious adverse effects.

Table 2. Status Register 1 (SR1) [SRAM, E0h]

0 R0 FAULT_RT

condition. This bit is cleared when read, regardless of the current state of fault. 2 R 0 STO_L Lamp Strike Timeout— Latched. A latched bit that is set when the lamp fails to strike. This bit is cleared when read. at least 64 lamp cycles. This bit is cleared when read. detected. This bit is cleared when read. Note 1: Writing to this register has no effect on it. Note 2: See Figure 8 for more details on how the status bits are set.

• VCC drops below the UVLO threshold.
• The SVML or SVMH thresholds are crossed.
• The PDNE hardware pin goes high.
• The PDNE software bit is written to a logic 1.
• The channel is disabled by the CH1D control bit.

Table 3. Brightness Lamp Current Register (BLC) [SRAM, E3h]

0 R/W 0 LC0

1 R/W 0 LC1

2 R/W 0 LC2

3 R/W 0 LC3

4 R/W 0 LC4

bits are used for fine adjustment of the lamp brightness.

5 R/W 0 CH1D

6 R/W 0 RSVD Reserved. Should be set to 0.

7 R/W 0 SEEB

Single-Channel Automotive CCFL Controller Table 4a. Soft-Start Protocol Registers (SSPx) [Shadowed-EEPROM, F0h, F1h, F2h, F3h] MSB LSBSSP# ADDR FACTORY DEFAULT 7 654 3 2 1 0 SSP1 F0h 21h LST1 Lamp Cycles 3 and 4 LST0 Lamp Cycles 1 and 2 SSP2 F1h 43h RSVD Lamp Cycles 7 and 8 RSVD Lamp Cycles 5 and 6 SSP3 F2h 65h RSVD Lamp Cycles 11 and 12 RSVD Lamp Cycles 9 and 10 SSP4 F3h 77h RSVD Lamp Cycles 15 and 16 RSVD Lamp Cycles 13 and 14 Table 4b. MOSFET Duty Cycle (MDC)Codes for Soft-Start Settings BIT R/W NAME FUNCTION

0 R/W MDC0

MDC0/1/2/3: These bits determine a MOSFET duty cycle that repeats twice in the 16 lamp cycle soft-start.

1 R/W MDC1

MDC CODE MOSFET DUTY CYCLE MDC CODE MOSFET DUTY CYCLE 0h Fixed at 0% 4h Fixed at 13%2 R/W MDC2 1h Fixed at 3% 5h Fixed at 16% 2h Fixed at 6% 6h Fixed at 19% 3h Fixed at 9% 7h Most Recent Value3 R/W LST0 / RSVD 4 R/W MDC0 LST0/1: These bits select strike and lamp out timeout. LST0 and LST1 control fault behavior for all lamps.

5 R/W MDC1 LST1 LST0 STRIKE AND LAMP OUT TIMEOUT

(LAMP FREQUENCY CYCLES) EXAMPLE TIMEOUT IF LAMP FREQUENCY IS 50kHz 0 0 32,768 0.66 seconds6 R/W MDC2 0 1 65,536 1.31 seconds 1 0 98,304 1.97 seconds7 R/W LST1 / RSVD 1 1 131,072 2.62 seconds

Table 5. Control Register 1 (CR1) [Shadowed-EEPROM, F4h]

0 R/W 0 LOCE

0 = Lamp overcurrent detection disabled. 1 = Lamp overcurrent detection enabled.

1 R/W 0 POSCS

1 = POSC input is a 22.5Hz to 440Hz clock.

2 R/W 0 LFSS

0 = Lamp frequency generated internally and sourced from the LSYNC output. 1 = Lamp frequency generated externally and supplied to the LSYNC input.

3 R/W 0 DPSS

0 = DPWM signal generated internally and sourced from the PSYNC output. 1 = DPWM signal generated externally and supplied to the PSYNC input.

4 R/W 0 RGSO

0 = Source DPWM at the PSYNC output. 1 = Source internal ramp generator at the PSYNC output.

5 R/W 0 ARD

0 = Autoretry function enabled. 1 = Autoretry function disabled. 6 R/W 0 RSVD Reserved. Should be set to 0.

7 R/W 0D P D

Table 6. Control Register 2 (CR2) [Shadowed-EEPROM, F5h]

0 R/W 0 UMWP

1 R/W 0 POSCR0

2 R/W 0 POSCR1

Lamp Sample Rate Select. Determines the feedback sample rate of the LCM inputs.

3 R/W 1 LSR0

5 — 0 RSVD Reserved. This bit should be set to zero. 6 — 0 RSVD Reserved. This bit should be set to zero.

7 R/W 0 PDNE

Table 7. EMI Control Register (EMIC) [Shadowed-EEPROM, F6h]

2 R/W 0 SSM

1 = Pseudorandom modulation. 3  RSVD Reserved. This bit should be set to zero.

4 R/W 0 STEPE

Lamp Frequency Step Enable. Logically ORed with the step invoked. 0 = Lamp operates at nominal frequency.

5 R/W 0 FS0

Table 8. Lamp Current Overdrive Control Register (LCOC) [Shadowed-EEPROM, F7h]

3 R/W 0 LCOE

Lamp Current Overdrive Enable. Logically ORed with the LCO pin. 0 = Lamp operated with nominal current setting.

4 R/W 0 TO0

5 R/W 0 TO1

6 R/W 0 TO2

7 R/W 0 TO3

clock pulses, start, and stop conditions. master to initiate a new data transfer with a slave. shifted into the device during the rising edge of the SCL. forms a NACK by transmitting a one during the 9th bit. the device is not receiving data. acknowledgement is read using the bit-read definition. NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN). Figure 9. I2C Timing Diagram

the next start condition is sent. memory location where the slave is to store the data. all byte write operations. See Figure 11 for more detail. the stop condition to write the contents to EEPROM. elapse before attempting to write again to the DS3881. are performed at room temperature. Figure 10. DS3881’s Slave Address Byte

28% to 35% duty cycle during steady state operation. open-circuit voltage that is used to strike the lamp. er supply, 438mm x 2.2mm lamp design. the Recommended DC Operating Conditions table. and capacitors used in the Typical Operating Circuit. and GND pins of the IC to minimize lead inductance. 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. Figure 11. I2C Communications Examples

Table 9. Transformer Specifications (as Used in the Typical Operating Circuit) Note 1: Primary should be Bifilar wound with center tap connection. Note 2: Turns ratio is defined as secondary winding divided by the sum of both primary windings. Table 10. Resistor and Capacitor Selection Guide 105kΩ 1 — See the Setting the SVM Threshold Voltage section. Configuration section to determine value. Configuration section to determine value. R7 1/Chan 140Ω 1 — See the Setting the RMS Lamp Current section. for V D C B to r each i ts nor m al op er ati ng l evel . C2 1/Chan 10pF 5 ±1000ppm/°C 2kV to 4kV breakdown voltage required. for V D C B to r each i ts nor m al op er ati ng l evel . C7 2/DS3881 0.1µF 10 X7R Place close to V CC and GND on DS3881.

Single-Channel Automotive CCFL Controller Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. Heaney INVERTER SUPPLY VOLTAGE (VINV) (8V TO 16V) GA1 LAMP CURRENT MONITOR CCFL LAMP GB1 OVD1 VCC VCC VCC VCC BRIGHT SVMH LAMP BRIGHTNESS TRANSFORMERDUAL POWER MOSFET DEVICE SUPPLY VOLTAGE (5V ±5%) OVERVOLTAGE DETECTION LCM1 GND LAMP FREQUENCY INPUT/OUTPUT LSYNC SCL SDA I2C CONFIGURATION AND CONTROL PORT FAULT PSYNCDPWM SIGNAL INPUT/OUTPUT LOSC POSC LCO PDNLAMP ON/OFF LAMP CURRENT OVERDRIVE ENABLE SVMLA0 HARDWARE CONTROL STEP LAMP FREQUENCY STEP GND_S R1 R2 R9 R10 R11 R3 R4 R5 R6 DS3881 Typical Operating Circuit

Package Information

For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Chip Information TRANSISTOR COUNT: 38,000 SUBSTRATE CONNECTED TO GROUND