DS3803 | DigiCamel IC Datasheet

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{> DALLAS Ds3803 I SEMICONDUCTOR 1024k Flexible NV SRAM SIMM FEATURES PIN ASSIGNMENT = Flexibly organized as 32k x 32, 64k x 16 or 128k x 8bits E- o = 10 years minimum data retention in the = absence of external power = = Nonvolatile circuitry transparent to and =e independent from host system = = Automatic write protection circuitry E le ns safeguards against data loss = e 3 = Separate control and data signals for each = SRAM allow byte, word or doubleword & low access B iz 3 = Fast access time of 70 ns BF = Full Voc + 10% operating range E = Employs popular JEDEC standard 72-position = SIMM connector =e = Extremely thin design built using TSOP- = Bx O package IC components ES DS3803 72-Pin SIMM PIN DESCRIPTION AO-Al14 - Address Inputs DOA-D7A_ - Data Inputs/Outputs, Byte A DOB-D7B_ - Data Inputs/Outputs, Byte B DOC -D7C_ - Data Inputs/Outputs, Byte C DOD-D7D_ - Data Inputs/Outputs, Byte D CEA - CED - Chip Enable Inputs WEA - WED - Write Enable Inputs OFA - OD - Output Enable Inputs VCC - +5V Power Supply GND - Ground NC - No Connect

DESCRIPTION

The DS3803 is a self-contained, 1,048,576-bit, nonvolatile static RAM which can be flexibly organized as 32k x 32, 64k x 16 or 128k x 8. Built using four 32k x 8 SRAMs, four nonvolatile control ICs and four lithium batteries, this nonvolatile memory contains all necessary control circuitry and lithium energy sources to maintain data integrity in the absence of power for more than 10 years. The DS3803 employs the popular JEDEC standard 72-position SIMM connection scheme and requires no additional circuitry. 1 of 10 112299

The DS3803 executes a read cycle whenever WE (Write enable) is inactive (high) and CE (Chip Enable) and OF (Output Enable) are active (low). The unique address specified by the 15 address inputs (Ao - Aj4) defines which byte of data is to be accessed from the selected SRAMs. Valid data will be available to the data output drivers within tacc (Access Time) after the last address input signal is stable, providing that CE and OF (Output Enable) access times are also satisfied. If CE and OF access times are not satisfied, then data access must be measured from the later occurring signal and the limiting parameter is either tco for CE or tor for OF rather than tacc . WRITE MODE The DS3803 executes a write cycle whenever both WE and CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (twr) before another cycle can be initiated. The OF control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OF active), then WE will disable the outputs in topw from its falling edge. DATA RETENTION MODE The DS3803 provides full functional capability for Voc greater than 4.5 volts and write-protects by 4.25 volts. Data is maintained in the absence of Vcc without any additional support circuitry. The nonvolatile static RAM constantly monitors Vcc. Should the supply voltage decay, the NV SRAM automatically write-protects itself, all inputs become don’t care, and all outputs become high impedance. As Vcc falls below approximately 3.0 volts, power switching circuits connect the lithium energy sources to the RAMs to retain data. During power-up, when Vcc rises above approximately 3.0 volts, the power switching circuits connect external Vcc to the RAMs and disconnects the lithium energy source. Normal RAM operation can resume after Vcc exceeds 4.5 volts. The DS3803 checks battery status to warn of potential data loss. Each time that Vec power is restored to the DS3803, the battery voltages are checked with precision comparators. If both batteries providing backup power to a particular SRAM are less than 2.0 volts, the second memory access to that SRAM is inhibited. Battery status for each SRAM can therefore be determined by a three-step process. First, a read cycle is performed to any location within that SRAM in order to save the contents of that location. A subsequent write cycle can then be executed to the same memory location, altering data. If a subsequent read cycle fails to verify the written data, then battery voltage for that SRAM is less than 2.0V and data is in danger of being lost. The DS3803 also provides battery redundancy. In many applications data integrity is paramount. The DS3803 provides two batteries for each SRAM and an internal isolation switch to select between them. During battery backup, the battery with the highest voltage is selected for use. If one battery fails, the other automatically takes over. The switch between batteries is transparent to the user. 2 of 10

AO-A14 A0-A14 Voc) Veco Voc! (=) ‘SRAM — = vi WEA |_| WE ok oR i oF be i cco ews ce D7 cei CEA AO-A14 Voc! Veco Veo on) ‘SRAM Veari OEB OE CEO CEB AD-A14 Voc) Veco Vee e) = = ‘SRAM Veart occ __} ce Fe ze) i «ze ii cei CEC AD-AI4 Voc} Veco Vea] C) ‘SRAM Vaart 7 we wi OED OE CEO fe a DOA-D7D cei CED 4 of 10

ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to +7.0V Operating Temperature 0°C to 70°C Storage Temperature -40°C to +85°C * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (Ta = 0°C to 70°C) PARAMETER SYMBOL UNITS | NOTES DC ELECTRICAL CHARACTERISTICS (Ta = 0°C to 70°C; Vee = 5V +10%) PARAMETER SYMBOL TEST MIN | TYP | MAX | UNITS CONDITION Output Leakage Current Lo OV < Vins Vee, +1 pA all CE = Vin Operating Current Icco min cycle, 300 mA duty=100% all CE = Vit, Ivo = 0, Vin = Vin or Vit CAPACITANCE Ta = 25°C) PARAMETER SYMBOL UNITS | NOTES 5 of 10

AC ELECTRICAL CHARACTERISTICS (Ta = O°C to 70°C; Voc = 5V +10%) [PARAMETER [SYMBOL] MIN | TYP | MAX [UNITS | NOTES | |Read Cycle Time | tee | 0 | ts | AccessTime | tue | ts | [oF to Ouputvaid | toe f(s as | toOupurvalid | to | Ps | OF or CE tw OupurActive | teow | Sf [| ts fs | Deselection to OutputHighZ | too | | 5s Output Hold after Address ton 5 ns Change [WriteCycleTime | twe | 0 Pts [Write Pulse Width | te =| 55 Ts | Address Setup Time | taw | 0] ts Write Recovery Time twri 5 ns 11 twr2 15 12 | WE Active to OutputHighZ | toow | | | sf | WE Inactive wo Output Active | tow | 5 | | ts ST [Data Seup Time | ts | 30 Pts Data Hold Time tom 0 ns 11 tor? 10 12 TIMING DIAGRAM: READ CYCLE sores ie eh mc : tou e SANS fe LULA LLLLLLL |__ V 7, Peg | ke wor mK vor BOG i Sei ie SEE NOTE 1 6 of 10

‘oow -— hed Dour WAV AVA AA OA Nakai AISI NS ZNSZNZNZNZNZNZNTZY ee | ooo TIMING DIAGRAM: WRITE CYCLE 2 (CE Controlled) cour ae | NON ZN ‘os | ‘ove 7 of 10

TIMING DIAGRAM: POWER-DOWN AND POWER-UP Voc : \\ eee 2Nv \\ Tha ‘ec ten Z SLEWS WwTH — lec we o LLL ve BACKUP CURRENT SUPPLIED FROM LITHIUM BATTERY ‘SEE NOTE 10 POWER-DOWN AND POWER-UP TIMING PARAMETER SYMBOL UNITS | NOTES Vcc Fail Detect to 1.5 Us CE and WE Inactive Vec Valid to tru 2 CE and WE Inactive Vec Valid to End of Write trec 125 ms Protection (Ta = 25°C) PARAMETER SYMBOL UNITS | NOTES Expected Data Retention tor 10 years Time WARNING Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high throughout read cycle. 2. OF =Vmor Vu. If OF = Vin during write cycle, the output buffers remain in a high impedance state. 8 of 10

twpis specified as the logical AND of CE and WE. twp is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tpsis measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. Ifthe CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high impedance state during this period. 7. Ifthe CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 9. Each DS3803 has a built-in switch that disconnects the lithium source until Vccis first applied by the user. The expected tpg is defined as accumulative time in the absence of Vcc starting from the time power is first applied by the user. 10. In a power-down condition the voltage on any pin may not exceed the voltage on Vcc. 11. twri, tpi are measured from WE going high. 12. twro, toro are measured from CE going high. DC TEST CONDITIONS Outputs Open Cycle = 200 ns All Voltages are Referenced to Ground AC TEST CONDITIONS Output Load: 100 pF + 1TTL gate Input Pulse Levels: 0 - 3.0 V Timing Measurements Reference Levels: Input - 1.5V Output - 1.5V Input Pulse Rise and Fall Times: 5 ns 9 of 10

° 72) q r TH WT il HDA LUALAEL HU i # a F Pm a [in| MAX | Bf 3.979 | 3.989 | | Dd | 0395 | 0.405 | PE | 0.245 | 0.255 | a ee PH 0.245 | 0.255 | a ee Pp Kf 2.120 | 2.130 | | Mf 0.057 | 0.067 | PN f= fT 0.173 | ee ee Pp Pf 0.047 0.054 10 of 10

Product Information

DS3803 specifications and overview.

Summary

1024 Flexible NV SRAM SIMM 112299

Description

1024 Flexible NV SRAM SIMM 112299

Source title DS3803 Datasheet(PDF) - Maxim Integrated Products

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