DS3510 MAXIM | Alldatasheet
Document overview
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Technical content
Features
o 8-Bit Gamma Buffers, 10 Channels o 8-Bit VCOM Buffer, 1 Channel o 4 EEPROM Bytes per Channel o Low-Power 400µA/ch Gamma Buffers o I2C-Compatible Serial Interface o Flexible Control from I2C or Pins o 9.0V to 15.0V Analog Supply o 2.7V to 5.5V Digital Supply o 48-Pin Package (TQFN 7mm x 7mm) Gamma or VCOM Channel Functional Diagram
Ordering Information
SDA, SCL S1/ S0 LD IN OUT ADDRESS I2C INTERFACE LATCH A LATCH B LOGIC MUX 8-BIT□ DAC VOUT Pin Configuration and Typical Operating Circuit appear at end of data sheet. PART TEMP RANGE PIN-PACKAGE DS3510T+ -45°C to +95°C 48 TQFN-EP* DS3510T+T&R -45°C to +95°C 48 TQFN-EP* +Denotes a lead-free package. T&R = Tape and reel. *EP = Exposed pad.
I2C Gamma and VCOM Buffer with EEPROM RECOMMENDED OPERATING CONDITIONS (TA = -45°C to +95°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on VRL, VRH, GHH, GHM, GLM, GLL Voltage on SDA, SCL, A0, LD, S0, Specification. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Digital Supply Voltage V CC (Note 1) +2.7 +5.5 V Analog Supply Voltage V DD (Note 1) +9.0 +15.0 V VRH, VRL Voltage V VCOM Applies to V COM output +2.0 V DD - 2.0 V GHH, GHM, GLM, GLL Voltage V GM1–10 Applies to GM1–GM10 GND + 0.2 V DD - 0.2 V Input Logic 1 (SCL, SDA, A0, S0, S1, LD) VIH 0.7 x VCC VCC + 0.3 V Input Logic 0 (SCL, SDA, A0, S0, S1, LD) VIL -0.3 0.3 x V CC V VCOM Load Capacitor C D 1 µF VCAP Compensation Capacitor C COMP 0.1 µF INPUT ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -45°C to +95°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage (SDA, SCL, S0, S1, LD) IL -1 +1 µA Input Leakage (A0) I L:A0 2 mA VDD Supply Current I DD (Notes 2, 3) 6.7 15.0 mA VCC Supply Current, Nonvo latile Read or Write ICC (Note 4) 0.2 1.0 mA VCC Standby Supply Current I CCQ (Note 5) 1.8 10.0 µA VDD Standby Supply Current I DDQ (Note 6) 2 4 mA I/O Capacitance (SDA, SCL, A0) C I/O (Note 7) 5 10 pF End-to-End Resistance (VRH to VRL) RTOTAL 16 k ABSOLUTE MAXIMUM RATINGS
I2C Gamma and VCOM Buffer with EEPROM INPUT ELECTRICAL CHARACTERISTICS (continued) (VCC = +2.7V to +5.5V, TA = -45°C to +95°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RTOTAL Tolerance T A= +25°C -20 +20 % Input Resistance (GHH, GHM, GLM, GLL) 75 k Input Resistance Tolerance T A= +25°C -20 +20 % OUTPUT ELECTRICAL CHARACTERISTICS otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCOM /GM1–10 DAC resolution 8 Bits VCOM -0.75 +0.75Integral Nonli nearity Error INL (Note 8) Gamma -0.4 +0.4 LSB Differential Nonlinearity Error DNL V COM /gamma (Note 9) -0.3 +0.3 LSB Output Voltage Range (V COM ) 2.0 V DD - 2.0 V Output Voltage Range (GM1–10) 0.2 V DD - 0.2 V VCOM -25 +25Output Accuracy (V COM , GM1–10) T A= +25°C Gamma -50 +50 mV Voltage Gain (GM1–10) (Note 10) 0.995 V/V Load Regulation (V COM , GM1–10) 0.5 mV/mA Short-Circuit Current (V COM ) To V DD or GND 250 mA S0/S1 to LD Setup Time t SU Figure 1 or 2 200 ns S0/S1 to LD Hold Time t HD Figure 1 or 2 200 ns VCOM Settling Time from LD Low to High (S0/S1 Meet t SU ) tSET-V Settling to 0.1% (see Figure 1) (Notes 3, 11) 2 µs GM1–10 Settling Time from LD Low to High tSET-G 4 tau settled with I LOAD = ±20mA (see Figure 2) (Notes 3, 11, 12) 6.7 µs S0, S1 to V COM or GM1–10 Output 10% Settled tSEL 10% settling (see Figure 3), LD = V CC (asynchronous) (Note 12) 450 ns
I2C ELECTRICAL CHARACTERISTICS (See Figure 4) (VCC = +2.7V to +5.5V, TA = -45°C to +95°C, timing referenced to V IL(MAX) and VIH(MIN).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency f SCL (Note 13) 0 400 kHz Bus Free Time Between STOP and START Conditions tBUF 1.3 µs Hold Time (Repeated) START Condition tHD:STA 0.6 µs Low Period of SCL t LOW 1.3 µs High Period of SCL t HIGH 0.6 µs Data Hold Time t HD:DAT 0 0.9 µs Data Setup Time t SU:DAT 100 ns START Setup Time t SU:STA 0.6 µs SDA and SCL Rise Time t R (Note 14) 20 + 0.1C B 300 ns SDA and SCL Fall Time t F (Note 14) 20 + 0.1C B 300 ns STOP Setup Time t SU:STO 0.6 µs SDA and SCL Capacitive Loading CB (Note 14) 400 pF EEPROM Write Time t W (Note 15) 20 ms Pulse-Width Suppression Time at SDA and SCL Inputs tIN (Note 16) 50 ns A0 Setup Time t SU:A Before START 0.6 µs A0 Hold Time t HD:A After STOP 0.6 µs SDA and SCL Input Buffer Hysteresis 0.05 x VCC V Low-Level Output Voltage (SDA) V OL 4mA sink current 0.4 V SCL Falli ng Edge to SDA Output Data Valid tAA SCL fallin g through 0.3V CC to SDA exit 0.3V CC ~0.7V CC window 900 ns Output Data Hold t DH SCL fallin g through 0.3V CC until SDA in 0.3V CC ~0.7V CC window 0 ns DS3510 I2C Gamma and VCOM Buffer with EEPROM
Note 2: IDD supply current is specified with VDD = 15.0V and no load on VCOM or GM1–10 outputs. Note 3: Specified with the VCOM and gamma bias currents set to 100%. Note 4: ICC is specified with the following conditions: SCL = 400kHz, SDA = VCC = 5.5V, and VCOM and GM1–10 floating. Note 5: ICCQ is specified with the following conditions: SCL = SDA = VCC = 5.5V, and VCOM and GM1–10 floating. Note 6: IDDQ is specified with the following conditions: SCL = SDA = VCC = 5.5V and VCOM and GM1–10 floating. Note 7: Guaranteed by design. value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting. expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position. Note 11: EEPROM data is assumed already settled at input of Latch B. LD transitions after EEPROM byte has been selected. Note 12: Rising transition from 5V to 10V; falling transition from 10V to 5V. Note 14: CB—total capacitance of one bus line in picofarads. Note 15: EEPROM write time begins after a STOP condition occurs. Note 16: Pulses narrower than max are suppressed. Figure 1. VCOM Settling Timing Diagram
4 TAU SETTLED
Figure 2. GM1–10 Settling Timing Diagram Figure 3. Input Pin to Output Change Timing Diagram NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). Figure 4. I2C Timing Diagram
I2C Gamma and VCOM Buffer with EEPROM Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) ICC vs. VCC DS3510 toc01 VCC (V) ICC (µA) 100 120 140 160 180 2.7 +95° C +25° C -40° C IDD vs. VDD DS3510 toc02 VDD (V) IDD (mA) 14 1513121110 4.5 5.0 5.5 6.0 6.5 7.0 4.0 +95°C +25° C -40°C ICC vs. TEMPERATURE DS3510 toc03 TEMPERATURE (°C) ICC (µA) 90450 100 120 140 160 180 -45 5.5V 3.6V 2.7V IDD vs. VDD DS3510 toc04 VDD (V) IDD (mA) 90450 4.5 5.0 5.5 6.0 6.5 7.0 4.0 -45 +95° C +25° C -40° C IDD vs. BIAS CURRENT SETTING DS3510 toc05 BIAS CURRENT SETTING (DEC) IDD (mA) VCC = 4V, VDD = 15V□ VCOM INL vs. SETTING DS3510 toc06 VCOM SETTING (DEC) VCOM INL (LSB) 25020050 100 150 -0.55 -0.35 -0.15 0.05 0.25 0.45 0.65 -0.75 VCOM DNL vs. SETTING DS3510 toc07 VCOM SETTING (DEC) VCOM DNL (LSB) 25020050 100 150 -0.2 -0.1 0.1 0.2 0.3 -0.3 GM1–GM10 INL vs. SETTING DS3510 toc08 GM1–GM10 SETTING (DEC) GM1–GM10 INL (LSB) 25020050 100 150 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 -0.4 GM1–GM10 DHL vs. SETTING DS3510 toc09 GM1–GM10 SETTING (DEC) GM1–GM10 DNL (LSB) 25020015010050 -0.2 -0.1 0.1 0.2 0.3 -0.3
I2C Gamma and VCOM Buffer with EEPROM Pin Description NAME PIN TYPE FUNCTION VDD 1, 19, 20, 24 Power Analog Supply (9.0V to 15.5V) GND 2, 38, 40, 42, 43 Power Ground LD 3 Input Latch Data Input. When LD is low, Latch B retains existing data (acts as a latch). When LD is high, the input to Latch B data flows through to the output and updates the DACs asynchronously. S1 4 S0 5 Input Select Inputs. When Control register [1,0] = 00, S0 and S1 pins are used to select DAC input data from EEPROM. SCL 6 Input I2C Serial Clock Input SDA 7 Input/Output I2C Serial Data Input/Output A0 8 Input Address Input. This pin determines I 2C slave address of the DS3510. VCC 9 Power Digital Supply (2.7V to 5.5V) VRH, VRL 10, 11 Reference Input VCOM Reference Inputs. High-voltage reference for V COM DAC. N.C. 12–17, 23, 36, 37, 44–48 — No Connect ion VCAP 18 Input Compensation Capacitor Input. Connect VCAP to GND through a 0.1µF capacitor. GLL, GLM 21, 22 Reference Input References for Low-Voltage Gamma DAC GM1–GM5 25–29 Output Low-Voltage Gamma Analog Outputs VCOM 30 Output VCOM Analog Output. This output requires a 1µF capacitor to GND. GM6–GM10 31–35 Output High-Voltage Gamma Analog Outputs GHM, GHH 41, 39 Reference Input References for High-Voltage Gamma DAC GND EP — Ground. Exposed pad. Connect to GND.
I2C Gamma and VCOM Buffer with EEPROM Block Diagram LATCH B LATCH A MUX 8-BIT□ DAC MODE1 BIT MODE0 BIT LD GHM GHH
8 BITS
8-BIT□ DAC MODE1 BIT MODE0 BIT LD GHM GHH 8-BIT□ DAC MODE1 BIT MODE0 BIT LD GLL GLM 8-BIT□ DAC MODE1 BIT MODE0 BIT LD GLL GLM 8-BIT□ DAC MODE1 BIT MODE0 BIT LD VRL VRH LOGIC□ AND□ CONTROL MODE0 BIT (CR.0) I2C INTERFACE I2C COMPENSATION COMP MODE1 BIT (CR.1) S0/S1 PINS S0/S1 BITS (SOFT S0/S1) LD SDA SCL LD VCAP VDD VDD VCC VCC GND DS3510
or using the SOFT S0/S1 bits in the Soft S0/S1 register. to simultaneously update each channel’s DAC output. SRAM (volatile), allowing quick and unlimited updates. features of the DS3510 follows. ing of the DAC update depends on the state of LD pin. es the selected DAC data into Latch B. only difference being how the desired bank is selected. being cleared to 0 and, hence, powering up to Bank A.
1 X I2C Individual Channel
Table 1. DS3510 Operating Modes Table 2. DS3510 Bank Selection Table
output voltage and DAC setting is illustrated in Table 3. ting the standby bit, which is the LSB of register 51h. this state is specified as IDDQ. rent drawn from the VCC supply is specified as ICCQ. tion temperature falls below +150° C. slave address is determined by the state of the A0 pin. responding bit position in the slave address. Interface Description section. Table 3. DAC Voltage/Data Relationship for Selected Codes *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0. Figure 5. DS3510 Slave Address Byte
I2C Gamma and VCOM Buffer with EEPROM Memory Organization Memory Description The list of registers/memory contained in the DS3510 is shown in the Memory Map. Also shown for each of the registers is the memory type and accessibility, as well as the power-up default values for volatile locations and factory-programmed defaults for the NV locations. Detailed register descriptions for the registers shown in bold follow in the Detailed Register Descriptions sec- tion. Furthermore, additional information regarding reading and writing the memory is located in the I2C Serial Interface Description section. NAME ADDR (HEX) DESCRIPTION MEMORY TYPE I2C ACCESS DEFAULT (HEX) VCOM Latch A 00 Data for I 2C Control of V COM Volatile R/W 00 GM1 Latch A 01 Data for I 2C Control of GM1 Volatile R/W 00 GM2 Latch A 02 Data for I 2C Control of GM2 Volatile R/W 00 GM3 Latch A 03 Data for I 2C Control of GM3 Volatile R/W 00 GM4 Latch A 04 Data for I 2C Control of GM4 Volatile R/W 00 GM5 Latch A 05 Data for I 2C Control of GM5 Volatile R/W 00 GM6 Latch A 06 Data for I 2C Control of GM6 Volatile R/W 00 GM7 Latch A 07 Data for I 2C Control of GM7 Volatile R/W 00 GM8 Latch A 08 Data for I 2C Control of GM8 Volatile R/W 00 GM9 Latch A 09 Data for I 2C Control of GM9 Volatile R/W 00 GM10 Latch A 0A Data for I 2C Control of GM10 Volatile R/W 00 Reserved 0B–0F Reserved — — — VCOM Bank A–D 10–13 V COM EEPROM Data (4 Bytes) NV R/W 80 GM1 Bank A–D 14–17 GM1 EEPROM Data (4 Bytes) NV R/W 80 GM2 Bank A–D 18–1B GM2 EEPROM Data (4 Bytes) NV R/W 80 GM3 Bank A–D 1C–1F GM3 EEPROM Data (4 Bytes) NV R/W 80 GM4 Bank A–D 20–23 GM4 EEPROM Data (4 Bytes) NV R/W 80 GM5 Bank A–D 24–27 GM5 EEPROM Data (4 Bytes) NV R/W 80 GM6 Bank A–D 28–2B GM6 EEPROM Data (4 Bytes) NV R/W 80 GM7 Bank A–D 2C–2F GM7 EEPROM Data (4 Bytes) NV R/W 80 GM8 Bank A–D 30–33 GM8 EEPROM Data (4 Bytes) NV R/W 80 GM9 Bank A–D 34–37 GM9 EEPROM Data (4 Bytes) NV R/W 80 GM10 Bank A–D 38–3B GM10 EEPROM Data (4 Bytes) NV R/W 80 Reserved 3C–4F Reserved — — — Soft S0/S1 50 Software Bank Select Bits Volatile R/W 00 Standby 51 Standby (xxxxxxx, Standby) Volatile R/W 00 Reserved 52–56 Reserved — — — Status 57 Status Bit s (LD, xxxxx, S1, S0) Status R N/A Reserved 58–5F Reserved — — — Control Register (CR) 60 Control Register NV R/W 10 Reserved 61–FF Reserved — — — Memory Map
I2C Gamma and VCOM Buffer with EEPROM Detailed Register Descriptions SOFT S0/S1 50h: SOFT S1/S0 Bits FACTORY DEFAULT 00h MEMORY TYPE Volatile 50h x x x x x x SOFT S1 SOFT S0 bit7 bit0 bit7:2 Reserved bit1, bit0 These bits are used when in SOFT S0/S1 (bit) Controlled Bank Updating Mode (MODE1 = 0, MODE0 = 1) SOFT S1, SOFT S0: 00 = Selects V COM and GM1–GM10 Bank A 01 = Selects V COM and GM1–GM10 Bank B 10 = Selects V COM and GM1–GM10 Bank C 11 = Selects V COM and GM1–GM10 Bank D STANDBY 51h: Standby Mode Enable FACTORY DEFAULT 00h MEMORY TYPE Volatile 51h x x x x x x x Standby bit7 bit0 bit7:1 Reserved bit0 Standby: 0 = Standby Mode Disabl ed 1 = Standby Mode Enabled STATUS 57h: Real-Time Indicator of Logic State on LD, S1, and S0 Pins FACTORY DEFAULT — MEMORY TYPE Read Only 57h LD x x x x x S1 S0 bit7 bit0
I2C Gamma and VCOM Buffer with EEPROM I2C Serial Interface Description I2C Definitions The following terminology is commonly used to describe I2C data transfers. (See Figure 4 and I2C Electrical Characteristicsfor additional information.) Master device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave devices: Slave devices send and receive data at the master’s request. Bus idle or not busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. START condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. STOP condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. Repeated START condition: The master can use a repeated START condition at the end of one data trans- fer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a nor- mal START condition. Bit write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements. Data is shifted into the device during the rising edge of the SCL. Bit read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledge (ACK and NACK): An Acknowledge (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a 0 during the 9th bit. A device performs a NACK by trans- mitting a 1 during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or indicates that the device is not receiving data. CONTROL REGISTER 60h: Control Register (CR) FACTORY DEFAULT 10h MEMORY TYPE NV 60h x x BIAS1 BIAS0 x x MODE1 MODE0 bit7 bit0 bit7:6 Reserved bit5:4 VCOM and Gamma Bias Current Control Bits: 00 = 150% 01 = 100% (default) 10 = 80% 11 = 60% bits3:2 Reserved bits1:0 DS3510 Mode: 00 = S0/S1 Pins are Used to Select the Desired Bank (A–D) (Default) 01 = Soft S0/S1 (Bits) Are Used to Select the Desired Bank (A–D) 1X = Latch A Is Used to Control the DACs
Byte write: A byte write consists of 8 bits of information transferred from the master to the slave (most signifi- cant bit first) plus a 1-bit acknowledgment from the slave to the master. The 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgment is read using the bit read definition. Byte read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to ter- minate communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I 2C bus responds to a slave address byte sent immediately fol- lowing a start condition. The slave address byte con- tains the slave address in the most significant 7 bits and the R/ W bit in the least significant bit. The DS3510’s slave address is determined by the state of the A0 address pin as shown in Figure 5. An address pin connected to GND results in a 0 in the correspond- ing bit position in the slave address. Conversely, an address pin connected to V CC results in a 1 in the cor- responding bit position. When the R/ W bit is 0 (such as in C0h), the master is indicating it will write data to the slave. If R/ W is set to a 1, (C1h in this case), the master is indicating it wants to read from the slave. If an incorrect (non-matching) slave address is written, the DS3510 will assume the master is communicating with another I 2C device and ignore the communication until the next start condition is sent. Memory address: During an I2C write operation to the DS3510, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. I2C Communication Writing a single byte to a slave: The master must gen- erate a START condition, write the slave address byte (R/ W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave’s acknowledgment during all byte write operations. When writing to the DS3510 (and if LD = 1), the DAC will adjust to the new setting once it has acknowledged the new data that is being written, and the EEPROM (used to make the setting nonvolatile) will be written following the STOP condition at the end of the write command. Writing multiple bytes to a slave: To write multiple bytes to a slave in one transaction, the master gener- ates a START condition, writes the slave address byte (R/ W = 0), writes the memory address, writes up to 8 data bytes, and generates a STOP condition. The DS3510 is capable of writing 1 to 8 bytes (1 page or row) in a single write transaction. This is internally con - trolled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory map). The first page begins at address 00h and subsequent pages begin at multiples of 8 (08h, 10h, 18h, etc). Attempts to write to additional pages of memory without sending a STOP condition between pages results in the address counter wrap - ping around to the beginning of the present row. To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, then wait for the bus-free or EEPROM-write time to elapse. Then the master can generate a new START condition and write the slave address byte (R/ W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge polling: Any time a EEPROM byte is written, the DS3510 requires the EEPROM write time W) after the STOP condition to write the contents of the byte to EEPROM. During the EEPROM write time, the device will not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS3510, which allows communication to continue as soon as the DS3510 is ready. The alternative to acknowledge polling is to wait for a maximum period of t W to elapse before attempting to access the device. DS3510 I2C Gamma and VCOM Buffer with EEPROM
a specified memory location. of the transfer and generates a STOP condition. *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0. Figure 6. I2C Communication Examples
I2C Gamma and VCOM Buffer with EEPROM Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. Applications Information Power-Supply Decoupling To achieve the best results when using the DS3510, decouple all the power-supply pins (VCC and VDD) with a 0.01µF or 0.1µF capacitor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount com- ponents minimize lead inductance, which improves per- formance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. SDA and SCL Pullup Resistors SDA is an I/O with an open-collector output that requires a pullup resistor to realize high-logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the I2C Electrical Characteristics are within specification. A typ- ical value for the pullup resistors is 4.7kΩ . Typical Operating Circuit DS3510□ VCC SCL SDA GND GM1 GM2 GM3 GM4 GM5 GM7 GM8 GM6 GM9 GM10 VRH VCOM VDD□ 15V□ GLL□ 0.2V□ GLM□ 7V□ GHM 8V□ GHH 14.8V□ VRL 2V7.5V I2C MASTER□ SOURCE DRIVER LCD□ TOP VIEW DS3510 TQFN (7mm ×× 7mm ×× 0.8mm) 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 *EP *EXPOSED PAD GM1 GM2 GM3 GM4 GM5 V COM GM6 GM7 GM8 GM9 GM10 N.C. N.C. VRL VRH VCC SDA SCL LD GND VDD VDD N.C. GLM GLL VDD VDD VCAP N.C. N.C. N.C. N.C. N.C. N.C. GND GHH GND GMH GND GND N.C. N.C. N.C. N.C. N.C. Pin Configuration Package Information (For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE TYPE PACKAGE CODE DOCUMENT NO.