DS3502 MAXIM | Alldatasheet
Document overview
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Technical content
Features
♦ 128 Wiper Tap Points ♦ Full-Scale Resistance: 10kΩ ♦ I2C-Compatible Serial Interface ♦ Address Pins Allow Up to Four DS3502s to Share the Same I2C Bus ♦ Digital Operating Voltage: 2.5V to 5.5V ♦ Analog Operating Voltage: 4.5V to 15.5V ♦ Operating Temperature: -40°C to +100°C ♦ 10-Pin µSOP Package +Denotes a lead-free package. T&R = Tape and reel.
Ordering Information
PART TEMP RANGE PIN-PACKAGE DS3502U+ -40°C to +100°C 10 μSOP DS3502U+T&R -40°C to +100°C 10 μSOP 7-BIT WIPER REGISTER 7-BIT NONVOLATILE MEMORY CONTROL CIRCUITRY AND ADDRESS DECODEA1 DECODER LEVEL SHIFTER 127 126 125 RH RL RW SDA SCL DS3502 Functional Diagram Pin Configuration and Typical Operating Circuit appear at end of data sheet.
High-Voltage, NV, I2C POT ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +100°C) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on SDA, SCL, A0, A1 CC + 0.5V), not to exceed 6.0V J-STD-020 Specification. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC (Note 1) +2.5 +5.5 V V+ Voltage V+ V+ > V CC +4.5 +15.5 V Input Logic 1 (SCL, SDA, A0, A1) VIH 0.7 x VCC VCC + 0.3 V Input Logic 0 (SCL, SDA, A0, A1) VIL -0.3 0.3 x VCC V Resistor Inputs (RL, RW, RH) V RES -0.3 +15.5 V Wiper Current I WIPER 1 mA
ELECTRICAL CHARACTERISTICS
(VCC = +2.5V to +5.5V, TA = -40°C to +100°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC Supply Current I CC (Note 2) 0.2 3 mA Standby Supply Current I STBY (Note 3) 10 μA V+ Bias Current I V+ +1 μA Input Leakage (SDA, SCL, A0, A1) I L -1 +1 μA Wiper Response Time t WRS 1 μs Low-Level Output Voltage (SDA) V OL 3mA sink current 0.0 0.4 V I/O Capacitance C I/O 5 10 pF Power-Up Recall Voltage V POR (Note 4) 1.2 2.6 V Power-Up Memory Recall Delay t D (Note 5) 3 ms Wiper Resistance R W V+ = 15.0V 5000 End-to-End Resistance (RH to RL) R TOTAL 10 k RTOTAL Tolerance T A = +25°C -20 +20 % CH, CL, CW Capacitance C POT 10 pF
High-Voltage, NV, I2C POT VOLTAGE-DIVIDER CHARACTERISTICS (VCC = +2.5V to +5.5V, TA = -40°C to +100°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Integral Nonlinearity INL (Note 6) -1 +1 LSB Differential Nonlinearity DNL (Note 7) -0.5 +0.5 LSB Zero-Scale Error ZS ERROR V+ = 4.5V (Note 8) 0 0.5 2 LSB Full-Scale Error FS ERROR V+ = 4.5V (Note 9) -2 -1 0 LSB Ratiometric Temp Coefficient TCV WR/IVR register set to 40h ±4 ppm/°C I2C AC ELECTRICAL CHARACTERISTICS (VCC = +2.5V to +5.5V, TA = -40°C to +100°C, timing referenced to V IL(MAX) and VIH(MIN). See Figure 2.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency f SCL (Note 10) 0 400 kHz Bus Free Time Between STOP and START Conditions tBUF 1.3 μs Hold Time (Repeated) START Condition tHD:STA 0.6 μs Low Period of SCL t LOW 1.3 μs High Period of SCL t HIGH 0.6 μs Data Hold Time t HD:DAT 0 0.9 μs Data Setup Time t SU:DAT 100 ns START Setup Time t SU:STA 0.6 μs SDA and SCL Rise Time t R (Note 11) 20 + 0.1CB 300 ns SDA and SCL Fall Time t F (Note 11) 20 + 0.1CB 300 ns STOP Setup Time t SU:STO 0.6 μs SDA and SCL Capacitive Loading CB (Note 11) 400 pF EEPROM Write Time t W (Note 12) 10 20 ms Pulse-Width Suppression Time at SDA and SCL Inputs tIN (Note 13) 50 ns A0, A1 Setup Time t SU:A Before START 0.6 μs A0, A1 Hold Time t HD:A After STOP 0.6 μs SDA and SCL Input Buffer Hysteresis 0.05 x VCC V
High-Voltage, NV, I2C POT NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.5V to +5.5V) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TA = +70°C 50,000EEPROM Write Cycles TA = +25°C 200,000 Writes Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative. Note 2: ICC is specified with the following conditions: SCL = 400kHz, SDA pulled up, and RL, RW, RH floating. Note 3: ISTBY is specified with SDA = SCL = VCC = 5.5V and resistor pins floating. Note 4: This is the minimum VCC voltage that causes NV memory to be recalled. Note 5: This is the time from VCC > VPOR until initial memory recall is complete. Note 6: Integral nonlinearity is the deviation of a measured resistor setting value from the expected values at each particular resis- tor setting. Expected value is calculated by connecting a straight line from the measured minimum setting to the mea- Note 7: Differential nonlinearity is the deviation of the step-size change between two LSB settings from the expected step size. The expected LSB step size is the slope of the straight line from measured minimum position to measured maximum posi- Note 8: ZS error = code 0 wiper voltage divided by one LSB (ideal). Note 9: FS error = (code 127 wiper voltage - V+) divided by one LSB (ideal). Note 10: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard mode timing. Note 11: CB—total capacitance of one bus line in picofarads. Note 12: EEPROM write time begins after a STOP condition occurs. Note 13: Pulses narrower than max are suppressed.
High-Voltage, NV, I2C POT Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Pin Description NAME PIN FUNCTION SDA 1 I 2C Serial Data. Input/output for I 2C data. GND 2 Ground Terminal VCC 3 Supply Voltage Terminal A1, A0 4, 5 Address Select Inputs. Determines I 2C slave address. Slave address is 01010A 1A0X. (See the Slave Address Byte and Address Pins section for details). RH 6 High Terminal of Potentiometer RW 7 Wiper Terminal of Potentiometer RL 8 Low Terminal of Potentiometer V+ 9 Wiper Bias Voltage SCL 10 I 2C Serial Clock. Input for I 2C clock. SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3502 toc01 SUPPLY VOLTAGE (V) SUPPLY CURRENT (μA) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.5 5.5 SDA = SCL = VCC, V+ = 15.5V RW, RH, AND RL ARE FLOATING SUPPLY CURRENT vs. TEMPERATURE DS3502 toc02 TEMPERATURE (°C) SUPPLY CURRENT (μA) 806040200-20 1.1 1.2 1.3 1.4 1.5 1.0 -40 100 SDA = SCL = VCC = 5V, V+ = 15.5V RW, RH, AND RL ARE FLOATING INTEGRAL NONLINEARITY vs. POTENTIOMETER SETTING DS3502 toc03 POTENTIOMETER SETTING (DEC) INTEGRAL NONLINEARITY (LSB) 12010060 804020 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 1.0 -1.0 DIFFERENTIAL NONLINEARITY vs. POTENTIOMETER SETTING DS3502 toc04 POTENTIOMETER SETTING (DEC) DIFFERENTIAL NONLINEARITY (LSB) 12010060 804020 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 -0.5
of the potentiometer’s wiper. I2C reads from address 00h read from WR. I2C reads from address 00h read from WR. of address 00h return the contents of the WR register. ting the device into MODE = 0. where WR is the wiper position in decimal (0–127). Table 1. Memory Map
High-Voltage, NV, I2C POT data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledge (ACK and NACK): An Acknowledge (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a 0 during the 9th bit. A device performs a NACK by trans- mitting a 1 during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or indicates that the device is not receiving data. Byte write: A byte write consists of 8 bits of information transferred from the master to the slave (most signifi- cant bit first) plus a 1-bit acknowledgment from the slave to the master. The 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgment is read using the bit read definition. Byte read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to ter- minate communication so the slave will return control of SDA to the master. Slave address byte: Each slave on the I 2C bus responds to a slave address byte sent immediately fol- lowing a START condition. The slave address byte con- tains the slave address in the most significant 7 bits and the R/ W bit in the least significant bit. The slave address byte of the DS3502 is shown in Figure 1. When the R/ W bit is 0 (such as in 50h), the master is indicating it will write data to the slave. If R/ W = 1 (51h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS3502 assumes the master is communicating with another I device and ignores the communication until the next START condition is sent. Memory address: During an I 2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte trans- mitted during a write operation following the slave address byte. I2C Communication Writing a single byte to a slave: The master must gen- erate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave’s acknowledgment during all byte write operations. When writing to the DS3502, the potentiometer adjusts to the new setting once it has acknowledged the new data that is being written, and the EEPROM is written following the STOP condition at the end of the write command. To change the setting without changing the EEPROM, termi- nate the write with a repeated START condition before the next STOP condition occurs. Using a repeated START condition prevents the t W delay required for the EEPROM write cycle to finish. Acknowledge polling: Any time a EEPROM byte is written, the DS3502 requires the EEPROM write time W) after the STOP condition to write the contents of the byte to EEPROM. During the EEPROM write time, the device will not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS3502, which allows communication to continue as soon as the DS3502 is ready. The alternative to acknowledge polling is to wait for a maximum period of t W to elapse before attempting to access the device. EEPROM write cycles: The DS3502’s EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature (hot) as well as at room tem- perature. Writing to the WR/IVR register with MODE = 1 does not count as a EEPROM write. Reading a single byte from a slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read opera- tion occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. However, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location.
START condition to specify the starting memory location. frequency response for decoupling applications. ical value for the pullup resistors is 4.7kΩ. EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE CONNECTED TO GND). *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1. Figure 3. I2C Communication Examples
High-Voltage, NV, I2C POT Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. VCC 2.5V GND RL RW V+ RH SCL I2C CLCD VCOM R1 G1 B1 GATE 1 GATE 2 GATE 3 CSTOR TFT 15.0V SDA DS3502 Typical Operating Circuit TOP VIEW SCL RL RWA1 VCC GND SDA RHA0 DS3502 Pin Configuration Package Information For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE DOCUMENT NO. 10 µSOP 21-0061