DS3501

DS3501 MAXIM | Alldatasheet

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Technical content

Features

♦ 128 Wiper Tap Points ♦ Full-Scale Resistance: 10kΩ ♦ On-Chip Temperature Sensor and ADC ♦ 36-Byte Lookup Table (LUT) ♦ I2C-Compatible Serial Interface ♦ Address Pins Allow Up to Four DS3501s to Share the Same I2C Bus ♦ Digital Operating Voltage: 2.7V to 5.5V ♦ Analog Operating Voltage: 4.5V to 15.5V ♦ Operating Temperature: -40°C to +100°C ♦ Pin and Software Compatible with ISL95311 (Default Mode) ♦ 10-Pin μSOP Package DS3501 High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table Rev 0; 1/07 +Denotes a lead-free package. T&R denotes tape-and-reel.

Ordering Information

PART TEMP RANGE PIN-PACKAGE DS3501U+ -40°C to +100°C 10 µSOP DS3501U+T&R -40°C to +100°C 10 µSOP VOLATILE WIPER REGISTER NV IVR 36-BYTE LUT NV MEMORY CONTROL CIRCUITRY AND ADDRESS DECODE TEMP SENSOR AND ADC SDA SCL DECODER LEVEL SHIFTER 127 126 125 RH RL RW DS3501 Functional Diagram Pin Configuration and Typical Operating Circuit appear at end of data sheet. For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +100°C) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on SDA, SCL, A0, A1 CC + 0.5V), not to exceed 6.0V J-STD-020 Specification PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC (Note 1) +2.7 +5.5 V V+ Voltage V+ V+ > V CC +4.5 +15.5 V Input Logic 1 (SCL, SDA, A0, A1) VIH 0.7 x VCC VCC + 0.3 V Input Logic 0 (SCL, SDA, A0, A1) VIL -0.3 0.3 x VCC V Resistor Inputs (RL, RW, RH) V RES -0.3 V+ + 0.3 V Wiper Current I WIPER 1m A DC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40°C to +100°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ICC (Note 2) 2 mAVCC Supply Current ICC2 (Note 3) 250 350 µA Standby Supply Current I STBY (Note 4) 40 60 µA V+ Bias Current I V+ +1 µA Inp ut Leakag e ( S D A, S C L, A0, A1) I L -1 +1 µA Low-Level Output Voltage (SDA) V OL 3mA sink current 0.0 0.4 V I/O Capacitance C I/O 51 0p F Power-Up Recall Voltage V POR (Note 5) 1.6 2.6 V Power-Up Memory Recall Delay t D (Note 6) 5 ms Wiper Resistance R W V+ = 15.0V 5000 Ω E nd - to- E nd Resi stance ( RH to RL) R TOTAL 10 k Ω RTOTAL Tolerance T A = +25°C -20 +20 % RTOTAL Temp Co. (Note 7) ±200 ppm CH, CL, CW Capacitance C POT 10 pF

High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table ANALOG VOLTAGE MONITORING CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40°C to +100°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Resolution LSB Full-scale voltage of 6.5536V 25.6 mV Input/Supply Accuracy A CC At factory setting 0.25 1 % FS (Full Scale) Input Supply Offset V OS (Note 7) 0 5 LSB Update Rate (Temperature and Supply Conversion Time) tFRAME 16 ms TEMPERATURE SENSOR CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40°C to +100°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Temperature Error ±5 °C Update Rate (Temperature and Supply Conversion Time) tFRAME 16 ms VOLTAGE-DIVIDER CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40°C to +100°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Integral Nonlinearity INL (Note 8) -1 +1 LSB Differential Nonlinearity DNL (Note 9) -0.5 +0.5 LSB Zero-Scale Error ZS ERROR V+ = 4.5V (Note 10) 0 0.5 2 LSB Full-Scale Error FS ERROR V+ = 4.5V (Note 11) -2 -0.003 0 LSB Ratiometric Temp Coefficient TCV WR set to 40h ±4 ppm/°C I2C AC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40°C to +100°C, timing referenced to V IL(MAX) and VIH(MIN). See Figure 3.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency f SCL (Note 12) 0 400 kHz Bus Free Time Between STOP and START Conditions tBUF 1.3 µs Hold Time (Repeated) START Condition tHD:STA 0.6 µs Low Period of SCL t LOW 1.3 µs High Period of SCL t HIGH 0.6 µs

High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.7V to +5.5V) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TA = +70°C 50,000EEPROM Write Cycles TA = +25°C 200,000 Writes Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are nega- tive. Note 2: ICC is specified with the following conditions: SCL = 400kHz; SDA pulled up; and RL, RW, RH floating. Note 3: ICC is specified with the following conditions: SCL, SDA pulled up; RL, RW, RH floating; and temperature sensor on. Note 4: ISTBY is specified with SDA = SCL = VCC = 5.5V, resistor pins floating, and CR2 bit 0 = logic-high. Note 5: This is the minimum VCC voltage that causes NV memory to be recalled. Note 6: This is the time from VCC > VPOR until initial memory recall is complete. Note 7: Guaranteed by design. Note 8: Integral nonlinearity is the deviation of a measured resistor setting value from the expected values at each particular resis- tor setting. Expected value is calculated by connecting a straight line from the measured minimum setting to the measured Note 9: Differential nonlinearity is the deviation of the step-size change between two LSB settings from the expected step size. The expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position. DNL = [V(RW)i+1 - (V(RW)i] / LSB(ideal) - 1, for i = 0...126. Note 10: ZS error = code 0 wiper voltage divided by one LSB(ideal). Note 11: FS error = (code 127 wiper voltage - V+) divided by one LSB (ideal). Note 12: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I 2C standard mode timing. Note 13: CB—total capacitance of one bus line in picofarads. Note 14: EEPROM write time begins after a STOP condition occurs. Note 15: Pulses narrower than max are suppressed. I2C AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +2.7V to +5.5V, TA = -40°C to +100°C, timing referenced to V IL(MAX) and VIH(MIN). See Figure 3.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Data Hold Time t HD:DAT 0 0.9 µs Data Setup Time t SU:DAT 100 ns START Setup Time t SU:STA 0.6 µs SDA and SCL Rise Time t R (Note 13) 20 + 0.1CB 300 ns SDA and SCL Fall Time t F (Note 13) 20 + 0.1CB 300 ns STOP Setup Time t SU:STO 0.6 µs SDA and SCL Capacitive Loading CB (Note 13) 400 pF EEPROM Write Time t W (Note 14) 10 20 ms Pulse-Width Suppression Time at SDA and SCL Inputs tIN (Note 15) 50 ns A0, A1 Setup Time t SU:A Before START 0.6 µs A0, A1 Hold Time t HD:A After STOP 0.6 µs SDA and SCL Input Buffer Hysteresis 0.05 x VCC V

High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) 120 170 220 -40 0 -20 20 40 60 80 100 SUPPLY CURRENT vs. TEMPERATURE DS3501 toc01 TEMPERATURE (°C) SUPPLY CURRENT (μA) LUT MODE DEFAULT MODE V+ = 15.5V, VCC = 5V SDA = SCL = VCC; RH, RL, RW ARE FLOATING 170 120 220 SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3501 toc02 SUPPLY VOLTAGE (V) SUPPLY CURRENT (μA) 2.7 4.1 5.5 LUT MODE DEFAULT MODE V+ = 15.5V SDA = SCL = VCC; RL, RH, RW ARE FLOATING -40 20 40-20 0 60 80 100 STANDBY SUPPLY CURRENT vs. TEMPERATURE DS3501 toc03 TEMPERATURE (°C) STANDBY SUPPLY CURRENT (μA) LUT MODE DEFAULT MODE V+ = 15.5V, VCC = 5V SDA = SCL = VCC; RH, RL, RW ARE FLOATING -0.75 -0.50 -0.25 0.25 0.50 0.75 03 2 16 48 64 80 96 112 INTEGRAL NONLINEARITY vs. POTENTIOMETER SETTING DS3501 toc04 POTENTIOMETER SETTING (DEC) INTEGRAL NONLINEARITY (LSB) -0.75 -0.50 -0.25 0.25 0.50 0.75 03 2 16 48 64 80 96 112 DIFFERENTIAL NONLINEARITY vs. POTENTIOMETER SETTING DS3501 toc05 POTENTIOMETER SETTING (DEC) DIFFERENTIAL NONLINEARITY (LSB) Pin Description NAME PIN DESCRIPTION SDA 1 I 2C Serial Data. Input/output for I2C data. GND 2 Ground Terminal VCC 3 Supply Voltage Terminal A1, A0 4, 5 Address Select Inputs. Determines I2C slave address. Slave address is 01010A1A0X. (See the Slave Address Byte and Address Pins section for details). RH 6 High Terminal of Potentiometer RW 7 Wiper Terminal of Potentiometer RL 8 Low Terminal of Potentiometer V+ 9 Wiper Bias Voltage SCL 10 I 2C Serial Clock. Input for I2C clock.

High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table I2C INTERFACE WIPER REGISTER/ INITIAL VALUE REGISTER (WR/IVR) 00h VCC SDA CONTROL LOGIC/ REGISTERS RH RL POS 7Fh POS 00h GND SCL SEE BIT RW DS3501 Default Mode Block Diagram (Update Mode bit = 0) I2C INTERFACE LUT ADDRESS REGISTER CONTROL LOGIC/ REGISTERS ADC VCC SDA GND SCL TEMP SENSOR VCC VOLTAGE TEMP 0Ch VCC (V) 0Eh DATA CONTROL RH RL POS 7Fh POS 00h RW (LUTAR) 08h

36 BYTE

(LUT) 80h-A3h WIPER REGISTER (WR) 09h* INITIAL VALUE REGISTER (IVR) 00h* ON POWER-UP ONLY WHEN IN LUT-ADDER MODE IVR LUTVAL OR LUTVAL+IVR LUTVAL *NOTE THAT WHEN IN LUT OR LUT ADDER MODE, WR IS ACCESSED THROUGH 09h (UNLIKE DEFAULT MODE) WHILE IVR REMAINS AT 00h. DS3501 LUT and LUT Adder Mode Block Diagram (Update Mode bit = 1) Block Diagrams

where WR is the wiper position in decimal (0–127). two’s complement format with a resolution of 1°C/bit. See below for the temperature sensor’s bit weights. equal to 128, subtract 256 from the result. surement can be read over I2C at the address 0Eh. Characteristics electrical table. bit = 0, hence configuring the DS3501 in Default Mode. controlled by the Shadow EEPROM ( SEE) bit, CR0.7. volatile and its power-up default state is 0.

0 X Default Mode (default)

Table 1. DS3501 Operating Modes

at the location pointed to by LUTAR is called LUTVAL. updating the wiper setting in a closed-loop fashion. settings for each four-degree temperature window. Table 2. Default Mode Memory Map *In Default Mode, both WR and IVR are accessed through memory location 00h. Refer to the Default Mode section for additional information. Table 3. LUT Mode and LUT Adder Mode Memory Map *In LUT Mode and LUT Adder Mode, the WR is accessed through memory address 09h, while IVR remains at memory address 00h.

negative offsetting of the nominal IVR value. Figure 1. LUT Hysteresis bit1 Adder Mode: This bit is valid only if the Update Mode bit = 1. 0 = Sets the DS3501 to LUT Mode. 1 = Sets the DS3501 to LUT Adder Mode. 0 = Sets the DS3501 to Default Mode. In this mode the DS3501 is compatible with the ISL95311 (default). 1 = Sets the DS3501 to one of the two LUT-based modes depending on the Adder Mode bit. bit7 SEE: Controls functionality of shadowed NV registers (such as the WR/IVR register). 0 = Data written to shadowed NV memory is stored in both SRAM and EEPROM (default). 1 = Data written to shadowed NV memory is stored only in SRAM. The DS3501 contains three control registers (CR0, CR1, and CR2) used to configure and control modes and features.

possible current consumption mode. clock pulses and START and STOP conditions. bit2 TEN: Temperature Update Enable bar. This bit is valid only in LUT Mode and LUT Adder Mode. 1 = Places the potentiometer in manual mode allowing WR (09h) to be written using I2C. bit1 AEN: Address Update Enable bar. This bit is valid only in LUT Mode and LUT Adder Mode. corresponding location in the LUT. exercise LUT values and functionality. is still active in this state. *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1. Figure 2. DS3501 Slave Address Byte

the master to initiate a new data transfer with a slave. high generates a START condition. device during the rising edge of the SCL. indicates that the device is not receiving data. acknowledgment is read using the bit read definition. NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN). Figure 3. I2C Timing Diagram

High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table minate communication so the slave will return control of SDA to the master. Slave address byte: Each slave on the I 2C bus responds to a slave address byte sent immediately fol- lowing a START condition. The slave address byte con- tains the slave address in the most significant 7 bits and the R/ W bit in the least significant bit. The slave address byte of the DS3501 is shown in Figure 2. When the R/ W bit is 0 (such as in 50h), the master is indicating it will write data to the slave. If R/ W = 1 (51h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS3501 assumes the master is communicating with another I device and ignores the communication until the next START condition is sent. Memory address: During an I 2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte trans- mitted during a write operation following the slave address byte. I2C Communication Writing a single byte to a slave: The master must gen- erate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave’s acknowledgment during all byte write operations. When writing to the DS3501, the potentiometer will adjust to the new setting once it has acknowledged the new data that is being written, and the EEPROM (if SEE = 0) will be written following the STOP condition at the end of the write command. To change the setting without changing the EEPROM, terminate the write with a repeat- ed START condition before the next STOP condition occurs. Using a repeated START condition prevents the t W delay required for the EEPROM write cycle to finish. Writing multiple bytes to a slave: To write multiple bytes to a slave in one transaction, the master gener- ates a START condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a STOP condition. The DS3501 is capable of writing 1 to 8 bytes (1 page or row) in a single write transaction. This is internally con- trolled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory map). The first page begins at address 00h and subsequent pages begin at multiples of 8 (08h, 10h, 18h, etc). Attempts to write to additional pages of memory without sending a STOP condition between pages results in the address counter wrap- ping around to the beginning of the present row. To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, then wait for the bus-free or EEPROM-write time to elapse. Then the master can generate a new START condition and write the slave address byte (R/ W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge polling: Any time a EEPROM byte is written, the DS3501 requires the EEPROM write time W) after the STOP condition to write the contents of the byte to EEPROM. During the EEPROM write time, the device will not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS3501, which allows communication to continue as soon as the DS3501 is ready. The alternative to acknowledge polling is to wait for a maximum period of t W to elapse before attempting to access the device. EEPROM write cycles: The DS3501’s EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature (hot) as well as at room tem- perature. Writing to shadowed EEPROM with SEE = 1 does not count as a EEPROM write. Reading a single byte from a slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read opera- tion occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. However, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. Manipulating the address counter for reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master gen- erates a START condition, writes the slave address byte (R/ W = 0), writes the memory address where it desires to read, generates a repeated START condi- tion, writes the slave address byte (R/ W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. See Figure 4 for a read example using the repeated START condition to specify the starting memory location.

the transfer and generates a STOP condition. response for decoupling applications. ical value for the pullup resistors is 4.7kΩ. EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE CONNECTED TO GND). *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1. Figure 4. I2C Communication Examples

2.7V GND RL RW V+ RH SCL I2C CLCD VCOM R1 G1 B1 GATE 1 GATE 2 GATE 3 CSTOR TFT 15.0V SDA DS3501 Typical Operating Circuit SCL RL RWA1 VCC GND SDA TOP VIEW RHA0 DS3501 Pin Configuration Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. DS3501 High-Voltage, NV, I2C POT with Temp Sensor and Lookup Table Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. Heaney