DS34RT5110SQ/NOPB

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DS34RT5110 DVI, HDMI Retimer with Input Equalization and Output De-Emphasis

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www.ti.com SNLS310G –MARCH 2009–REVISED APRIL 2013 DS34RT5110DVI,HDMIRetimerwithInputEqualizationandOutputDe-Emphasis Check forSamples: DS34RT5110 1FEATURES DESCRIPTION The DS34RT5110 isa 10.2Gbps (3x 3.4Gbps) high 2• OptimizedforHDMI/DVI RepeaterApplications performance re-clockingdevice that supports 3• TMDS compatibleInputswithConfigurable TransitionMinimized DifferentialSignaling(TMDS)Receive EqualizationSupportingData Rates datachannelsand a singleclockchanneloverDVI™ up to3.4Gbps v1.0,and HDMI ™ v1.3adataratesup to3.4Gbps for each data channel. The device incorporatesa• TMDS compatibleOutputs withConfigurable configurablereceiveequalizer,a clock and dataTransmitDe-Emphasis recovery(CDR) circuitand a de-emphasisdriveron• DedicatedCDR on Each Data Channel each data channel.The clockchannelfeedsa high-Reduces JitterTransfer,EnablingMultiple performance phase-locked loop (PLL) thatDevices tobe Cascaded withoutImpairing regeneratesa lowjitteroutputclockfordatarecovery.SignalFidelity The DS34RT5110 equalizesand retimesgreaterthan• Capable ofMulti-HopExtensionofHDMI/DVI 25 meters 28 AWG of HDMI cable for 1080pApplicationsatData Rates between 250 Mbps resolutionwith12 bitdeep colordepth(2.25Gbps),toand 3.4Gbps a low jitterversionof the clock and data signal

ResistorAdjustableDifferentialOutput Voltage outputs,reducingbothdeterministicand random jitter. Several devices can be cascaded for long linksforAC Coupled Cat5e and Cat6 Extension withoutdegradingsignalfidelity.ObtainingtotaljitterApplications is0.09UI orlessoverthesupporteddatarates.This• 2 EqualizerSettingsfora Wide Range ofCable low levelof outputjitterprovidessystem designersReaches atDifferentData Rates withextramargin and flexibilitywhen workingwith
TotalOutput Jitterof0.09UI at2.25Gbps stringenttimingbudgets.
TotalOutput Jitterof0.10UI at3.4Gbps The transmittersupportsconfigurabletransmitde-
DVI 1.0and HDMI v1.3aCompatible TMDS emphasis so the outputcan be optimizedfordriving additionallengthsofcablesorFR4 traces.Source and Sink Interface
7 mm x 7 mm 48 Pin WQFN Package
>8 kV HBM ESD Protection
0 °C to+70 °C OperatingTemperature

APPLICATIONS

RepeaterApplications – DigitalRouters – HDMI /DVI ExtenderMulti-Hops
Source Applications – Video Cards – Blu-rayDVD Players – Game Consoles
Sink Applications – High DefinitionDisplays – Projectors Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

10.2 G DVI/HDMI Sink

10.2 G DVI/HDMI Source

SNLS310G –MARCH 2009–REVISED APRIL 2013 www.ti.com ApplicationDiagram PIN DESCRIPTIONS Pin Name Pin Number I/O,Type Description High Speed DifferentialI/O C_IN− 1 I,CML Invertingand non-invertingTMDS Clockinputstotheequalizer.An on-chip50 Ω terminating C_IN+ 2 resistorconnectsC_IN+ toVDD and C_IN-toVDD . D_IN0− 4 I,CML Invertingand non-invertingTMDS Data inputstotheequalizer.An on-chip50 Ω terminating D_IN0+ 5 resistorconnectsD_IN0+ toVDD and D_IN0-toVDD . D_IN1− 8 I,CML Invertingand non-invertingTMDS Data inputstotheequalizer.An on-chip50 Ω terminating D_IN1+ 9 resistorconnectsD_IN1+ toVDD and D_IN1-toVDD . D_IN2− 11 I,CML Invertingand non-invertingTMDS Data inputstotheequalizer.An on-chip50 Ω terminating D_IN2+ 12 resistorconnectsD_IN2+ toVDD and D_IN2-toVDD . C_OUT- 36 O, CML Invertingand non-invertingTMDS outputsfromtheequalizer.Open collector. C_OUT+ 35 D_OUT0 − 33 O, CML Invertingand non-invertingTMDS outputsfromtheequalizer.Open collector. D_OUT0+ 32 D_OUT1 – 29 O, CML Invertingand non-invertingTMDS outputsfromtheequalizer.Open collector. D_OUT1+ 28 D_OUT2 − 26 O, CML Invertingand non-invertingTMDS outputsfromtheequalizer.Open collector. D_OUT2+ 25 EqualizationControl EQ2 37 I,LVCMOS EQ2, EQ1 and EQ0 selecttheequalizerboostlevelforEQ channels.InternallypulledLOW EQ1 38 as default.RefertoTable1. EQ0 39 De-Emphasis Control DE1 42 I, DE1, DE0 selecttheDE-emphasis levelforoutputdrivers.Internallypulledlowas default. DE0 43 LVCMOS RefertoTable2. Device Control BYPASS 47 I, Reclockerenablecontrol.Internallypulledlowas default. LVCMOS H = Reclockand De-Emphasis functionisbypassed. L = Normal operation. EN 44 I,LVCMOS EnableOutputDrivers.InternallypulledHIGH as default. H = normaloperation(enabled). L = standbymode. MODE 21 I,LVCMOS Clockchannelmode control.InternallypulledLOW as default. H = Clockchannelisbypassed. L = Normal operation. SD 45 O, LVCMOS SignalDetectOutputpin. H = signaldetectedon allchannels. L = no signaldetectedon one ormore channels.

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DAP = GND DS34RT5110 (Top View) D_IN2+ D_IN2- D_IN1+ D_IN1- D_IN0+ D_IN0- C_IN+ C_IN- D_OUT2+ D_OUT2- D_OUT1+ D_OUT1- D_OUT0+ D_OUT0- C_OUT+ C_OUT- VDD VDD VDD VDD GND GND GND GND VDD VDD GND GND EQ1 EQ0 BYPASS VDD SD EN LFn DE0 DE1 LFp VOD_CRL EQ2 Reserv Reserv LOCK MODE Reserv Reserv Reserv Reserv DS34RT5110 www.ti.com SNLS310G –MARCH 2009–REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O,Type Description LOCK 14 O, LVCMOS Lock IndicatorOutputpin. H = PLL islocked. L = PLL isnotlocked. VOD_CRL 48 I, VOD controlpin.RefertoTable3.See FunctionalDescription. Analog Externalresistance= 24 kΩ toGND, OutputDC CoupledApplication. Externalresistance= 12 kΩ toGND, OutputAC CoupledApplication. LFp 40 I, Loop filtercapacitorpins. LFn 41 Analog See FunctionalDescription. Power VDD 3,6,7, Power VDD = 3.3V ±5%. VDD pinsshouldbe tiedtotheVDD planethrougha lowinductancepath.A 10,13, 0.1µF bypasscapacitorshouldbe connectedbetween each VDD pintotheGND planes.See 15,46 POWER SUPPLY BYPASSING foradditionaldetails. GND 22,24, GND Ground reference.GND shouldbe tiedtoa solidgroundplanethrougha lowimpedance 27,30, path. 31,34 Exposed DAP GND Ground reference.The exposed pad atthecenterofthepackage must be connectedtothe DAP groundplane. Other Reserv 16,17, Reserved.Do notconnect.Leave open. 18,19, 20,23 Connection Diagram TOP VIEW — Not toScale

48 Pin WQFN Package

SNLS310G –MARCH 2009–REVISED APRIL 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) SupplyVoltage(VDD ) -0.5Vto4.0V LVCMOS InputVoltage -0.5Vto(VDD + 0.5)V LVCMOS OutputVoltage -0.5Vto(VDD + 0.5)V CML Input/OutputVoltage -0.5Vto(VDD + 0.5)V JunctionTemperature +125°C StorageTemperature -65°C to+150°C Lead Temp. (Soldering,5 sec.) +260°C ESD Rating HBM, 1.5kΩ,100 pF >8 kV ThermalResistanceθJA,No Airflow 33°C/W (1) “AbsoluteMaximum Ratings”aretheratingsbeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimplythat thedeviceshouldbe operatedattheselimits. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions(1)(2) Min Typ Max Units SupplyVoltage(VDD toGND) 3.135 3.3 3.465 V SupplyNoiseTolerance(100Hz to50 MHz) (3) 100 mVp-p AmbientTemperature 0 25 +70 °C (1) Typicalparametersaremeasured atVDD = 3.3V,TA = 25 °C. They areforreferencepurposes,and arenotproduction-tested. (2) Parameterisensuredby statisticalanalysisand/ordesign. (3) Allowedsupplynoise(mVp-p sinewave) attypicalcondition.

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www.ti.com SNLS310G –MARCH 2009–REVISED APRIL 2013 ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.Allparametersareensuredby test, statisticalanalysis,ordesignunlessotherwisespecified(1). Symbol Parameter Condition Min Typ Max Units Power EN = H, DeviceEnabled PRBS15 pattern, 1100 1250 mWfCLK=340 MHz RT= 50Ω toAV CC ,Figure2Power SupplyP Consumption EN = L,StandbyMode PRBS15 pattern, 850 1000 mWfCLK=340 MHz RT= 50Ω toAV CC ,Figure2 LVCMOS /LVTTL DC Specifications HighLevelInputVIH 2 VDD VVoltage Low LevelInputVIL GND 0.8 VVoltage HighLevelOutputVOH IOH = -3mA 2.4 VVoltage Low LevelOutputVOL IOL = 3 mA 0.4 VVoltage VIN = VDD ,EQ2, EQ1, EQ0, DE1, DE0, BYPASS, MODE 60 μA IIH InputHighCurrent pins(pulldown) VIN = VDD ,EN pin(pullup) -15 μA VIN = 0 V,EQ2, EQ1, EQ0, DE1, DE0, BYPASS, MODE 15 μA IIL InputLow Current pins(pulldown) VIN = 0 V,EN pin(pullup) -20 μA SignalDetect DefaultInputsignalleveltoSignalDetectHigh 80 mVp-pSDH assertSD pin DefaultInputsignalleveltoSignalDetectLow 20 mVp-pSDL deassertSD CML Inputs VTX InputVoltage Measured differentiallyatTPA,Swing (Launch 800 1000 1560 mVp-pFigure1(2) Amplitude) VICMDC DC-Coupled requirement InputCommon- Measured atTPB, VDD -0.3 VDD -0.2 VMode Voltage VINmin = 800mV, VINmax = 1200mV, Figure1 VIN Measured differentiallyatTPB,InputVoltage Figure1,3.4Gbps, Clock 150 1560 mVp-pSensitivity Pattern RIN Inputresistance IN+ toVDD and IN-toVDD 40 50 60 Ohms DifferentialoutputRLI 100 MHz – 1125 MHz 10 dBreturnloss CML Outputs Measured DC outputsatTPC, RT = 50Ω when DUT VDD isStandbyOutputVOFF offwithOUT+ and OUT- AV CC -10 AV CC + 10 mVVoltage terminatedby RT= 50Ω to AV CC ,Figure2 (1) Typicalparametersaremeasured atVDD = 3.3V,TA = 25 °C. They areforreferencepurposes,and arenotproduction-tested. (2) Parameterisensuredby statisticalanalysisand/ordesign. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS34RT5110

SNLS310G –MARCH 2009–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.Allparametersareensuredby test, statisticalanalysis,ordesignunlessotherwisespecified(1). Symbol Parameter Condition Min Typ Max Units Externalresistor= 24 kΩ at VOD_CRL pin.MeasuredDifferentialOutputVO differentiallywithOUT+ and 800 1200 mVp-pvoltageswing OUT- terminatedby RT=50 Ω toAV CC ,Figure2 Measured single-ended,Outputcommon-VOCM >1.65Gbps, Figure2, AV CC -0.35 AV CC -0.20 Vmode Voltage Figure3 20% to80% ofdifferential outputvoltage,measuredtR,tF Transitiontime 80 pswithin1”fromoutputpins, Figure3 InterPairData Differencein50% crossingChannel-to-tCCSK between channels 2 3 psChannelSkew (all 3.4Gbps, ClockPattern(2) 3 datachannels) Differencein50% crossingInterPairData between channelsofany twotPPSK ChannelsPart- 50 psdevicestoPartSkew 3.4Gbps, ClockPattern Data Channels 3.4Gbps, ClockPattern,tDD 520 psLatency Figure4 ClockChannel 3.4Gbps, ClockPattern,tCD 600 psLatency Figure4 LVCMOS Outputs tSL SD toLOCK time Figure4 10 ms BitRate fCLK ClockFrequency ClockPath(3) 25 340 MHz bR BitRate Data Paths(3) 0.25 3.4 Gbps Data Channel Random Jitter RJ Random Jitter See (3)(4)(5)(6) 3 psrms Data Channel CDR JitterGeneration Data Paths,measured atTPCTotalOutputJitterTROJ1 PRBS7, EQ [2:0]= 000 0.03 0.05 UIp-p0.25Gbps Figure1(3)(4)(5) Data Paths,measured atTPCTotalOutputJitterTROJ2 PRBS7, EQ [2:0]= 000 0.08 0.14 UIp-p1.65Gbps Figure1(3)(4)(5) Data Paths,measured atTPCTotalOutputJitterTROJ3 PRBS7, EQ [2:0]= 000 0.09 0.16 UIp-p2.25Gbps Figure1(3)(4)(5) Data Paths,measured atTPCTotalOutputJitterTROJ4 PRBS7, EQ [2:0]= 000 0.10 0.17 UIp-p3.4Gbps Figure1(3)(4)(5) 0.25Gbps datarate 0.25 MHz 1.65Gbps datarate 1.65 MHzCDR LoopBWLOOP Bandwidth 2.25Gbps datarate 2.25 MHz 3.4Gbps datarate 2.25 MHz (3) Parameterisensuredby statisticalanalysisand/ordesign. (4) Deterministicjitterismeasured atthedifferentialoutputs(TPC ofFigure1),minus thedeterministicjitterbeforethetestchannel(TPA of Figure1).Random jitterisremoved throughtheuse ofaveragingorsimilarmeans. (5) TotalJitterisdefinedas peak-to-peakdeterministicjitterfrom+ 12 timesrandom jitter(ps). (6) Random jittercontributedby theequalizerisdefinedas sq rt(JOUT 2 − JIN2).JOUT istherandom jitteratequalizeroutputsinps-rms,see TPC ofFigure1;JIN istherandom jitterattheinputoftheequalizerinps-rms,see TPA ofFigure1.

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www.ti.com SNLS310G –MARCH 2009–REVISED APRIL 2013 ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.Allparametersareensuredby test, statisticalanalysis,ordesignunlessotherwisespecified(1). Symbol Parameter Condition Min Typ Max Units Clock Channel PLL JitterGeneration TotalOutputJitter ClockPath,measured atTPCTROJ5 0.03 0.045 UIp-p25 MHz Figure1(7)(8)(9) TotalOutputJitter ClockPath,measured atTPCTROJ6 0.07 0.13 UIp-p165 MHz Figure1(7)(8)(9) TotalOutputJitter ClockPath,measured atTPCTROJ7 0.08 0.135 UIp-p225 MHz Figure1(7)(8)(9) TotalOutputJitter ClockPath,measured atTPCTROJ8 0.09 0.14 UIp-p340 MHz Figure1(7)(8)(9) (7) Parameterisensuredby statisticalanalysisand/ordesign. (8) Deterministicjitterismeasured atthedifferentialoutputs(TPC ofFigure1),minus thedeterministicjitterbeforethetestchannel(TPA of Figure1).Random jitterisremoved throughtheuse ofaveragingorsimilarmeans. (9) TotalJitterisdefinedas peak-to-peakdeterministicjitterfrom+ 12 timesrandom jitter(ps). Setup and Timing Diagrams Figure1. TestSetup Diagram Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS34RT5110

tDD, tCD OUT IN 0V 20% 80% 80% 20% OUT+ OUT- VO = (OUT+) ± (OUT-) tFtR A B VOH = VDD VOL = VDD - 500mV 0V (DIFF) Vo = 1000 mVp-p Single-ended Waveforms @ A and B Differential Waveform A - B Vocm AV cc 50Ö50Ö DS34RT5110 SNLS310G –MARCH 2009–REVISED APRIL 2013 www.ti.com Figure2. CML Output Swings atA/B (VOD_CRL = 24 kΩ) Figure3. CML Output TransitionTimes Figure4. CML Latency Delay Time

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VOD_CRL LFp LFn GND DAP VDD VDDVDD VDD VDD VDD DS34RT5110 HDMI / DVI Retimer C_IN+ C_IN- D_IN0+ C_OUT+ 3V3 TMDS INPUT PORT - 4 CHANNEL TMDS OUTPUT PORT - 4 CHANNEL Input Equalization Control 10 PF DC Couple 50 Ö Termination PLL EQ DE EN BYPASS Reserv 3V3 All Bypass CAPS 0.1 PF unless noted. 10 PF VDD Output De-E Control D_IN0- D_IN1+ D_IN2+ D_IN1- D_IN2- C_OUT- D_OUT0+ D_OUT0- D_OUT2+ D_OUT1+ D_OUT1- D_OUT2- VDD VDD VDD VDD Other Control Analog Pins Other Outputs MODE MODE CDR AV CC AV CC AV CC AV CC GND tSL LOCK SD 50% 50% DS34RT5110 www.ti.com SNLS310G –MARCH 2009–REVISED APRIL 2013 Figure5. SD – LOCK Delay Time FunctionalDescription The DS34RT5110 DVI,HDMI RetimerwithInputEqualizationand OutputDe-Emphasis consistsofthreedata channelsand a clockchannel.Each datachannelconsistsofa TMDS compatiblereceiverwitha power efficient equalizer,a dedicatedclock-datarecovery(CDR) unit,and a TMDS compatibletransmitter. Figure6. Block Diagram Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS34RT5110

SNLS310G –MARCH 2009–REVISED APRIL 2013 www.ti.com PHASE-LOCKED-LOCKED LOOP (PLL) The clockchannelhas a high-performancePLL thatcreatesa low jittersamplingclockfortheclockand data recoveryunitsinthedatachannels.An externalloopfilter,composed of2.2nF (+5% tolerance)capacitorand a 3.3kΩ (+5% tolerance)resistorinseries,arerequiredbetween theLFp and theLFn pins. CLOCK-DATA RECOVERY UNIT (CDR) Each TMDS datachannelhas a CDR thatoperatesindependentlyfrom otherTMDS datachannels.Each CDR alignsthe samplingclockedges by digitallyinterpolatingthe clockfrom PLL of the TMDS clockchannel.The deviceisdesignedtoconnecttoDVI/HDMI compatibletransmitterand receiveratany dataratebetween 250 data. INPUT EQUALIZATION The inputdatachannelequalizerssupporteightprogrammable levelsofequalizationboostTable1 by theEQ pins(EQ [2:0]).The range of boostsettingsprovidedenablesthe DS34RT5110 to addressa wide range of transmissionlinepathlossscenarios,enablingsupportfora varietyofdataratesand formats.See Application Informationforrecommended EQ settings. OUTPUT DE-EMPHASIS De-emphasisistheconditioningfunctionforuse incompensatingagainstbackplaneand cabletransmissionloss. The DS34RT5110 providesfourstepsofde-emphasisrangingfrom0,3,6 and 9 dB, user-selectabledependent on thelossprofileofoutputchannels.Table2 shows theDe-emphasis controlwithdefaultVO = 1000 mVp-p, and Figure7 shows a driverde-emphasiswaveform. OUTPUT VO CONTROL Outputdifferentialvoltage(VO) iscontrolledthroughVOD_CRL pintiesan externalresistorto the ground as shown inTable3.Users shouldrestricttheexternalresistorvaluesused tobe 12 kΩ to24 kΩ.+5% toleranceis recommended. Table1.EqualizationControl INPUTS RESULT EQ2 EQ1 EQ0 EqualizationindB (1.7GHz) 0 0 0 0 (default) 0 0 1 10 0 1 0 16 0 1 1 19 1 0 0 23 1 0 1 25 1 1 0 26 1 1 1 27 Table2.De-Emphasis Control INPUTS RESULT VO De-Emphasis levelinmVp-pDE1 DE0 VO De-Emphasis indB(VODE w/VOD_CRL = 24 kΩ 0 0 1000 (default) 0 (default) 0 1 710 -3 1 0 500 -6 1 1 355 -9

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1-bit 1 to N bits 1-bit 1 to N bits 0 dB -3 dB -6 dB -9 dB DS34RT5110 www.ti.com SNLS310G –MARCH 2009–REVISED APRIL 2013 Table3.VO Control ExternalResistorValue Applications VO Level(mVp-p)(VOD_CRL pin) 24 kΩ DC Coupled 1000 12 kΩ AC Coupled 1000 Figure7. Output De-Emphasis DifferentialWaveform (showing allde-emphasis steps) RETIMING AND DE-EMPHASIS BYPASS The retimingand De-emphasis BYPASS pinprovidestheflexibilitytoconfigurethedevicetoan equalizeronly mode. The deviceisinnormaloperation,when holdinga LOW stateon theBYPASS pin.The retimingand De- emphasisfeaturesaredisabled,when a HIGH stateisapplied. CLOCK CHANNEL MODE CONTROL Duringthenormaloperationmode, theclockchannelsignalisregeneratedby thePLL and theCDR. Holdinga LOW state(default)on theMODE pinplacestheDS34RT5110 inthisnormaloperationmode. A HIGH stateon theMODE pinbypassestheclockchannel.Thisclockchannelmode featureenablesthemulti-hopapplications. (RefertoMultipleHop Applicationfordetailedinformation) DEVICE STATE AND ENABLE CONTROL The DS34RT5110 has an Enable featurewhich providestheabilitytocontroldevicepower consumption.This featurecan be controlledviatheEnablePin(EN Pin).IfEnableisactivated,thedatachannelsand clockchannel are placedinthe ACTIVE stateand alldeviceblocksfunctionas described.The DS34RT5110 can alsobe placedinSTANDBY mode tosave power.Inthismode, theoutputdriversofthedevicearedisabled.The CML outputsareintheHIGH (AVCC) state.AllLVCMOS outputsareintheHiZ state. LOCK DETECT When thePLL oftheDS34RT5110 islocked,and thegeneratedreferencephases aresuccessfullyinterpolated by theCDR, thisstatusisindicatedby a logicHIGH on theLOCK pin.The LOCK pinmay be connectedtothe Enable(EN)pininputtodisablethedatachannelsand clockchannelwhen no datasignalisbeingreceived. SIGNAL DETECT The DS34RT5110 featuresa signaldetectcircuiton allchannels.The statusof the inputsignalscan be determinedby the stateof the SD pin.A logicHIGH indicatesthe presenceof signalsthathave exceeded a specifiedmaximum thresholdvalue(calledSD_ON) on allchannels.A logicLOW means thatthesignalshave fallenbelowa minimum thresholdvalue(calledSD_OFF) on one ormore channels. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS34RT5110

SNLS310G –MARCH 2009–REVISED APRIL 2013 www.ti.com AUTOMATIC ENABLE FEATURE Duringnormaloperation(i.e.BYPASS pinisLOW), theDS34RT5110 can be configuredtoautomaticallyenter STANDBY mode, ifthe PLL of the DS34RT5110 isnot locked.The STANDBY mode can be implementedby connectingthe LOCK DETECT (LOCK) pin to the external(LVCMOS) Enable (EN) pin.Ifthe LOCK pin is connectedto the EN pin,a logicHIGH on the LOCK pin willenable the device;thus the DS34RT5110 will automaticallyentertheACTIVE state.IfthePLL isunlocked,thentheLOCK pinwillbe assertedLOW, causing theaforementionedblockstobe placedintheSTANDBY state.

APPLICATION INFORMATION

The DS34RT5110 isa DVI/HDMI videosignalreconditioningdevice.The deviceconformstoDVI v1.0and HDMI v1.3astandardssupportingup to10.2Gbps totalthroughputTMDS datafor1080p with48 bitdeep colordepth. TYPICAL APPLICATION Ingeneral,theDS34RT5110 inthedefaultmode (MODE = L)isused as a DVI/HDMI sourcedevice,sinkdevice, or a repeaterdevice,see Figure8.As thesourcedevice,theoutputde-emphasissettingshouldbe configured based on thedrivingcablelength.When used as thesinkdevice,thelevelsoftheequalizationboostoftheinput datachannelsshouldbe optimizedbased on thereceivingcablelength.The DS34RT5110 can alsobe used as a repeaterinan externalextenderbox withtheequalizationand de-emphasislevelsettingsoptimizedtoprovide themaximum cablereach. Figure8. TypicalApplicationDiagram MULTIPLE HOP APPLICATION ForDVI/HDMI home theaterand professionalstudiosystemswithextensivelengthsofcable,multi-hopswith2 or more cascaded DS34RT5110 devicescan be implementedas shown inFigure9.Inordertoreachthemaximum cablelength,thelevelsoftheequalizationand de-emphasisshouldbe optimizedforeach individualhop.The MODE pin(s)ofthedeviceatthefirsthop (usingtwo hop application),oratthefirstand thesecond hops (using threehop applicationshown inFigure9) isrecommended tobe setHIGH tominimizethejitteraccumulationin multiplehops.The MODE pinofthedeviceforthefinalhop shouldbe settoa LOW statetocleanup theclock jitter,inordertodrivethemaximum cablelengthtotheSink.

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MODE = 1 MODE = 1 MODE = 0 (Default) DS34RT5110 www.ti.com SNLS310G –MARCH 2009–REVISED APRIL 2013 Figure9. MultipleHop Systems MATRIX SWITCH APPLICATION For the securitysystem withmatrixDVI/HDMI switches,the DS34RT5110 isidealto equalizethe longcable reach requirementfrom the Sources,clean the system jitterdue to the complexityof PCB routings,and regeneratecleanTMDS signalstotheSinksas shown inFigure10. Figure10. MatrixSwitch Systems DUAL LINK APPLICATION The DS34RT5110 supportsDVI duallinkapplicationsrequiringultra-highresolutionsforQXGA and WQXGA. Two DS34RT5110 devicesareconfiguredas shown inFigure11.Thisconfigurationisonlyrecommended fora singleduallinkrepeaterapplication. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS34RT5110

VOD_CRL 24 k5 VOD_CRL DS34RT5110 DS34RT5110 CLK CLK CLK MODE = 0 (Default) MODE = 1 DS34RT5110 SNLS310G –MARCH 2009–REVISED APRIL 2013 www.ti.com Figure11. DVI/HDMI Dual LinkApplication DC AND AC COUPLED APPLICATIONS The DS34RT5110 isdesignedtosupportTMDS differentialpairswithDC coupledtransmissionlines.Itcontains integratedterminationresistors(50Ω),pulledup toVDD attheinputstage,and open collectoroutputsforDVI / HDMI signaling.Figure12 shows theDC coupledconnectionbetween theHDMI Source (ie.DS34RT5110) and HDMI Sink (ie.DS34RT5110) devices.In the DC coupled application,the externalresistanceof 24 kΩ at VOD_CRL pinisused attheSource toensuretheVO levelof1000 mVp-p. The AC coupledmethod connecting between the Source and the Sink devicesmay be preferredto eliminatethe impactof the ground potential difference,or to use one CAT5/6 cablebetween two chassis.To optimizethe DS34RT5110 performance,the externalresistanceof12 kΩ attheVOD_CRL pinshouldbe used on theSource DS34RT5110, and a pairof50 Ω pull-upresistorsshouldbe placedclosetotheoutputsoftheSource DS34RT5110, inordertoDC biasthe outputdriver.Meanwhile,622Ω pull-downresistorsshouldbe placedat the inputsof the Sink DS34RT5110 device,inordertosettheinputcommon mode toa 3.05V.Note AC coupledconfigurationisnotcomplianttothe HDMI specificationofSourcerequirement(See Figure13). Figure12. DC Coupled Application

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12 k5VOD_CRL VDD 505 505 6225 6225 24 k5 VOD_CRL DS34RT5110 www.ti.com SNLS310G –MARCH 2009–REVISED APRIL 2013 Figure13. AC Coupled Application CABLE SELECTION AND INTER-PAIR SKEW DVI v1.0and HDMI v1.3aspecifyInter-PairSkew requirementsforthe system.The DS34RT5110 intendsto extendthelongercablereachwithSTP (DVI/HDMI) cable,orUTP (Cat5/Cat5e /Cat6)cable,and itdoes not have a de-skew functiontocompensate any cableInter-PairSkews. Long cablewithInter-PairSkew exceeding theDVI /HDMI standardlimittolerancecouldcause system distortion.Therefore,TIsuggeststheconsideration ofInter-PairSkew budgetduringthesystem design,and recommends Low-Skew Video grade cablesforcable extendingapplications.

28 AWG STP (SHIELDED TWIST PAIRS) DVI /HDMI CABLES RECOMMENDED EQ SETTINGS

Table 4 providesthe recommended EQ controlsettingsforvariousdata ratesand cablelengthsfor28 AWG DVI/HDMI compliantconfigurations.The EQ settingismade viathreeEQ [2:0]pins. Table4.EQ ControlSettingforSTP Cable Format(DataRate) 0 ~ 10m > 10m 1080P 48-bit(3.4Gbps) Setting0x01 Setting0x06 1080P 36-bit(2.25Gbps) Setting0x01 Setting0x06 1080P (1.65Gbps) Setting0x01 Setting0x06 1080I(750Mbps) Setting0x06 Setting0x06

24 AWG UTP (LOW SKEW UNSHIELDED TWIST PAIRS) CABLES

The DS34RT5110 can be used toextendthelengthoflow skew gradeUTP cables,such as Cat5e and Cat6 to distancesgreaterthan 30 meters at 1.65 Gbps with< 0.20 UI of jitter.Note thatfornon-standardDVI/HDMI cables,theusermust ensuretheinterpairskew requirementsare met.Table5 shows therecommended EQ controlsettingsforvariousdataratesand cablelengthsforUTP configurations. Table5.EQ ControlSettingforUTP Cable Format(DataRate) 0 ~ 10m > 10m 1080P 48-bit(3.4Gbps) Setting0x01 Setting0x05 1080P 36-bit(2.25Gbps) Setting0x01 Setting0x05 1080P (1.65Gbps) Setting0x01 Setting0x05 1080I(750Mbps) Setting0x05 Setting0x05 GeneralRecommendations The DS34RT5110 isa highperformancecircuitcapableofdeliveringexcellentperformance.To achieveoptimal performance,carefulattentionmust be paidtothedetailsassociatedwithhigh-speeddesignas wellas providing a cleanpower supply.RefertotheLVDS Owner ’s Manual formore detailedinformationon high-speeddesign tipsas wellas many otheravailableresourcesaddressingsignalintegritydesignissues. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS34RT5110

+ Clamp Circuitry DS34RT5110 SNLS310G –MARCH 2009–REVISED APRIL 2013 www.ti.com PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS The TMDS differentialinputsand outputsmust have a controlleddifferentialimpedance of100 Ω.Itispreferable torouteTMDS linesexclusivelyon one layeroftheboard,particularlyfortheinputtraces.The use ofviasshould be avoidedifpossible.Ifviasmust be used,theyshouldbe used sparinglyand must be placedsymmetricallyfor each sideofa givendifferentialpair.Route theTMDS signalsaway fromothersignalsand noisesourceson the printedcircuitboard.AlltracesofTMDS differentialinputsand outputsmust be equalinlengthtominimizeintra- pairskew. WQFN FOOTPRINT RECOMMENDATIONS See TI applicationnote:AN-1187 “LeadlessLeadframe Package (LLP)ApplicationReport” (literaturenumber SNOA401 )foradditionalinformationon WQFN packagesfootprintand solderinginformation. POWER SUPPLY BYPASSING Two approachesare recommended to ensure the DS34RT5110 isprovidedwithan adequate power supply. First,thesupply(VDD) and ground(GND) pinsshouldbe connectedtopower planesroutedon adjacentlayers of the printedcircuitboard.The layerthicknessof the dielectricshouldbe minimizedso the VDD and GND planes createa low inductancesupply with distributedcapacitance.Second, carefulattentionto supply bypassingthroughthe properuse of bypass capacitorsis required.A 0.1 μF bypass capacitorshould be connectedtoeach VDD pinsuch thatthecapacitorisplacedas closeas possibletotheDS34RT5110. Smaller body size capacitorscan help facilitateproper component placement.Additionally,two capacitorswith capacitanceintherange of2.2μF to10 μF shouldbe incorporatedinthepower supplybypassingdesignas well.These capacitorscan be eithertantalumor an ultra-lowESR ceramicand shouldbe placedas closeas possibletotheDS34RT5110. EQUIVALENT I/OSTRUCTURES Figure14 shows theDS34RT5110 CML outputstructureand ESD protectioncircuitry. Figure15 shows theDS34RT5110 CML inputstructureand ESD protectioncircuitry. Figure14. EquivalentOutput Structure Figure15. EquivalentInputStructure

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www.ti.com SNLS310G –MARCH 2009–REVISED APRIL 2013 TypicalPerformance Characteristicsas a Repeater Figure16. SimplifiedTestSetup as a SingleRepeater Figure17.System Source Eye Diagram atTPA Figure18.Device Sink Eye Diagram atTPB (3.4Gbps) (3.4Gbps, Cable A = 20m 28 AWG HDMI) Figure19.Device Source Eye Diagram atTPC Figure20.Device Source Eye Diagram atTPC (3.4Gbps, Cable A = 20m 28 AWG HDMI, (3.4Gbps, Cable A = 20m 28 AWG HDMI, EQ = 0x05,BYPASS = 0,DE = 0dB) EQ = 0x05,BYPASS = 0,DE = -3dB) Figure21.System Sink Eye Diagram atTPD Figure22.System Source Eye Diagram atTPA (3.4Gbps, Cable A = 20m 28 AWG HDMI, Cable B = 5m (2.25Gbps) 28AWG HDMI, EQ = 0x05,BYPASS = 0,DE = -3dB) Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS34RT5110

SNLS310G –MARCH 2009–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristicsas a Repeater(continued) Figure23.Device Sink Eye Diagram atTPB Figure24.Device Source Eye Diagram atTPC (2.25Gbps, Cable A = 25m 28 AWG HDMI) (2.25Gbps, Cable A = 25m 28 AWG HDMI, EQ = 0x05,BYPASS = 0,DE = 0dB) Figure25.Device Source Eye Diagram atTPC Figure26.System Sink Eye Diagram atTPD (2.25Gbps, Cable A = 25m 28 AWG HDMI, (2.25Gbps, Cable A = 25m 28 AWG HDMI, Cable B = 7.5m 28AWG HDMI, EQ = 0x05,BYPASS = 0,DE = -3dB)EQ = 0x05,BYPASS = 0,DE = -3dB) Figure27.System Source Eye Diagram atTPA Figure28.Device Sink Eye Diagram atTPB (1.65Gbps) (1.65Gbps, Cable A = 35m 28 AWG HDMI)

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www.ti.com SNLS310G –MARCH 2009–REVISED APRIL 2013 TypicalPerformance Characteristicsas a Repeater(continued) Figure29.Device Source Eye Diagram atTPC Figure30.Device Source Eye Diagram atTPC (1.65Gbps, Cable A = 35m 28 AWG HDMI, (1.65Gbps, Cable A = 35m 28 AWG HDMI, EQ = 0x05,BYPASS = 0,DE = 0dB) EQ = 0x05,BYPASS = 0,DE = -6dB) Figure31.System Sink Eye Diagram atTPD (1.65Gbps, Cable A = 35m 28 AWG HDMI, Cable B = 10m 28AWG HDMI, EQ = 0x05,BYPASS = 0,DE = -6dB) Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DS34RT5110

SNLS310G –MARCH 2009–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionF (April2013)toRevisionG Page

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www.ti.com 5-Nov-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS34RT5110SQ/NOPB NRND WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 34RT5110 DS34RT5110SQE/NOPB NRND WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 34RT5110 DS34RT5110SQX/NOPB NRND WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 34RT5110 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 5-Nov-2014 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS34RT5110SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS34RT5110SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS34RT5110SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 2

www.ti.com SQA48A (Rev B)

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