Interface

DS32EL0421SQ

Texas Instruments

5-bit DDR LVDS Parallel Data Interface

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DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 DS32EL0421,DS32ELX0421125-312.5MHzFPGA-LinkSerializerwithDDRLVDS ParallelInterface Check forSamples: DS32EL0421 ,DS32ELX0421 1FEATURES DESCRIPTION The DS32EL0421/DS32ELX0421 is a 125 MHz to 2• 5-bitDDR LVDS ParallelData Interface 312.5 MHz (DDR) serializerfor high-speedserial• Programmable TransmitDe-emphasis transmissionover FR-4 printed circuitboard

ConfigurableOutput Levels(VOD ) backplanes,balancedcables,and opticalfiber.This easy-to-usechipsetintegratesadvanced signaland• SelectableDC-balanced Encoder clockconditioningfunctions,withan FPGA friendly• SelectableData Scrambler interface.
Remote Sense forAutomatic Detectionand The DS32EL0421/DS32ELX0421 serializesup to 5NegotiationofLinkStatus parallelinputLVDS channelsto createa maximum• On Chip LC VCOs data payload of 3.125 Gbps. Ifthe integratedDC-
Redundant SerialOutput (ELX deviceonly) balance encoding is enabled,the maximum data payloadachievableis2.5Gbps.• Data ValidSignalingtoAssistwith SynchronizationofMultipleReceivers The DS32EL0421/DS32ELX0421 serializersfeature remote sense capabilityto automaticallydetectand• Supports AC- and DC-coupled Signaling negotiate link status with its companion• IntegratedCML and LVDS Terminations DS32EL0124/DS32ELX0124 deserializerswithout
ConfigurablePLL Loop Bandwidth requiringan additionalfeedbackpath.
Programmable Output Termination(50Ω or The parallelLVDS interfacereducesFPGA I/Opins,75Ω). board tracecount and alleviatesEMI issues,when
Built-inTestPatternGenerator compared to traditionalsingle-endedwide bus interfaces.• Loss ofLock and ErrorReporting
ConfigurableviaSMBus The DS32EL0421/DS32ELX0421 is programmable througha SMBus interfaceas wellas throughcontrol• 48-pinWQFN Package withExposed DAP pins. TARGET APPLICATIONS
Imaging:Industrial,MedicalSecurity,Printers
Displays:LED Walls,Commercial
Video Transport
Communication Systems
Testand Measurement
IndustrialBus KEY SPECIFICATIONS
1.25to3.125Gbps SerialData Rate
125 to312.5MHz DDR ParallelClock
-40° to+85°C Temperature Range
>8 kV ESD (HBM) Protection
Low IntrinsicJitter— 35ps at3.125Gbps Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2008–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

DC_B RS VDD25 N/C DE_EMPH0 DE_EMPH1 GPIO2 N/C VDD3336 VDD2535 SMB_CS34 SCK33 SDA LOCK RESET RSVD VDDPLL LF_CP LF_REF VDD25 N/C 24 N/C 23 N/C 22 N/C 21 N/C N/C VDD25 TXOUT0- TXOUT0+ VDD25 VOD_CTRL N/C

49 DAP = GND

3.125 Gbps Data Payload

5 LVDS

ControlPLL Parallel to Serial Encoder LVDS Clock LVDS Interface LVDS Interface Control SMBus Redundant Driver DS32ELX0124 Serial to Parallel LVDS Interface LVDS Interface PLL Control LVDS Clock Control SMBus DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com TypicalApplication Connection Diagram See Package Number RHS0048A TOP VIEW

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DC_B RS VDD25 N/C DE_EMPH0 DE_EMPH1 GPIO2 TXOUT1_EN VDD3336 VDD2535 SMB_CS34 SCK33 SDA LOCK RESET RSVD VDDPLL LF_CP LF_REF VDD25 TXIN4-48 TXIN4+47 TXIN3-46 TXIN3+45 TXIN2- TXIN2+ TXIN1- TXIN1+ TXIN0- TXIN0+ TXCLKIN- TXCLKIN+ N/C 24 N/C 23 N/C 22 N/C 21 TXOUT1- TXOUT1+ VDD25 TXOUT0- TXOUT0+ VDD25 VOD_CTRL N/C DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 See Package Number RHS0048A TOP VIEW PIN DESCRIPTIONS Pin Name Pin Number I/O,Type Description Power, Ground and Analog Reference VDD33 1,36 I,VDD 3.3Vsupply VDD25 7,15,18,25, I,VDD 2.5Vsupply VDDPLL 28 I,VDD 3.3Vsupply VOD_CTRL 14 Analog VOD control.The serializeroutputamplitudecan be adjustedby connectingthispintoa pull- down resistor.The valueoftheresistordeterminestheVOD. See CML LAUNCH AMPLITUDE formore details. LF_CP 27 Analog Loop filterconnectionforPLL LF_REF 26 Analog Loop filtergroundreference Exposed Pad 49 GND Exposed Pad must be connectedtoGND by 9 vias CML I/O TxOUT0+ 16 O, CML Invertingand non-invertinghighspeed CML differentialoutputsoftheserializer.These outputs TxOUT0- 17 areinternallyterminated. TxOUT1+ 19 O, CML DS32ELX0421 ONLY. Redundancy output.Invertingand non-invertinghighspeed CML TxOUT1- 20 differentialoutputsoftheserializer.These outputsareinternallyterminated Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS32EL0421 DS32ELX0421

DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O,Type Description LVDS ParallelData Bus TxCLKIN+ 37 I,LVDS Serializerinputclock.TxCLKIN+/-aretheinvertingand non-invertingLVDS transmitclockinput TxCLKIN- 38 pins. TxIN[4:0]+/- 39,40, I,LVDS Serializerinputdata.TxIN[4:0]+/-aretheinvertingand non-invertingLVDS serializerinputdata 41,42, pins. 43,44, 45,46, 47,48 LVCMOS ControlPins DC_B 5 I, DC-balanceand Remote Sense pins.See DeviceConfigurationsectionDEVICE RS 6 LVCMOS CONFIGURATION fordevicebehavior. DE_EMPH0 9 I, DE_EMPH0, DE_EMPH1 selecttheoutputde-emphasislevel.These pinsareinternallypull- DE_EMPH1 10 LVCMOS down. 00:Off 01:Low 10:Medium 11:Maximum TXOUT1_EN 12 I, DS32ELX0421 ONLY. When heldhigh,redundantoutputTxOUT1+/- isenabled.Thispinmust LVCMOS be tiedhighwhen usingTxOUT1+/-. RESET 30 I, When heldlow,resetthedevice. LVCMOS 0 = DeviceReset 1 = Normal operation LOCK 31 O, Lock indicationoutput.The inputdataon TxIN[0:4]+/-pinsisignoredwhen LOCK pinishigh. LVCMOS SMBus Interface SCK 33 I/O, SMBus compatibleclock. SMBus SDA 32 I/O, SMBus compatibledataline. SMBus SMB_CS 34 I,SMBus SMBus chipselect.When heldhigh,SMBus management controlisenabled. Other GPIO0 3 I/O, SoftwareconfigurableI/Opin. LVCMOS GPIO1 4 I/O, SoftwareconfigurableI/Opin. LVCMOS GPIO2 11 I/O, SoftwareconfigurableI/Opin. LVCMOS NC 2,8,12,13, Misc. No Connect,forDS32EL0421 19,20,21, 22,23,24, 2,8,13,21, Misc. No Connect,forDS32ELX0421 22,23,24, These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 AbsoluteMaximum Ratings (1)(2) SupplyVoltage(3.3VVDD33 ) −0.3Vto+4V SupplyVoltage(2.5VVDD25 ) −0.3Vto+3V LVCMOS InputVoltage −0.3Vto(VDD + 0.3V) LVCMOS OutputVoltage −0.3Vto(VDD + 0.3V) LVDS InputVoltage(IN+,IN-) −0.3Vto+3.6V CML OutputVoltage −0.3Vto+3.6V JunctionTemperature +125°C StorageTemperatureRange -65°C to+150°C Lead TemperatureRange Soldering(4sec.) +260°C ThermalResistance,θJA 25°C/W ESD Susceptibility HBM (3) >8 kV (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. (3) Human Body Model,applicablestd.JESD22-A114C Recommended OperatingConditions Min Typ Max Units SupplyVoltage(VDD33 – GND) 3.135 3.3 3.465 V SupplyVoltage(VDD25 – GND) 2.375 2.5 2.625 V SupplyNoiseAmplitudefrom10 Hz to50 MHz 100 mV P-P AmbientTemperature(TA) -40 +25 +85 °C Power Supply Specifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Condition Min Typ Max Unit IDD25 2.5Vsupplycurrent 1.25Gbps 87 94 1 OutputEnabled 2.5Gbps 95 105 3.125Gbps 101 112 mA 2.5Vsupplycurrent 1.25Gbps 126 135 2 OutputsEnabled 2.5Gbps 136 145 3.125Gbps 142 152 IDD33 3.3Vsupplycurrent 1.25Gbps 74 85 1 OutputEnabled 2.5Gbps 74 85 3.125Gbps 74 85 mA 3.3Vsupplycurrent 1.25Gbps 80 92 2 OutputsEnabled 2.5Gbps 80 92 3.125Gbps 80 92 (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS32EL0421 DS32ELX0421

DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com Power Supply Specifications(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Condition Min Typ Max Unit PD Power Consumption 1.25Gbps 460 540 1 OutputEnabled 2.5Gbps 485 560 3.125Gbps 500 575 mW Power Consumption 1.25Gbps 580 670 2 OutputEnabled 2.5Gbps 605 695 3.125Gbps 620 710 LVCMOS ElectricalSpecifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.AppliestoGPIO0, GPIO1, GPIO2, RESET, LOCK, RS, and DC_BAL. (1)(2)(3) Symbol Parameter Conditions Min Typ Max Units VIH HighLevelInputVoltage 2.0 VDD V VIL Low LevelInputVoltage 0 0.8 V VOH HighLevelOutputVoltage IOH = -2mA 2.7 3.3 V VOL Low LevelOutputVoltage IOL = 2mA 0.3 V VCL InputClamp Voltage ICL = -18mA -0.79 -1.5 V IIN InputCurrent VIN = 0.4V,2.5V,orVDD -35 35 μA IOS OutputShortCircuitCurrent VOUT = 0V 42 mA (4) (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedtoground exceptVOD and ΔVOD . (3) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (4) Outputshortcircuitcurrent(IOS )isspecifiedas magnitudeonly,minus signindicatesdirectiononly. SMBus ElectricalSpecifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2)(3) Symbol Parameter Conditions Min Typ Max Units VSIL Data,ClockInputLow Voltage 0.8 V VSIH Data,ClockInputHighVoltage 2 VSDD V VSDD NominalBus Voltage 2.375 3.6 V iSLEAKB InputLeakage Per Bus Segment ±200 μA C SI CapacitanceforSDA and SCLK See (4),(5) 10 pF (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedtoground exceptVOD and ΔVOD . (3) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (4) Recommended value,parameterisnottested. (5) Recommended maximum capacitanceloadperbus segment is400 pF.

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DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 SMBus Timing Specifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units tSMB Bus OperatingFrequency 10 100 kHz tBUF Bus FreeTime between Stopand StartCondition 4.7 μs tHD:STA Holdtimeafter(repeated)startcondition.Afterthis 4.0 μs period,thefirstclockisgenerated. tSU:STA Repeated StartConditionSetupTime 4.7 μs tSU:STO StopConditionSetupTime 4.0 μs tHD:DAT Data HoldTime 300 ns tSU:DAT Data SetupTime 250 ns tLOW ClockLow Time 4.7 μs tHIGH ClockHighTime 4.0 50 μs tF Clock/DataFallTime 20% to80% 300 ns tR Clock/DataRiseTime 1000 ns tSU:CS SMB_CS SetupTime 30 ns tPOR Time inwhichthedevicemust be operationafter See (3) 500 ms power on (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (3) Parameterisensuredby characterizationand isnottestedatproduction. LVDS ElectricalSpecifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2)(3) Symbol Parameter Conditions Min Typ Max Units VTH DifferentialInputHighThreshold +100 mV 0.05V< VLVCM < VDD25 – 0.05V VTL DifferentialInputLow Threshold -100 mV VLVCM LVDS InputCommon Mode Voltage 0.05 VDD25 – V 0.05 VLVOS LVDS InputLoss ofSignal LVDS inputlossofsignallevel. 20 mV P-P See (4) R LVIN InputImpedance InternalLVDS inputtermination 85 100 115 Ωbetween differentialpairs. (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedtoground exceptVOD and ΔVOD . (3) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (4) IfinputLVDS signalisbelow20mV P-P,lossofsignal(LOS) isdetected.The devicewillflaga validinputsignalifthesignallevelis above 100mV P-P LVDS Timing Specifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units f InputDDR Clock(TxCLKIN)FrequencyRange 125 312.5 MHz tCIP TxCLKIN Period See Figure3 3.2 2T 8 ns (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS32EL0421 DS32ELX0421

DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com LVDS Timing Specifications(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units tCIT TxCLKIN TransitionTime See Figure2 0.5 1.0 3.0 ns See (3) tXIT TxIN TransitionTime 0.15 3 ns tCIH TxCLKIN HighTime See Figure3 0.7T T 1.3T ns tCIL TxCLKIN Low Time 0.7T T 1.3T ns tSTC TxIN SetuptoTxCLKIN -550 ps tHTC TxIN HoldtoTxCLKIN 900 ps tLVDLS LVDS InputClockDelayStepSize Programmable throughtheSMBus, 100 ps register30'h Defaultsetting= 011'b [7:5] (3) Parameterisensuredby characterizationand isnottestedatproduction. CML ElectricalSpecifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2)(3) Symbol Parameter Conditions Min Typ Max Units R OT OutputTerminations On chipterminationfromTxOUT0/1 + 40 50 60 Ω and TxOUT0/1 -toVDD25 50Ω mode 75Ω mode 60 75 90 Ω ΔR OT MismatchinOutputTerminationResistors 5 % VOD OutputDifferentialVoltageSwing Based on VOD_CTRL = 9.1kΩ 1175 1350 1450 mV P-P (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedtoground exceptVOD and ΔVOD . (3) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. CML Timing Specifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units LR LineRate Testedwithalternating1-0pattern. 1.25 3.125 Gbps tOS OutputOvershoot See (3) 10 % tR DifferentialLow toHighTransitionTime See (3) 60 90 ps tF DifferentialHightoLow TransitionTime 60 90 ps tRFMM MismatchinRise/FallTime See (3) 15 ps tDE De-emphasiswidth Measured fromzero-crossingatrising 1 UI edge to80% ofVOD fromzero- crossingatfallingedge.TDE is measured attheHighsettingduring test. tBIT SerializerBitWidth 0.2x ns tCIP tSD SerializerPropagationDelay– Latency Depends on mode — see Table3 (10– ns 14)T+ 5.5 (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (3) Parameterisensuredby characterizationand isnottestedatproduction.

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80% 20% tCIT 80% 20% tCIT SP tBUF tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA ST SP tSU:STO SCK SDA SMB_CS tSU:CS ST DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 CML Timing Specifications(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units tJIND SerializerOutputDeterministicJitter Serializeroutputintrinsicdeterministic jitter.Measure withPRBS-7 test patternDe-emphasisdisabled. See (3) 1.25Gbps 10 ps 2.5Gbps 24 ps 3.125Gbps 21 ps tJINR SerializerOutputRandom Jitter Serializeroutputintrinsicrandom jitter.Biterrorrate≥10-15. Alternating–10 pattern.De-emphasis disabled. See (3) 1.25Gbps 1.3 psRMS 2.5Gbps 1.15 psRMS 3.125Gbps 1.14 psRMS tJINT Peak-to-peakSerializerOutputJitter Serializeroutputpeak-to-peakjitter includesdeterministicjitter,random jitter,and jittertransferfromserializer input.Measure withPRBS-7 test pattern.Biterrorrate≥10-15.De- emphasisdisabled. See (3) 1.25Gbps 28 ps 2.5Gbps 38 ps 3.125Gbps 35 ps λTXBW JitterTransferFunction-3dB Bandwidth 1.25Gbps 100 kHz (4) 3.125Gbps 300 kHz δTX JitterTransferFunctionPeaking 0.5 dB (4) (4) Parameterisensuredby characterizationand isnottestedatproduction. Timing Diagrams Figure1. SMBus timingparameters Figure2. SerializerInputClock TransitionTime Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS32EL0421 DS32ELX0421

Symbol N Symbol N+3Symbol N+1 Symbol N+2 Symbol N+4 Symbol NSymbol N-1Symbol N-2Symbol N-3Symbol N-4 TXCLK TXN TXOUT tSD TxIN TxCLKIN Programmable Delay Clock (Internal) tHTC tSTC Valid Data Window tCIP/2 Clock Delay (Programmable) TXCLK TXn Setup Hold tCIL, tCIH tCIP/2 tSTC tHTC +100 mV -100 mV DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com Figure3. Serializer(LVDS Interface)Setup/Holdand High/Low Times Figure4. LVDS InputClock Delay Figure5. PropagationDelay Timing Diagram

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Current CyclePrevious Cycle Next Cycle Input Transmit Clock A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3 D0 D1 D2 D3 E0 E1 E2 E3 LVDS Data-0 LVDS Data-1 LVDS Data-2 LVDS Data-3 LVDS Data-4 Serialized CML Output First Bit Out Last Bit Out DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 Figure6. 5-BitParallelLVDS InputsMapped toCML Output FUNCTIONAL DESCRIPTION POWER SUPPLIES The DS32EL0421 and DS32ELX0421 have severalpower supplypins,at2.5V as wellas 3.3V.Itisimportant thatthesepinsallbe connectedand properlybypassed.Bypassingshouldconsistofparallel4.7μF and 0.1μF capacitorsas a minimum, witha 0.1μF capacitoron each power pin.A 22 μF capacitorisrequiredon the VDDPLL pinwhichisconnectedtothe3.3Vrail. These deviceshave a largecontactinthecenteron thebottomofthepackage.Thiscontactmust be connected tothesystemGND as itisthemajorgroundconnectionforthedevice. POWER UP Itisrecommended, althoughnotnecessary,tobringup the3.3Vpower supplybeforethe2.5Vsupply.Ifthe2.5V supplyispowered up first,an initialcurrentdraw ofapproximately600mA from the2.5V railmay occurbefore settlingtoitsfinalvalue.Regardlessofthesequence,bothpower railsshouldmonotonicallyramp up totheirfinal values. POWER MANAGEMENT These deviceshave two methods to reduce power consumption.To enterthe firstpower save mode, the on board hostFPGA or controllingdevicecan cease to outputthe DDR transmitclock.To furtherreduce power consumption,write40'hto register26'hand 10'hto register01'h.Thiswillput the deviceinitslowestpower consumptionmode. RESET There arethreeways toresetthesedevices.A resetoccursautomaticallyduringpower-up.The devicecan also be resetby pullingtheRESET pinlow,withnormaloperationresumingwhen thepinisdrivenhighagain.The devicecan alsobe resetby writingtotheresetregister.Thisresetwillputalloftheregistervaluesback totheir defaultvalues,except itwillnot affectthe address registervalue ifthe SMBus defaultaddress has been changed. Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS32EL0421 DS32ELX0421

DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com LVDS INPUTS The DS32EL0421 and DS32ELX0421 have standard2.5V LVDS inputswhicharecompliantwithANSI/TIA/EIA- 644.These inputshave internal100Ω terminationresistors.Itisrecommended thatthePCB tracebetween the FPGA and theserializerbe lessthan40-inches.LongerPCB tracesmay degradethequalityoftheinputsignal. The connectionbetween the host and the DS32EL0421 or DS32ELX0421 should be over a controlled impedance transmissionlinewithimpedance thatmatches the terminationresistor– usually100Ω. Setup and holdtimesarespecifiedintheLVDS TimingSpecifications,however theclockdelaycan be adjustedby writing toregister30’h. LOOP FILTER The DS32EL0421 and DS32ELX0421 have an internalPLL whichisused togeneratetheserializationclockfrom theparallelclockinput.The loopfilterforthisPLL isexternal;and foroptimum results,a 100nF capacitorand a 1.5kΩ resistorinseriesshouldbe connectedbetween pins26 and 27.See typicalinterfacecircuit(Figure11). CML LAUNCH AMPLITUDE The launchamplitudeoftheCML output(s)iscontrolledby placinga singleresistorfromtheVOD_CTRL pinto ground.Use thefollowingequationtoobtainthedesiredVOD by selectingthecorrespondingresistorvalue. R = (1400mV /VOD )x 9.1kΩ (1) The CML outputlaunchamplitudecan alsobe adjustedby writingtoSMBus register69'h,bits2:0.Thisregister is meant to assistsystem designersduringthe initialprototypedesign phase. For finalproduction,itis recommended thattheappropriateresistorvaluebe selectedforthedesiredVOD and thatregister69'hbe leftto itsdefaultvalue. REMOTE SENSE The remotesense featurecan be used when a DS32EL0421 orDS32ELX0421 serializerisdirectlyconnectedto a DS32EL0124 or DS32ELX0124 deserializer.Activecomponents inthesignalpathbetween theserializerand thedeserializermay interferewiththeback channelsignalingofthedevices. When remote sense isenabled,theserializerwillcyclethroughfourstatestosuccessfullyestablisha linkand alignthe data.The statediagram forthe serializerisshown inFigure7. The serializerwillremain inthe low power IDLE stateuntilitreceivesan inputclock.Once thePLL oftheserializerhas lockedtotheinputclock,the devicewillenterthe LINK DETECT state.While inthisstate,the serializerwillmonitorthe lineto see ifthe deserializerispresent.Ifa deserializerisdetected,theserializerwillentertheLINK ACQUISITION state.The serializerwilltransmittheentiretrainingpatternand thenentertheNORMAL state.Ifthedeserializerisunableto successfullylockormaintainlockitwillbreakthelink,sendingtheserializerback totheIDLE orLINK DETECT states. WiththeRemote Sense featureactive,theserializercan be forcedoutoflockdue toeventson thehighspeed seriallineintwo ways, a serialchannelresetsignalissentupstream from the deserializeror the near end terminationdetectcircuitsignalsand open terminationwas detected.The upstream signalsent from the deserializerthatresetsthe serializeriscalledthe linkdetectsignal.Since the serializerand deserializermay power up atdifferenttimes,thedeserializerwilltransmitthislinkdetectsignalperiodically,once itdetectsthata serializerisactiveon theothersideofthehighspeed line.When a serializerreceivesthelinkdetectsignal,itwill returntotheLINK DETECT state.The near end open terminationdetectioncircuitwilltriggeronlyfornear end open terminationevents,such as unpluggingthecableon theserializerend oftheline. DC-BALANCE ENCODER The DS32EL0421 and DS32ELX0421 have a built-inDC-balanceencodertosupportAC-coupledapplications. When enabled,theinputsignalon TXIN4+/-istreatedas a datavalidbit.IfTXIN4+/-islow,thenthefourbit nibblesfromTXIN0-TXIN3 aretakentoforma 16 bitword.This16 bitword isprocessedas two 8 bitwords and convertedtotwo 10 bitwords by usingthestandard8b/10bdatacodingscheme. The two 10 bitwords arethen combined tocreatea 20 bitcode.This20 bitword isserializedand drivenon theoutput.The nibbletakeninon therisingedge oftheclockisthemost significantnibbleand thenibbletakeninon thefallingedge istheleast significantnibble.IfTXIN4+/TXIN4-ishigh,thentheinputsTXIN0 -TXIN3 areignoredand a programmableDC- balancedSYNC characterisinsertedinthe outputstream.The defaultcharacterisa K28.5 code.In orderto send otherK codes,theymust firstbe programmed intothe serializerviathe SMBus. The SMBus registers allowsforonlya singleprogrammablecharacter.

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RS: 1, DC_B: 0 RS: 1, DC_B: 1 DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 Figure7. SerializerStateDiagram SCRAMBLER and NRZI Encoder The CDR oftheDS32EL0124 and theDS32ELX0124 expecta transitiondensityof20% fora periodof200 μs.If thescramblerand NRZI encoderare enabled,theraw or DC-balancedserializeddataisscrambledtoimprove transitiondensity.The scrambleraccepts20 bitsofdataand encodes itusingthepolynomialX9 + X4 + 1.The datacan thenbe senttotheNRZ-to-NRZIconverterbeforebeingoutput. Enablingthescramblercan helptolowerEMI emissionsby spreadingthespectrumofthedata.Scramblingalso createstransitionsforthedeserializer’s CDR toproperlylockonto. The scramblerand NRZI encoderareenabledordisabledby defaultdependingon how theDC_B and RS pins are configured.To overridethe defaultscramblersettingtwo registerwritesmust be performed.First,writeto register22’h and setbit3 tounlockthescramblerregister.Next writetoregister21’h and change bit4 tothe desiredvalue.The NRZI encodercan be enabledordisabledindependentlyofthescramblerby controllingbit7 ofregister21'hand bit4 ofregister22'h. CML OUTPUT DATA INTERFACING The serialoutputsprovidelow-skew differentialsignals.Internalresistorsconnected from TxOUTn+ and TxOUTn- to VDD25 terminatethe outputs.The outputlevelcan be programmed by adjustingthe pull-down resistortotheVOD_CTRL pin.The outputterminationscan alsobe programmed tobe either50 Ω or75 Ω. The outputbufferconsistsof a currentmode logic(CML) driverwithuser configurablede-emphasiscontrol, which can be used to optimizeperformanceover a wide range of transmissionlinelengthsand attenuation distortionsresultingfrom low cost CAT(-5, -6,-7) cable or FR –4 backplane.Output de-emphasis is user programmable througheitherdevicepinsDE_EMPH0 and DE_EMPH1 or SMBus interface.Users can control thestrengthofthede-emphasistooptimizefora specificsystemenvironment.Pleasesee Table1 fordetails. Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS32EL0421 DS32ELX0421

DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com Table1.De-Emphasis ControlTable DE_EMPH[1:0] Output De-Emphasis Level 00'b Off 01'b Low 10'b Medium 11'b High The DS32ELX0421 providesa secondary serialoutput,supportingredundancy applications.The redundant outputdrivercan be enabledby settingTXOUT1_EN pintoHIGH orby activatingitthroughtheSMBus reigsters. DEVICE CONFIGURATION Therearefourways toconfiguretheDS32EL0421 and DS32ELX0421 serializers,thesecombinationsareshown inTable 2. Referto Figure7 to see how the combinationsof the RS and DC_B pinschange the linkstartup behaviorof the serializers.When connectingto a deserializerotherthan the DS32EL0124 or DS32ELX0124, Remote Sense shouldbe disabled.The scramblerand NRZI encoder shown in Table 2 can be enabled or disabledthroughregisterprogramming. When Remote Sense is enabled,with RS pin tiedlow, the serializermust be connected directlyto a DS32EL0124 or DS32ELX0124 deserializerwithoutany activecomponents between them.The Remote Sense module featuresan upstream communicationmethod forthe serializerand deserializerto communicate.This featureisused to pass linkstatusinformationbetween the 2 devices.When Remote Sense isenabled the serializerwillsend a trainingpatterntothedeserializertoestablishlockand lanealignment. IfDC-Balance isenabled,a maximum of 4 parallelLVDS lanescan be used to receivedata.The fifthlane (TXIN4±) isused forData Validsignaling.Each timea serializerestablishesa linkto a deserializerwithDC- Balanceenabledand Remote Sense disabled,theData Validinputtotheserializermust be heldhighfor110 LVDS clockperiods.IftheData ValidinputtotheserializerislogicHIGH, thenSYNC charactersaretransmitted. Ifthedeserializerreceivesa SYNC character,thentheLVDS dataoutputswillallbe logiclow and theData Valid outputwillbe logichigh.Ifthedeserializerdetectsa DC-Balance code error,theoutputdatapinswillbe setto logichighwiththeData Validoutputalsosettologichigh. Inthecase where DC-Balance isenabledand Remote Sense isdisabled,withRS settohighand DC_B setto low,itisrecommended thatthehostdeviceperiodicallytoggletheData Validinputtotheserializer,totransmit SYNC symbols on the line,to ensure thatthe deserializerisand remains locked.In thisconfigurationthe deserializerorreceivingdevicedoes nothave a way todirectlynotifytheserializerifithas lostlock.Periodically sendingSYNC symbols willallowthereceivingsystem toreacquirelockifa problemhas occurred.With these pinsettingstheDS32EL0421/DS32ELX0421 and DS32EL0124/DS32ELX0124 devicescan interfacewithother activecomponent inthehighspeed signalpath,such as fibermodules. When both Remote Sense and DC-Balance are disabled,RS and DC_B pins set to high,the LVDS lane alignmentisnotmaintained.Inthisconfiguration,dataformattingishandledby an FPGA orexternalsource.This pin settingcombinationalso allowsfor the DS32EL0421/DS32ELX0421 devices to interfacewith active components otherthantheDS32EL0124/DS32ELX0124 inthehighspeed signalpath.Inthisconfigurationthe hostdeviceisresponsibleforDC balancingthedatainan AC coupledapplication.

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DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 Table2. Device ConfigurationTable Remote Sense Pin DC-Balance Pin (DC_B) Configuration (RS) 0 0 Remote Sense enabled DC-Balanceenabled Data Alignment Scramblerand NRZI encoderdisabledby default 0 1 Remote Sense enabled DC-Balancedisabled Data Alignment Scramblerand NRZI encoderenabledby default 1 0 Remote Sense disabled DC-Balanceenabled Data Alignment Scramblerand NRZI encoderenabledby default 1 1 Remote Sense disabled DC-Balancedisabled No Data Alignment Scramblerand NRZI encoderdisabledby default SMBus INTERFACE The System Management Bus interfaceiscompatibletoSMBus 2.0physicallayerspecification.The use ofthe Chip Selectsignalisrequired.HoldingtheSMB_CS pinHIGH enablestheSMBus port,allowingaccesstothe configurationregisters.Holdingthe SMB_CS pinLOW disablesthe device'sSMBus, allowingcommunication fromthehosttootherslavedeviceson thebus.IntheSTANDBY state,theSystem Management Bus remains active.When communicationtootherdeviceson theSMBus isactive,theSMB_CS signalfortheserializermust be drivenLOW. The address byte for allDS32EL0421 and DS32ELX0421 devices is AE'h. Based on the SMBus 2.0 specification,thesedeviceshave a 7-bitslaveaddressof1010111'b.The LSB issetto0'b(fora WRITE), thus the8-bitvalueis1010 1110 'borAE'h. The SCK and SDA pinsare 3.3V LVCMOS signalingand includehigh-Zinternalpullup resistors.Externallow impedance pullup resistorsmaybe requireddependingupon SMBus loadingand speed.Note,thesepinsarenot 5V tolerant. TransferofData viatheSMBus Duringnormaloperationthedataon SDA must be stableduringthetimewhen SCK isHIGH. TherearethreeuniquestatesfortheSMBus: START A HIGH toLOW transitionon SDA whileSCK isHIGH indicatesa message START condition STOP A LOW toHIGH transitionon SDA whileSCK isHIGH indicatesa message STOP condition. IDLE IfSCK and SDA arebothhighfora timeexceedingtBUF fromthelastdetectedSTOP conditionoriftheyareHIGH fora total exceedingthemaximum specificationfortHIGH thenthebus willtransfertotheIDLE state. SMBus Transactions The devicessupportWRITE and READ transactions.See RegisterDescriptionTableforregisteraddress,type (Read/Write,Read Only),defaultvalueand functioninformation. Writingtoa Register To writea register,thefollowingprotocolisused (seeSMBus 2.0specification). 1. The Host(Master)selectsthedeviceby drivingitsSMBus ChipSelect(SMB_CS) signalHIGH. 2. The Hostdrivesa START condition,the7-bitSMBus address,and a “0”indicatinga WRITE. 3. The Device(Slave)drivestheACK bit(“0”). 4. The Hostdrivesthe8-bitRegisterAddress. 5. The Devicedrivesan ACK bit(“0”). Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS32EL0421 DS32ELX0421

DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com 6. The Hostdrivethe8-bitdatabyte. 7. The Devicedrivesan ACK bit(“0”). 8. The Hostdrivesa STOP condition. 9. The Hostde-selectsthedeviceby drivingitsSMBus CS signalLow. The WRITE transactioniscompleted,the bus goes IDLE and communicationwithotherSMBus devicesmay now occur. Reading a Register To reada register,thefollowingprotocolisused (seeSMBus 2.0specification). 1. The Host(Master)selectsthedeviceby drivingitsSMBus ChipSelect(SMB_CS) signalHIGH. 2. The Hostdrivesa START condition,the7-bitSMBus address,and a “0”indicatinga WRITE. 3. The Device(Slave)drivestheACK bit(“0”). 4. The Hostdrivesthe8-bitRegisterAddress. 5. The Devicedrivesan ACK bit(“0”). 6. The Hostdrivesa START condition. 7. The Hostdrivesthe7-bitSMBus Address,and a “1”indicatinga READ. 8. The Devicedrivesan ACK bit“0”. 9. The Devicedrivesthe8-bitdatavalue(registercontents). 10. The Hostdrivesa NACK bit“1”indicatingend oftheREAD transfer. 11. The Hostdrivesa STOP condition. 12. The Hostde-selectsthedeviceby drivingitsSMBus CS signalLow. The READ transactioniscompleted,thebus goes IDLE and communicationwithotherSMBus devicesmay now occur. SMBus Configurations Many differentconfigurationsof the SMBus are possibleand depend upon the specificrequirementsof the applications.Severalpossibleapplicationsaredescribed. Configuration1 The deserializerSMB_CS may be tiedHigh (alwaysenabled)sinceitisthe onlydeviceon the SMBus. See Figure8. Configuration2 SincethemultipleSER deviceshave thesame address,theuse oftheindividualSMB_CS signalsisrequired. To communicate witha specificdevice,itsSMB_CS isdrivenHigh toselectthedevice.Afterthetransactionis complete,itsSMB_CS isdrivenLow todisableitsSMB interface.Otherdeviceson thebus may now be selected withtheirrespectivechipselectsignalsand communicatedwith.See Figure9. Configuration3 The addressingfieldislimitedto 7-bitsby the SMBus protocol.Thus itispossiblethatmultipledevicesmay sharethesame 7-bitaddress.An optionalfeatureintheSMBus 2.0specificationsupportsan AddressResolution Protocol(ARP).Thisoptionalfeatureisnotsupportedby theDS32EL0421/DS32ELX0421 devices.Solutionsfor thisinclude:theuse oftheindependentSMB_CS signals,independentSMBus segments,orothermeans.

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SMB_CS SMBus Device SCK SDA SMB_CS SMBus Device SCK SDA SMB_CS SMBus Device 3V3 3V3 3V3 FPGA Host LVCMOS GPIO SMBus Interface 3V3 SCK SDA SMB_CS SMBus Device SCK SDA SMB_CS SMBus Device SCK SDA SMB_CS SMBus Device FPGA Host LVCMOS GPIO SMBus Interface 3V3 SCK SDA SMB_CS SMBus Device 3V3 DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 Figure8. SMBus Configuration1 Figure9. SMBus Configuration2 Figure10. SMBus Daisy Chained CS Configuration Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS32EL0421 DS32ELX0421

DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com PROPAGATION DELAY Once theserializerislocked,theamount oftimeittakesfora bittotravelintothedevicethroughtheDDR LVDS inputsand out throughthe CML serialoutputisdefinedto be the propagationdelay.The propagationdelay throughthe DS32EL0421/DS32ELX0421 due to the analogcircuitryisconsiderednegligiblecompared to the timedelaycaused by thedigitalcomponents.The informationpresentedinthissectionallowssystem designers topredictthepropagationdelaythroughthedeviceintermsofclockcycleswhich are proportionaltothehigh speed seriallinerate. Each clockcycleshown inTable3 isdefinedtobe 1/2tCIP.Note at3.125Gbps,tCIP is312.5MHz,T is1/2tCIPor 156.25MHz whichis6.40nsperclock.. Table3.SerializerPropagationDelay Config.Pins LVDS DC Balance Scrambler NRZ CML Analog Total (DC_B, RS) Interface Encoder Encoder interface Delay Propagation Delay Data Flow (lefttoright) 0,0 3 clocks 1 clock – – 5 – 6 clocks 2 clocks 11 – 12 clocks + ~5.5ns + ~5.5ns 0,1 3 clocks 1 clock 1 clock 1 clock 5 – 6 clocks 2 clocks 13 – 14 clocks + ~5.5ns + ~5.5ns 1,0 3 clocks – 1 clock 1 clock 5 – 6 clocks 2 clocks 12 – 13 clocks + ~5.5ns + ~5.5ns 1,1 3 clocks – – – 5 – 6 clocks 2 clocks 10 – 11 clocks + ~5.5ns + ~5.5ns ApplicationInformation GPIO PINS The GPIO pinscan be usefultoolswhen debuggingor evaluatingthesystem.For specificGPIO configurations and functionsrefertoregisters2,3,4,5 and 6 inthedeviceregistermap. GPIO pinsare commonly used when thereare multipleserializerson the same SMBus. In orderto program individualsettingsintoeach serializer,theywilleach need to have a uniqueSMBus address.To reprogram multipleserializerson a singleSMBus, configurethefirstserializersuch thattheSMBus linesareconnectedto theFPGA or hostcontroller.The CS pinofthesecond serializershouldbe tiedtoGPIO0 ofthefirstserializer, withtheCS pinofthenextserializertiedtoGPIO0 ofitsprecedingserializer.By holdingalloftheGPIO0 pins low,thefirstserializer’s addressmay now be reprogrammed by writingtoregister0.The firstserializer’s GPIO pincan now be assertedand thesecond serializer’s addressmay now be reprogrammed. HIGH SPEED COMMUNICATION MEDIA Using the serializer’s integratedde-emphasisblocksincombinationwiththe DS32EL0124 or DS32ELX0124 ’s integratedequalizationblocksallowsdatatobe transmittedacrossa varietyofmedia athighspeeds.Factors thatcan limitdeviceperformanceincludeexcessiveinputclockjitter,noisypower rails,EMI from nearbynoisy components and poor layouttechniques.Althoughmany cablescontainwiresof similargauge and shielding, performancecan varygreatlydependingon thequalityoftheconnector. REDUNDANCY APPLICATIONS The DS32ELX0421 has two highspeed CML serialoutputs.SMBus registercontrolallowsthedevicetouse a singleoutputexclusively,or bothoutputssimultaneously.Thisallowsa singleserializertotransmitdatatotwo independantreceivingsystems,a primaryand secondaryendpoint.Some applicationsrequirea redundancy measure incase theprimarysignalpathiscompromised.The secondaryoutputcan be activated“on-the-go”,ifa problem isdetectedon the primarylink.See the Redundancy / FailOver Configurationsectionlocatedunder RegisterRecipes.

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SMB_CS GPIO2 FPGA Host 2.5V 3.3V VDDPLL LF_REF LF_CP 100 nF GPIO0 GPIO1 22 PF 3.3V TXOUT0 TXOUT1 GND VCC25 VCC33 VOD_CTRL 9.1 k: 1, 36 7, 15, 18, 25, 3549 DC_B RS 3.3V3.3V 0.1 PF 0.1 PF 1.5 k: LOCK31 RESET30 TXIN3 -43 TXIN2 -44 TXIN1 -42 TXIN0 -40 TXCLKIN -38 DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 LINK AGGREGATION MultipleDS32EL0421/DS32ELX0421 serializersand D32EL0124/DS32ELX0124 deserializerscan be aggregatedtogetherifan applicationrequiresa datathroughputofmore than3.125Gbps. By utilizingthedata validsignalofeach device,thesystem can be properlydeskewed toallowfora singlecable,such as CAT-6, DVI-D,orHDMI, tocarrydatapayloadsbeyond 3.125Gbps. Linkaggregationconfigurationscan alsobe implementedinapplicationswhich requirelongercablelengths.In thesetypeofapplicationsthedatarateofeach serializerand deserializerchipsetcan be reduced,such thatthe applications'netdatathroughputisstillthesame. Sinceeach highspeed channelisnow operatingata fraction oftheoriginaldatarate,thelossoverthecableisreduced,allowingforgreaterlengthsofcabletobe used inthe system. For more informationregardinglinkaggregationpleasesee SNLA109 ,ExpandingthePayloadwithTI'sFPGA- LinkDS32ELX0421 and DS32ELX0124 Serializerand Deserializer. LAYOUT GUIDELINES Itisimportanttofollowgood layoutpracticesforhighspeed devices.The lengthofLVDS inputtracesshouldnot exceed 40 inches.InnoisyenvironmenttheLVDS tracesmay need tobe shortertopreventdatacorruptiondue toEMI. Noisycomponents shouldnotbe placednexttotheLVDS or CML traces.The LVDS and CML traces must have a controlleddifferentialimpedance of100 Ω.Do notplaceterminationresistorattheLVDS inputsor CML outputs,the DS32EL0421 and DS32ELX0421 have internalterminationresistors.Itisrecommended to avoidusingvias.Viascreatean impedance mismatch inthetransmissionlineand resultinreflections,whichcan greatlylowerthe maximum distanceof the highspeed data link.Ifviasare required,theyshouldbe placed symmetricallyon each sideofthedifferentialpair.For more tipsand detailedsuggestionsregardinghighspeed boardlayoutprinciples,pleaseconsulttheLVDS Owner ’s Manual. Figure11. TypicalInterfaceCircuit Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DS32EL0421 DS32ELX0421

DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics The eye diagramsshown belowillustratethetypicalperformaceoftheDS32ELX0421/DS32EL0421 configuredwithRS = 0,DC_B = 0,fortheconditionslistedbeloweach figure.The PRBS-15 datawas generatedby a lowcostFPGA, whichused an LMK03000C togeneratethevariousclockfrequencies. Figure12.CML SerialDifferentialOutput 1.25Gbps Figure13.CML SerialDifferentialOutput 3.125Gbps Figure14.CML SerialSingledEnded Output (+)1.25Gbps Figure15.CML SerialSingleEnded Output (+)3.125Gbps

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DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 RegisterMap The registerinformationforthe serializerisshown inthe tablebelow.Some registershave been omittedor marked as reserved;theseare forinternaltestingand shouldnot be writtento.Some registerbitsrequirean overridebittobe setbeforetheycan be writtento. Addr Name Bits Field R/W Default Description (Hex) 00 DeviceID 7:1 SMBus Address R/W 57'h Some systemswilluse all8 bitsas thedeviceID.Thiswill shiftthevaluefrom57’h toAE ’h

0 Reserved 0

01 Reset 7:5 Reserved 0

4 AnalogDisable R/W 0 1:Disablesanalogblocks.Power save feature 3:1 Reserved 0 0 SoftwareReset 0 1:Resetthedevice.Does notaffectdeviceID.

02 GPIO0 Config 7:4 GPIO0 Mode R/W 0 0000:GP outregister

0001:Linklossindicator 0011:TxCLKIN lossofsignal 0100:TxCLKIN detect Allothers:Reserved 3:2 GPIO0 R Enable R/W 01'b 00:Pullup/downdisabled 01:Pulldownenabled 10:Pullupenabled 11:Reserved

1 InputEnable R/W 0 0:Inputbufferdisabled

1:Inputbufferenabled

0 OutputEnable R/W 1'b 0:OutputTtri-State™

1:Outputenabled

03 GPIO1 Config 7:4 GPIO1 Mode R/W 0 0000:Power on reset

0001:GP outregister 0010:PLL lockindicator 0011:TxIN0 lossofsignal 0100:TxIN1 lossofsignal 0101:TxIN2 lossofsignal 0110:TxIN3 lossofsignal 0111:TxIN4 lossofsignal Allothers:Reserverd 3:2 GPIO1 R Enable R/W 01'b 00:Pullup/downdisabled 01:Pulldownenabled 10:Pullupenabled 11:Reserved 1:Inputbufferenabled

0 OutputEnable R/W 1'b 0:OutputTri-State™

1:Outputenabled

04 GPIO2 Config 7:4 GPIO2 Mode R/W 0 0000:GP outregister

0001:Alwayson clockout 0010:Parallel-to-serialclockout 0100:Digitalclockout Allothers:Reserverd 3:2 GPIO2 R Enable R/W 01'b 00:Pullup/downdisabled 01:Pulldownenabled 10:Pullupenabled 11:Reserved 1:Inputbufferenabled 1:Outputenabled Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DS32EL0421 DS32ELX0421

DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com Addr Name Bits Field R/W Default Description (Hex)

05 GP In 7:3 Reserved 0

2 GP In2 R 0 Inputvalueon GPIO2

1 GP In1 R 0 Inputvalueon GPIO1

0 GP In0 R 0 Inputvalueon GPIO0

06 GP Out 7:3 Reserved 0

2 GP Out 2 R/W 0 Outputvalueon GPIO2

1 GP Out 1 R/W 0 Outputvalueon GPIO1

0 GP Out 0 R/W 0 Outputvalueon GPIO0

07–1F Reserved

20 De-Emphasis 7:3 Reserved 0

2 PinOverride R/W 0 0:Pinvaluesdeterminesetting

1:Registeroverridespinvalues 1:0 De-emphasis R/W 0 00:No de-emphasis level 01:Low 10:Medium 11:High

21 DeviceConfig 7 NRZI enable R/W 0 1:EnableNRZI,ifoverridebitisset

6 DV disable R/W 0 1:DisableData Valid

5 Reserved R/W 0

4 ScramblerEnable R/W 0 1:Scramblerenable,requiresoverridebittochange

3 DC Balencoder R/W 0 1:Bypass encoder,requiresoverridebittochange setting

2 Training R/W 0 1:Enabletrainingsequence,requiresoverridebitto

Sequence Enable change setting 1:0 Device R/W 0 MSB: Remote Sense enable,activelow Configuration LSB: DC balanceencoderenable,activelow Requiresoverridebittochange settingsthroughregisters. Normallycontrolledby pins.See Table2 formore information.

22 DeviceConfig 7:5 Reserved 0

Override 4 NRZ bypass R/W 0 1:Unlockreg21’h bit7 override

3 Scramblerbypass R/W 0 1:Unlockreg21’h bit4

2 DC Balencoder R/W 0 1:Unlockreg21’h bit3

1 Training R/W 0 1:Unlockreg21’h bit2

0 Configpin R/W 0 1:Unlockreg21’h bits1 and 0

23 Reserved

24 LVDS ClockDelay 7 TxCLKIN Delay R/W 0 0:TxCLKIN delayenable

Enable Bypass 1:Bypass TxCLKIN delay 6:0 Reserved 0

25 Reserved

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DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 Addr Name Bits Field R/W Default Description (Hex) 26 Power Down 7 ChannelReset R/W 0 1:Resethighspeed channel.Self-clearingbit.

6 ClockPowerdown R/W 0 1:Power down parallel,parallel-to-serial,and alwayson

5 LVDS Clock R/W 1'b 0:DisableTxCLKIN

enable 1:EnableTxCLKIN

4 TxIN4 Enable R/W 1'b 0:DisableTxIN4

1:EnableTxIN4

3 TxIN3 Enable R/W 1'b 0:DisableTxIN3

1:EnableTxIN3

2 TxIN2 Enable R/W 1'b 0:DisableTxIN2

1:EnableTxIN2

1 TxIN1 Enable R/W 1'b 0:DisableTxIN1

1:EnableTxIN1

0 TxIN0 Enable R/W 1'b 0:DisableTxIN0

1:EnableTxIN0

27 EventDisable 7:5 Reserved R/W 0

4 PLL Lock Disable R/W 0 0:Count clockerrors

1:Clockerrorcountdisabled

3 FIFO Error R/W 0 0:Count FIFO erros1:FIFO errorcountdisabled

2 ParallelClock R/W 0 0:Count clockdetecterrors

DetectDisable 1:Clockdetectcountdisabled

1 ClockLoss of R/W 0 0:Count clocklosofsignalerrors

SignalDisable 1:Clocklossofsignalcountdisabled

0 Data Loss of R/W 0 0:Count datalosofsignalerrors

SignalDisable 1:Clockdataofsignalcountdisabled

28 LVDS Operation 7:2 Reserved 0

1 LVDS Loss of R/W 0 1:PresetsignalforLVDS lossofsignalregister

0 LVDS Loss of R/W 0 1:ClearsignalforLVDS lossofsignalregister

29 Loss ofSignal 7:6 Reserved 0

Status 5 ClockLoss of R 0 0:Clockpresent Signal 1:No clockpresenton TxCLKIN 4:0 Data Loss of R 0 0:Data present Signal 1:No datapresenton TxIN4:0 2A EventStatus 7:4 Reserved 0

3 TxCLKIN Detect R/W 0 0:TxCLKIN notdetected

1:TxCLKIN detected

2 Reserved 0

DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com Addr Name Bits Field R/W Default Description (Hex) 2B EventConfig 7 Reserved 0

6 PLL Lock Event R/W 0 0:Count PLL lockevents

1:Do notcountPLL lockevents

5 LinkEvent R/W 0 0:Count linkevents

1:Do notcountlinkevents

4 Loss ofSignal R/W 0 0:Count lossofsignalevents

Event 1:Do notcountlossofsignalevents

3 EventCount R/W 0 0:SelectPLL eventcountforreading

Select 1:Selectlinkeventcountforreading 2 ClearPLL Error R/W 0 1:ResetPLL errorcount.Selfclearingbit. Count 1 ClearLinkError R/W 0 1:Resetlinkerrorcount.Selfclearingbit. Count

0 EnableCount R/W 0 0:Disableeventcounters

1:Enableeventcounters 2C EventCount 7:0 EventCounter R 0 2D Reserved 2E AnalogDriver 7 Reserved 0

6 ReverseData R/W 0 0:Normal

Order 1:Reverseoutputdataorder 5:2 Reserved R/W 0

1 LinkDetect1 R/W 0 Linkdetectvalueforchannel1

0 LinkDetect0 R/W 0 Linkdetectvalueforchannel0

2F Tx Config 7:6 Reserved 0

5 Output R/W 1'b 0:75 Ω terminations

Termination 1:50 Ω terminations

4 LinkStart R/W 1'b 0:Startwhen TxOUT0 orTxOUT1 link

1:Startwhen TxOUT0 and TxOUT1 linke

3 LinkStop R/W 1'b 0:Stopwhen TxOUT0 and TxOUT1 bothlinksinvalid

1:Stopwhen TxOUT0 orTxOUT1 breaklink,eitherlinkis invalid

2 TxOUT Override R/W 0 0:TxOUT0 enabledby default,TxOUT1_en pincontrols

1:OverrideenableofTxOUT0 and TxOUT1

1 TxOUT1 Enable R/W 0 0:TxOUT1 disabled

1:TxOUT1 enabled ForproperoperationofTxOUT1, theTxOUT1_EN pin must be heldhigh.

0 TxOOUT0 Enable R/W 0 0:TxOUT0 disabled

1:TxOUT0 enabled

30 ClockDelay 7:5 TxCLKIN Delay R/W 011’b 000:Min clockdelay,350 ps

011:725 ps 111:Max clockdelay,1225 ps 4:0 Reserved 00010’b 31–68 Reserved

69 OutputAmplitude 7:3 Reserved 0

Adjust 2:0 AmplitudeAdjust R/W 011’b 000:Level7 001:Level8 (Highestoutput) 010:Level5 011:Level6 (Normaloutput) 100:Level4 101:Level3 110:Level2 111:Level1 (Lowestoutput)

ProductFolderLinks:DS32EL0421 DS32ELX0421

DS32EL0421,DS32ELX0421 www.ti.com SNLS282F –MAY 2008–REVISED APRIL 2013 RegisterRecipes Many featuresof the serializercontainedwithinthe SMBus registersrequiremultiplewritesto configureand enable.Thismethodologywas implementedtopreventaccidentalregisterwritesfromcausingundesireddevice behavior.Severalrecipesforcommon featuresarelistedbelow.When experimentingwithotherSMBus register features,be suretoreadthroughtheregistermap foroverrideand enablebits. SCRAMBLER OVERRIDE CONTROL The scrambler’s defaultsettingsare describedin the DEVICE CONFIGURATION section.However, the scrambler’s settingcan be overriddenifdesired. Reg 22’h,write08’h Reg 21’h,writetobit3 toenable/disable 75Ω MODE The serializercan be programmed tointerfacewith75Ω media by usingtherecipeshown below.The inverting serialoutputshouldbe terminatedwhen interfacingwithsingleended media. Reg 2F’h,write0 tobit5 OUTPUT CHANNEL MUX CONTROL DS32ELX0421 only.TxOUT0 istheoutputchannelenabledby default.By usingtheexternalpinTxOUT1_EN, TxOUT1 willbe activatedalongwithTxOUT0. Ifan applicationrequiresthatonlyone channelbe activeata time, thefollowingrecipeallowsforeach channeltobe enabledordisabledindependentoftheother. Reg 2F’h,write1’b tobit2 Reg 2F’h,writetobits1 or0 tocontroltheoutputchannels OUTPUT THE SERIAL CLOCK ON GPIO2 Itisveryhelpfulto be ableto monitorhighspeed communicationsystems and observetheirsignalintegrity. Generally,thisis done with a high speed realtime oscilloscopeor a sampling oscilloscope.Sampling oscilloscopesrequirea referenceclockto triggeron. The followingrecipecan be used to bringout the serial clockon GPIO2 toprovidea triggerforsamplingoscilloscopes. Reg 04’h,write21’h Power Save Mode When a system does notneed totransmithighspeed datafromtheDS32EL0421 orDS32ELX0421, thepower consumptionof the devicecan be managed as describedin the POWER MANAGEMENT sectionon the FunctionalDescriptionpage. The followingrecipepowers down many of the analogand digitalblocksinthe serializer,butleavestheSMBus module operational.Pleasenotethatinordertoresume normaloperationthe recipebelowwillhave tobe unwritten. Reg 01'h,write10'h Reg 26'h,write40'h Redundancy /FailOver Configuration DS32ELX0421 only.Implementinga redundancysystem withtheDS32ELX0421 can be done inseveralways. One method would be to program the redundancyor failover logicintothe hostdeviceor FPGA. The recipe below willdescribea differentmethod,forwhicha DS32ELX0421 willcommunicate totwo differentDS32EL0124 deserializers.The recipebelow willconfiguretheDS32ELX0421 serializertoautomaticallyswitchtothealternate outputwhen thecurrenthighspeed linkfails. ConfigurealldevicewithRemote Sense enabledeitherby pinorregistercontrol.PullTxOUT1_EN pinhigh reg2F'h,write2D'h Reg 2F'h,write28'h Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:DS32EL0421 DS32ELX0421

DS32EL0421,DS32ELX0421 SNLS282F –MAY 2008–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionE (April2013)toRevisionF Page

ProductFolderLinks:DS32EL0421 DS32ELX0421

www.ti.com 15-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples DS32EL0421SQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 32EL0421 DS32EL0421SQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 32EL0421 DS32EL0421SQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 32EL0421 DS32ELX0421SQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 32ELX0421 DS32ELX0421SQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 32ELX0421 DS32ELX0421SQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 32ELX0421 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

www.ti.com 15-Apr-2013 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS32EL0421SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS32EL0421SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS32EL0421SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 DS32ELX0421SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS32ELX0421SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS32ELX0421SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 2

www.ti.com SQA48A (Rev B)

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Product Information

DS32EL0421SQ specifications and overview.

Summary

5-bit DDR LVDS Parallel Data Interface

Description

5-bit DDR LVDS Parallel Data Interface

Source title DS32EL0421SQ Datasheet(PDF) - Texas Instruments

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