DS32EL0124SQE

DS32EL0124_09 NSC | Alldatasheet

Document overview

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Technical content

Features

■ 5-bit DDR LVDS parallel data interface ■ Programmable Receive Equalization ■ Selectable DC-balance decoder ■ Selectable De-scrambler ■ Remote Sense for automatic detection and negotiation of link status ■ No external receiver reference clock required ■ LVDS parallel interface ■ Programmable LVDS output clock delay ■ Supports output data-valid signaling ■ Supports keep-alive clock output ■ On chip LC VCOs ■ Redundant serial input (ELX device only) ■ Retimed serial output (ELX device only) ■ Configurable PLL loop bandwidth ■ Configurable via SMBus ■ Loss of lock and error reporting ■ 48-pin LLP package with exposed DAP Key Specifications ■ 1.25 to 3.125 Gbps serial data rate ■ 125 to 312.5 MHz DDR parallel clock ■ -40° to +85°C temperature range ■ > 8 kV ESD (HBM) protection ■ 0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps) Typical Application 30043101 © 2009 National Semiconductor Corporation 300431 www.national.com DS32EL0124/DS32ELX0124 125 — 312.5 MHz Deserializer with DDR LVDS Parallel Interface

Ordering Information

NSID Description Package T&R Quantity DS32EL0124SQ DES 48 - LLP, SQA48A 1000 DS32EL0124SQE 48 - LLP, SQA48A 250 DS32EL0124SQX 48 - LLP, SQA48A 2500 DS32ELX0124SQ DES with Redundant Input and Retimed Output 48 - LLP, SQA48A 1000 DS32ELX0124SQE 48 - LLP, SQA48A 250 DS32ELX0124SQX 48 - LLP, SQA48A 2500 www.national.com 2 DS32EL0124/DS32ELX0124

Pin Name Pin Number I/O, Type Description VDD33 1, 15, 18, 36 I, VDD 3.3V supply VDD25 7, 25, 35 I, VDD 2.5V supply VDD_PLL 28 I, VDD 3.3V supply LF_CP 27 Analog Loop filter capacitor connection LF_REF 26 Analog Loop filter ground reference Exposed Pad 49 GND Exposed Pad must be connected to GND by 9 vias. CML I/O RxIN0+ RxIN0- I, CML Non-inverting and inverting high speed CML differential inputs of the deserializer. These inputs are internally terminated. RxIN1+ RxIN1- I, CML DS32ELX0124 only. Non-inverting and inverting high speed CML differential inputs of the deserializer. These inputs are internally terminated. TxOUT+ TxOUT- O, CML DS32ELX0124 only. Retimed serialized high speed output. Non-inverting and inverting speed CML differential outputs of the deserializer. These outputs are internally terminated. LVDS Parallel Data Bus RxCLKOUT+ RxCLKOUT- O, LVDS Deserializer output clock. RxCLKOUT+/- are the non-inverting and inverting LVDS recovered clock output pins. 46, 47, 48 O, LVDS Deserializer output data. RxOUT[0:4]+/- are the non-inverting and inverting LVDS deserialized output data pins. 3 www.national.com DS32EL0124/DS32ELX0124

Pin Name Pin Number I/O, Type Description Control Pins LT_EN 2 I, LVCMOS DS32ELX0124 only. When held high, retimed serialized high speed output is enabled. RX_MUX_SEL 12 I, LVCMOS DS32ELX0124 only. RX_MUX_SEL selects the input of the deserializer. 0 = RxIN0+/- selected 1 = RxIN1+/- selected VOD_CTRL 14 I, LVCMOS DS32ELX0124 only. VOD control. The deserializer loop through output amplitude can be adjusted by connecting this pin to a pull-down resistor. The value of the pull-down resistor determines the VOD. See LOOP THROUGH DRIVER LAUNCH AMPLITUDE for more details. DC_B RS I, LVCMOS DC-balance and Remote Sense pins. See Application section for device behavior. RESET 30 I, LVCMOS Reset pin. When held low, reset the device. 0 = Device Reset 1 = Normal operation LOCK 31 O, LVCMOS Lock indication output. pin goes low when the deserializer is locked to the incoming data stream and begins to output data and clock on RxOUT and RxCLKOUT respectively. 0 = Deserializer locked 1 = Deserializer not locked SMBus SCK I, SMBus 33 SMBus compatible clock. SDA I/O, SMBus 32 SMBus compatible data line. SMB_CS I, SMBus 34 SMBus chip select. When held high, SMBus management control is enabled. Other GPIO0 3 I/O, LVCMOS Software configurable IO pins. GPIO1 4 I/O, LVCMOS Software configurable IO pins. GPIO2 11 I/O, LVCMOS Software configurable IO pins. 20, 21, 22, 23, 24, 29 Misc. No Connect, for DS32EL0124 8, 9, 10, 13, 23, 24, 29 Misc No Connect, for DS32ELX0124 www.national.com 4 DS32EL0124/DS32ELX0124

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD33) −0.3V to +4V Supply Voltage (VDD25) -0.3V to +3.0V LVCMOS Input Voltage −0.3V to (VDD33 + 0.3V) LVCMOS Output Voltage -0.3V to (VDD33 + 0.3V) CML Input/Output Voltage -0.3V to 3.6V LVDS Output Voltage -0.3V to +3.6V Junction Temperature +125°C Storage Temperature Range −65°C to +150°C Lead Temperature Range Soldering (4 sec.) +260°C Package Thermal Resistance θJA +25.0°C/W ESD Susceptibility HBM ≥8 kV Recommended Operating Conditions Min Typ Max Units Supply Voltage (VDD33) 3.135 3.3 3.465 V Supply Voltage (VDD25) 2.375 2.5 2.625 V Supply Noise Amplitude from 10 Hz to 50 MHz 100 mVP-P Ambient Temperature (TA) −40 +25 +85 °C SMBus Pull–Up Resistor to VSDD Value 1000 Ω Power Supply Characteristics Symbol Parameter Condition Min Typ Max Unit IDD25 2.5V supply current Loop Through Driver Disabled

1.25 Gbps 50 59

2.5 Gbps 62 73

3.125 Gbps 69 79

2.5V supply current Loop Through Driver Enabled

1.25 Gbps 88 99

2.5 Gbps 100 112

3.125 Gbps 107 120

IDD33 3.3V supply current Loop Through Driver Disabled

1.25 Gbps 105 121

2.5 Gbps 105 121

3.125 Gbps 105 121

3.3V supply current Loop Through Driver Enabled

1.25 Gbps 111 127

2.5 Gbps 111 127

3.125 Gbps 111 127

Loop Through Driver Disabled

1.25 Gbps 475 560

2.5 Gbps 500 600

3.125 Gbps 520 620

Loop Through Driver Enabled

1.25 Gbps 590 690

2.5 Gbps 620 730

3.125 Gbps 640 750

5 www.national.com DS32EL0124/DS32ELX0124

Over recommended operating supply and temperature ranges unless otherwise specified. Applies to LT_EN, GPIO0, GPIO1, GPIO2, RX_MUX_SEL, DC_B, RESET, RS, LOCK. (Note 2, Note 4, Note 5) Symbol Parameter Conditions Min Typ Max Units VIH High Level Input Voltage 2.0 VDD V VIL Low Level Input Voltage GND 0.8 V VOH High Level Output Voltage IOH = -2mA 2.7 3.2 V VOL Low Level Output Voltage IOL = 2mA 0.3V V VCL Input Clamp Voltage ICL = −18 mA -0.9 −1.5 V IIN Input Current VIN = 0.4V, 2.5V, or VDD33 -40 40 μA IOS Output Short Circuit Current VOUT = 0V (Note 6) -45 mA SMBus Electrical Specifications Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 5) Symbol Parameter Conditions Min Typ Max Units VSIL Data, Clock Input Low Voltage 0.8 V VSIH Data, Clock Input High Voltage 2.1 VSDD V VSDD Nominal Bus Voltage 2.375 3.465 V ISLEAKB Input Leakage Per Bus Segment SCK and SDA pins ±200 µA ISLEAKP Input Leakage Per Pin ±10 µA CSI Capacitance for SDA and SCK 10 pF SMBus Timing Specifications Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 5) Symbol Parameter Conditions Min Typ Max Units fSMB Bus Operating Frequency 10 100 kHz tBUF Bus free time between top and start condition 4.7 μs tHD:STA Hold time after (repeated) start condition. After this period, the first clock is generated 4.0 µs tSU:STA Repeated Start Condition Setup Time (Note 3) 4.7 µs tHD:DAT Data Hold Time 300 ns tSU:DAT Data Setup Time (Note 3) 250 ns tLOW Clock Low Time 4.7 µs tHIGH Clock High Time 4.0 50 µs tSU:CS SMB_CS Setup Time (Note 3) 30 ns tHS:CS SMB_CS Hold Time (Note 3) 100 ns tPOR Time in which the device must be operational after power on (Note 3) 500 ms www.national.com 6 DS32EL0124/DS32ELX0124

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 5) Symbol Parameter Conditions Min Typ Max Units VOD Differential Output Voltage RL = 100Ω 230 310 mV ΔVOD Changes in VOD between complimentary output states 35 mV VOS Offset Voltage 1.125 1.25 1.375 V ΔVOS Change in VOS between complimentary states 35 mV IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω (Note 6) -50 mA LVDS Timing Specifications Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 5) Symbol Parameter Conditions Min Typ Max Units tROTR LVDS low-to-high transition time 300 ps tROTF LVDS high-to-low transition time 300 ps tROCP LVDS output clock period 2T ns tRODC RxCLKOUT Duty Cycle 45 50 55 % tRBIT LVDS output bit width T ns tROSC RxOUT Setup to RxCLKOUT OUT 650 800 ps tROHC RxOUT Hold to RxCLKOUT OUT 650 800 ps tRODJ LVDS Output Deterministic Jitter RxCLKOUT (Note 3) psRxOUT0–4 (Note 3) tRORJ LVDS Output Random Jitter RxCLKOUT (Note 3) 2.5 psRxOUT0–4 (Note 3) 2.5 tROTJ Peak-to-Peak LVDS Output Jitter RxCLKOUT (Note 3) psRxOUT0–4 (Note 3) tRLA Deserializer Lock Time (Note 3)

1.25 Gbps

ms2.5 Gbps 90

3.125 Gbps 115

tLVSK LVDS Output Skew LVDS Differential Output Skew between + and - pins 20 ps 7 www.national.com DS32EL0124/DS32ELX0124

CML Input Timing Specifications Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 5) Symbol Parameter Conditions Min Typ Max Units TOLJIT Serial Input Jitter Tolerance RJ = 0.18 UI DJ = 0.37 UI SJ increased until failure f < 10 kHz f > 1 MHz 0.5 UI2.5 Gbps f < 10 kHz f > 1 MHz 0.3

3.125 Gbps

f < 10 kHz f > 1 MHz 0.3 CML Input Electrical Specifications Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 5) Symbol Parameter Conditions Min Typ Max Units VID Differential input voltage (Note 3) 230 2200 mV VIN Single ended input voltage (Note 3) 115 1100 mV IIN Input Current -300 50 μA RIT Input Termination 84 100 116 Ω CML Retimed Loop Through Output Electrical Specifications, DS32ELX0124 Only Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 5) Symbol Parameter Conditions Min Typ Max Units VLTOD Output differential voltage VOD_CTRL resistor = 9.09 kΩ (Note 3) 1.15 1.45 V RLTOT Output termination 50Ω 40 50 60 Ω 75Ω 60 75 90 ΔRLTOT Mismatch in output termination resistors 5 % CML Retimed Loop Through Output Timing Specifications, DS32ELX0124 Only Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 5) Symbol Parameter Conditions Min Typ Max Units tJIT Additive Output Jitter (Note 3) 24 35 ps tOS Output Overshoot (Note 3) 1.5 8 % tLTR Retimed output driver differential low to high transition time (Note 3) 74 105 ps tLTF Retimed output driver differential high to low transition time (Note 3) 74 105 ps tLTRFMM Mismatch in Rise/Fall Time (Note 3) 5 15 % tLTDE Retimed driver de-emphasis width 1 UI Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 2: The Electrical and Timing Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: Parameter is guaranteed by characterization and is not tested at production. www.national.com 8 DS32EL0124/DS32ELX0124

monotonically ramp up to their final values. down register will put the device in its lowest power mode. VLTOD by selecting the corresponding resistor value. also be adjusted by writing to SMBus register 49'h, bits 3:1. Figure 7. The deserialzer will remain in the low power IDLE expected training pattern and then enter the NORMAL state. registers allow for only a single programmable character.

FIGURE 7. Deserializer State Diagram deserializer’s CDR to properly lock onto. its own control bits in registers 22'h and 21'h. ing the RX_MUX_SEL pin or internal control registers. deserializer. Only one input may be selected at a time.

Ground potential difference between the interfacing systems. can also be programmed to be either 50 or 75 ohms. register 67'h bits 6:5, for details. Table 1. Refer to Figure 7 to see how the combinations of the 1 can be enabled or disabled through register programming. is used to pass link status information between the 2 devices. nent in the high speed signal path, such as fiber modules. transition density of approximately 20% for a period of 200 µs. nents in the high speed signal path. TABLE 1. Device Configuration Table

The System Management Bus interface is compatible to SM- Bus 2.0 physical layer specification. The use of the Chip Select signal is required. Holding the SMB_CS pin HIGH en- ables the SMBus port, allowing access to the configuration registers. Holding the SMB_CS pin LOW disables the device's SMBus, allowing communication from the host to other slave devices on the bus. In the STANDBY state, the System Management Bus remains active. When communi- cation to other devices on the SMBus is active, the SMB_CS signal for the deserializer must be driven LOW. The address byte for all DS32EL0124 and DS32ELX0124 devices is B0'h. Based on the SMBus 2.0 specification, these devices have a 7-bit slave address of 1011000'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1011 0000'b or B0'h. The SCK and SDA pins are 3.3V LVCMOS signaling and in- clude high-Z internal pull up resistors. External low impedance pull up resistors maybe required depending upon SMBus loading and speed. Note, these pins are not 5V tol- erant. Transfer of Data via the SMBus During normal operation the data on SDA must be stable dur- ing the time when SCK is HIGH. There are three unique states for the SMBus: START A HIGH to LOW transition on SDA while SCK is HIGH indicates a message START condition. STOP A LOW to HIGH transition on SDA while SCK is HIGH indicates a message STOP condition. IDLE If SCK and SDA are both HIGH for a time exceeding tBUF from the last detected STOP condition or if they are HIGH for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state. SMBus Transactions The devices support WRITE and READ transactions. See Register Description Table for register address, type (Read/ Write, Read Only), default value and function information. Writing to a Register The devices support WRITE and READ transactions. See Register Description Table for register address, type (Read/ Write, Read Only), default value and function information. 1. The Host (Master) selects the device by driving its SMBus Chip Select (SMB_CS) signal HIGH. 2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 3. The Device (Slave) drives the ACK bit (“0”). 4. The Host drives the 8-bit Register Address. 5. The Device drives an ACK bit (“0”). 6. The Host drive the 8-bit data byte. 7. The Device drives an ACK bit (“0”). 8. The Host drives a STOP condition. 9. The Host de-selects the device by driving its SMBus CS signal Low. The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. Reading a Register To read a register, the following protocol is used (see SMBus 2.0 specification). 1. The Host (Master) selects the device by driving its SMBus Chip Select (SMB_CS) signal HIGH. 2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 3. The Device (Slave) drives the ACK bit (“0”). 4. The Host drives the 8-bit Register Address. 5. The Device drives an ACK bit (“0”). 6. The Host drives a START condition. 7. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ. 8. The Device drives an ACK bit “0”. 9. The Device drives the 8-bit data value (register contents). 10. The Host drives a NACK bit “1”indicating end of the READ transfer. 11. The Host drives a STOP condition. 12. The Host de-selects the device by driving its SMBus CS signal Low. The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. SMBus Configurations Many different configurations of the SMBus are possible and depend upon the specific requirements of the applications. Several possible applications are described. Configuration 1 The deserializer SMB_CS may be tied High (always enabled) since it is the only device on the SMBus. See Figure 8. Configuration2 Since the multiple SER devices have the same address, the use of the individual SMB_CS signals is required. To com- municate with a specific device, its SMB_CS is driven High to select the device. After the transaction is complete, its SMB_CS is driven Low to disable its SMB interface. Other devices on the bus may now be selected with their respective chip select signals and communicated with. See Figure 9. Configuration 3 The addressing field is limited to 7-bits by the SMBus protocol. Thus it is possible that multiple devices may share the same 7-bit address. An optional feature in the SMBus 2.0 specifi- cation supports an Address Resolution Protocol (ARP). This optional feature is not supported by the DS32EL0124/ DS32ELX0124 devices. Solutions for this include: the use of the independent SMB_CS signals, independent SMBus seg- ments, or other means. www.national.com 14 DS32EL0124/DS32ELX0124

The GPIO pins can be useful tools when debugging or eval- uating the system. For specific GPIO configurations and func- tions refer to registers 2, 3, 4, 5 and 6 in the device register map. GPIO pins are commonly used when there are multiple de- serializers on the same SMBus. In order to program individual settings into each serializer, they will each need to have a unique SMBus address. To reprogram multiple deserializers on a single SMBus, configure the first deserializer such that the SMBus lines are connected to the FPGA or host controller. The CS pin of the second serializer should be tied to GPIO0 of the first deserializer, with the CS pin of the next deseriazlier tied to GPIO0 of its preceding deserializer. By holding all of the GPIO0 pins low, the first deserializer’s address may now be reprogrammed by writing to register 0. The first deserializer’s GPIO pin can now be asserted and the second deserializer’s address may now be reprogrammed. HIGH SPEED COMMUNICATION MEDIA Using the deserializer’s integrated equalizer blocks in combi- nation with the DS32EL0421 or DS32ELX0421’s integrated de-emphasis block allows data to be transmitted across a va- riety of media at high speeds. Factors that can limit device performance include excessive input clock jitter, noisy power rails, EMI from nearby noisy components and poor layout techniques. Although many cables contain wires of similar gauge and shielding, performance can vary greatly depend- ing on the quality of the connector. The DS32ELX0124 also has a programmable de-emphasis block on its retimed loop through output TxOUT+/-. The de- emphasis setting for the loop through driver is programmed through the SMBus. REDUNDANCY APPLICATIONS The DS32ELX0124 has two high speed CML serial inputs. SMBus register control allows the host device to monitor for errors or link loss on the active input channel. This enables the host device, usually an FPGA, to switch to the secondary input if problems occur with the primary input. LINK AGGREGATION Multiple DS32EL0421/DS32ELX0421 serializers and D32EL0124/DS32ELX0124 deserializers can be aggregated together if an application requires a data throughput of more than 3.125 Gbps. By utilizing the data valid signal of each device, the system can be properly deskewed to allow for a single cable, such as CAT-6, DVI-D, or HDMI, to carry data payloads beyond 3.125 Gbps. The ELXEVK01 evaluation kit includes sample IP for a link aggregation system to operate at an application throughput of 6.25 Gbps. Link aggregation configurations can also be implemented in applications which require longer cable lengths. In these type of applications the data rate of each serializer and deserializer chipset can be reduced, such that the applications' net data throughput is still the same. Since each high speed channel is now operating at a fraction of the original data rate, the loss over the cable is reduced, allowing for greater lengths of cable to be used in the system. For more information regarding link aggregation please see Application Note 1887, Expanding the Payload with National's FPGA-Link DS32ELX0421 and DS32ELX0124 Serializer and Deserializer. REACH EXTENSION The DS32ELX0124 deserializer contains a retimed loop through CML serial output. The loop through driver also has programmable de-emphasis making this device capable of reach extension applications. DAISY CHAINING The loop through driver of the DS32ELX0124 deserializer can be used to string together deserializers in a daisy chain con- figuration. This allows a single data source such as a DS32EL0421 serializer to communicate to multiple receiving systems. LAYOUT GUIDELINES It is important to follow good layout practices for high speed devices. The length of LVDS input traces should not exceed 40 inches. In noisy environments the LVDS traces may need to be shorter to prevent data corruption due to EMI. Noisy components should not be placed next to the LVDS or CML traces. The LVDS and CML traces must have a controlled differential impedance of 100Ω. Do not place termination re- sistors at the CML inputs or output, the DS32EL0124 and DS32ELX0124 have internal termination resistors. It is rec- ommended to avoid using vias. Each pair of vias creates an impedance mismatch in the transmission line and result in reflections, which can greatly lower the maximum distance of the high speed data link. If vias are required, they should be placed symmetrically on each side of the differential pair. For more tips and detailed suggestions regarding high speed board layout principles, please consult the LVDS Owner’s Manual. 17 www.national.com DS32EL0124/DS32ELX0124

FIGURE 12. Typical Interface Circuit

Typical Performance Characteristics The eye diagrams shown below illustrate the typical perfor- mace of the DS32ELX0124/DS32EL0124 configured with RS = 0, DC_B = 0, for the conditions listed below each figure. The PRBS-15 data was generated by a low cost FPGA, which used an LMK03000C to generate the various clock frequen- cies. The data was then sent to a DS32ELX0421 configured with RS = 0, DC_B = 0, which transmitted the data across the specified cable type and length at the specified data rate. The signal conditioning settings used for each measurement are also listed below the figures. 30043118 LVDS RxCLKOUT Output (1.25 Gbps, 40m CAT-5e, 0x000 DS32ELX0124 EQ setting, 0x10 DS32EL0421 De-Emphasis setting) 30043119 LVDS RxOUT0 Output (1.25 Gbps, 40m CAT-5e, 0x000 DS32ELX0124 EQ setting, 0x10 DS32EL0421 De-Emphasis setting) 30043120 LVDS RxCLKOUT Output (3.125 Gbps, 20m CAT-6 SCTP, 0x001 DS32ELX0124 EQ setting, 0x10 DS32EL0421 De-Emphasis setting) 30043121 LVDS RxOUT0 Output (3.125 Gbps, 20m CAT-6 SCTP, 0x001 DS32ELX0124 EQ setting, 0x10 DS32EL0421 De-Emphasis setting) 19 www.national.com DS32EL0124/DS32ELX0124

Retimed Loop Through Output (1.25 Gbps, 40m CAT-5e, 0x000 DS32ELX0124 EQ setting, 0x10 DS32EL0421 De-Emphasis setting) 30043123 Retimed Loop Through Output (3.125 Gbps, 20m CAT-6 SCTP, 0x001 DS32ELX0124 EQ setting, 0x10 DS32EL0421 De-Emphasis setting) www.national.com 20 DS32EL0124/DS32ELX0124

The register information for the deserializer is shown in the table below. Some registers have been omitted or marked as reserved; these are for internal testing and should not be writ- ten to. Some register bits require an override bit to be set before they can be written to. Addr (Hex) Name Bits Field R/W Default Description

00 Device ID 7:1 SMBus Address R/W 58'h Some systems will use all 8 bits as the

device ID. This will shift the value from 58’h to B0’h

0 Reserved 0

01 Reset 7:1 Reserved 0

0 Software Reset R/W 0 Reset the device. Does not affect device ID.

02 GPIO0 Config 7:4 GPIO0 Mode R/W 0 0000: GP Out

0001: Signal Detect RxIN0 0010: BIST Status All Others: Reserved 3:2 GPIO0 R Enable R/W 01'b 00: Pullup/Pulldown disabled 01: Pulldown Enabled 10: Pullup Enabled 11: Reserved

1 Input Enable R/W 0 0: Input buffer disabled

1: Input buffer enabled

0 Output Enable R/W 1'b 0: Output Tri-State™

1: Output enabled

03 GPIO1 Config 7:4 GPIO1 Mode R/W 0 0000: Power On Reset

0001: GP Out 0010: Signal Detect RxIN1 0011:CDR Lock All Others: Reserved 3:2 GPIO1 R Enable R/W 01'b 00: Pullup/Pulldown disabled 01: Pulldown Enabled 10: Pullup Enabled 11: Reserved 1: Input buffer enabled

0 Output Enable R/W 1 0: Output Tri-State™

1: Output enabled

04 GPIO2 Config 7:4 GPIO2 Mode R/W 0 0000: GP Out

0001: Always on Clock Out 0010: LVDS Tx CLK 0011: CDR CLK All Others: Reserved 3:2 GPIO2 R Enable R/W 01'b 00: Pullup/Pulldown disabled 01: Pulldown Enabled 10: Pullup Enabled 11: Reserved 1: Input buffer enabled 1: Output enabled

05 GP In 7:3 Reserved

2 GP In 2 R 0 Input value on GPIO2

1 GP In 1 R 0 Input value on GPIO1

0 GP In 0 R 0 Input value on GPIO0

21 www.national.com DS32EL0124/DS32ELX0124

Addr (Hex) Name Bits Field R/W Default Description

06 GP Out 7:3 Reserved 0

2 GP Out 2 R/W 0 Output value on GPIO2

1 GP Out 1 R/W 0 Output value on GPIO1

0 GP Out 0 R/W 0 Output value on GPIO0

07 — 1F Reserved

20 Device Config 0 7 LVDS Always On Clock R/W 0 1: Disable

0: When not locked switch to Always On Clock 6:3 Reserved 0

2 Reverse Data Order R/W 0 0: Normal

1: Reverse output data order

1 Reset Channel R/W 0 Reset input high speed channel

0 Digital Power Down R/W 0 Power down parallel, seria-to-

parallell, and always on clock

21 Device Config 1 7 Reserved 0

6 NRZI Decode Enable R/W 0 Enable NRZI decoding of incoming

data; requires an override bit

5 Descramble Enable R/W 0 Enabled the descrambler, requires an

4 Rx Mux R/W 0 RX_MUX_SEL control register. requires an override bit 3 Decode Bypass R/W 0 Bypass DC Balance decoder. requires an override bit 2 Training Sequence Enable R/W 0 Enable training sequence. requires an override bit 1:0 Device Configuartion R/W 0 MSB: Remote Sense enable, active low LSB: DC balance encoder enable, active low requires an override bit

22 Device Config Override 7 Reserved 0

6 NRZ Override R/W 0 Unlock bit 6 of register 21'h

5 Descramble Override R/W 0 Unlock bit 5 of register 21'h

4 Rx Mux Override R/W 0 Unlock bit 4 of register 21'h

3 Reserved 0

2 Decode Bypass Override R/W 0 Unlock bit 3 of register 21'h

1 Traning Override R/W 0 Unlock bit 2 of register 21'h

0 Device Config Override R/W 0 Unlock bits 1 and 0 of register 21'h

23 — 26 Reserved www.national.com 22 DS32EL0124/DS32ELX0124

Addr (Hex) Name Bits Field R/W Default Description 27 LVDS Per Channel Enable 7 LVDS VOD High R/W 0 0: LVDS VOD normal operation. Setting used in Electrical Characteristics Table 1: Increases VOD. Allows for longer traces to be driven, but consume more power

6 LVDS Control R/W 0 1: Allow SMBus to control LVDS per

5 RxCLKOUT Enable R/W 0 Enables RxCLKOUT output driver

4 RxOUT4 Enable R/W 0 Enables RxOUT4 output driver

3 RxOUT3 Enable R/W 0 Enables RxOUT3 output driver

2 RxOUT2 Enable R/W 0 Enables RxOUT2 output driver

1 RxOUT1 Enable R/W 0 Enables RxOUT1 output driver

0 RxOUT0 Enable R/W 0 Enables RxOUT0 output driver

28 LVDS Config 7 Reserved 0

6 LVDS Reset R/W 0 Resets LVDS block

5 LVDS Clock Rate R/W 1 0:RxCLKOUT is DDR/2

1: RxCLKOUT is DDR

4 LVDS Clock Invert R/W 0 Inverts the polarity of the RxCLKOUT

3:2 LVDS Clock Delay R/W 10'b 00: 160 ps 11: -80 ps 80 ps step size 1:0 Reserved 0 29 — 2A Reserved 2B Event Config 7:4 Reserved 0

3 Event Count Select R/W 0 0: Select CDR Event Counter for

reading. Events include loss of signal detect or loss of CDR lock. 1: Select Data Event Counter for reading

2 Reset CDR Error Count R/W 0 Resets CDR event count

1 Reset Link Error Count R/W 0 Reset data event count

0 Enable Count R/W 0 Enable event coutners

2D Error Monitor 7:5 Reserved 0

4 Accumulate Error Enable R/W 0 1: Enable counting accumulation of

3 8b/10b Error disable R/W 0 1: Disables 8b/10b decode errors from being counted or flagged on LOCK pin

2 Clear Event Counter R/W 0 1: clears errors in both the current and

previous state of teh errors count

1 Select Error Count R/W 0 0: Number of errors in current run

1: Number of errors within the selected timing window

0 Normal Error Disable R/W 0 1: Disable exiting NORMAL state

when the number of errors exceeds the error threshold 2E Error Threshold LSBs 7:0 Error Threshold R/W 10'h Error threshold above which part stops transmittion of data — LSB 2F Error Threshold MSBs 7:0 Error Threshold R/W 0 Error threshold above which part stops transmittion of data — MSB 23 www.national.com DS32EL0124/DS32ELX0124

Addr (Hex) Name Bits Field R/W Default Description 30 — 3A Reserved 3B Data Rate 7 Reserved 0 6:4 Frequency Range R 111'b 001: Reserved 010: 1 — 1.3 Gbps 011: 1.2 — 1.8 Gbps 100: 1.5 — 2.1 Gbps 101: 1.9 — 2.7 Gbps 110: 2.4 — 3.2 Gbps 111: No Lock 3:2 BIST Status R 0 00: BIST passed 01: BIST failed to capture PREAMBLE 10: BIST pattern mode failed 11: BIST data sequence failed 1 BIST Done R 0 BIST pattern done. Set when not using repeat.

0 BIST Allign Done R 0 Alignment of incoming data done

3D Event Status 7:0 Event Count R 0 Count of errors that caused a loss of link 3E Error Status LSBs 7:0 Data Error Count R 0 Number of errors in data — LSB 3F Errors Status MSBs 7:0 Data Error Count R 0 Number of errors in data — MSB 40 — 49 Reserved

49 Loop Through Driver Config 7:5 Reserved 0

4 Termination Select R/W 1 0: 75Ω

1: 50 Ω 3:1 Output Amplitude Adjust R/W 011'b 000: Level 7 001: Level 8 (Highest output) 010: Level 5 011: Level 6 (Normal output) 100: Level 4 101: Level 3 110: Level 2 111: Level 1 (Lowest output)

60 EQ Attenuator 7:4 Reserved 0

3 Attenuator 0 Override R/W 0 Overrides attenuation control in EQ 0

2 Attenuator 1 Override R/W 0 Overrides attenuation control in EQ 1

1 Attenuator 0 Enable R/W 0 1: enables attenuatorfor for EQ 0. Requires bit 3 to be set 0 Attenuator 1 Enable R/W 0 Enables attenuato for EQ 1. Requires bit 2 to be set.r www.national.com 24 DS32EL0124/DS32ELX0124

Addr (Hex) Name Bits Field R/W Default Description 61 EQ Boost Control 7:5 EQ 0 Boost Control 0 Sets EQ level for RxIN0. Requires override bit 000: Off x10: Low (or 110) x01: Mid (or 101) x11: High (or 111) 4:2 EQ 1 Boost Control 0 Sets EQ level for RxIN1. Requires override bit 000: Off x10: Low (or 110) x01: Mid (or 101) x11: High (or 111) 1:0 Reserved 0

62 Reserved

63 EQ Override Control 7 Reserved 1

6 Reserved 1

5 EQ 0 Enable R/W 1 1: Enables EQ for RxIN0

4 EQ 1 Enable R/W 0 1: Enables EQ for RxIN1

3:0 Reserved 0 64 — 66 Reserved

67 LT De-Emphasis Control 7 Reserved 0

6:5 De-Emphasis Setting 0 00: Off 01: Low 10: Med 11: Max 4:0 Reserved 0 25 www.national.com DS32EL0124/DS32ELX0124

Physical Dimensions inches (millimeters) unless otherwise noted (See AN-1187 for PCB Design and Assembly Recommendations) www.national.com 26 DS32EL0124/DS32ELX0124

27 www.national.com DS32EL0124/DS32ELX0124

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