DS32B35

DS32X35 MAXIM | Alldatasheet

Document overview

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Technical content

Features

o Integrated 32.768kHz Crystal o Fast (400kHz) I2C Interface o RTC Counts Seconds, Minutes, Hours, Day, Date, Month, and Year with Leap Year Compensation Valid Up to 2100 o RTC Accuracy ±2ppm from 0°C to +40°C o RTC Accuracy ±3.5ppm from -40°C to 0°C and +40°C to +85°C o Nonvolatile Memory with 10 Years of Guaranteed Backup Time and Write Protection o Two Available Densities of Nonvolatile Memory

2048 Bytes (DS32B35)

8192 Bytes (DS32C35)

o No Cycle Limitations on Memory o Power-Switching Circuit Selects Between Main Power and Battery Backup for the RTC o Programmable Square Wave with Frequency of 32.768kHz, 8.192kHz, 4.096kHz, or 1Hz o Two Time-of-Day Alarms o Reset Output/Pushbutton Reset (Debounced) Input o Programmable Output Provides Interrupt or Square Wave o Calibrated 32.768kHz Open-Drain Output o Temp Sensor with ±3°C Accuracy o 3.3V Operating Voltage o Commercial and Industrial Temperature Ranges o 300-mil, 20-Pin SO Package o Underwriters Laboratories (UL) Recognized DS32x35 Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Rev 0; 12/06 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Pin Configuration and Ordering Information appear at end of data sheet. DS32x35 VCC SCL RPU RPU = tR/CB RPU INT/SQW 32kHz VBAT PUSHBUTTON RESET SDA RST N.C. N.C. N.C. N.C. N.C. VCC VCC GND VCC CPU N.C. GND N.C. N.C. N.C. SCL WP Typical Operating Circuit

Accurate I2C RTC with Integrated TCXO/Crystal/FRAM ABSOLUTE MAXIMUM RATINGS RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. IPC/JEDEC J-STD-020 Specification PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC 2.70 3.3 3.63 V Battery Voltage V BAT (Note 3) 2.3 3.0 3.6 V Input High Voltage V IH (Note 4) 0.7 x VCC VCC + 0.3 V Input Low Voltage V IL -0.3 +0.3 x VCC V

ELECTRICAL CHARACTERISTICS

(VCC = 2.7V to 3.63V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Accessing RTC registers 260 Active Supply Current I CCA VCC = 3.63V, SCL = 400kHz (Note 5) Accessing FRAM memory 260 µA Standby Supply Current I CCS VCC = 3.63V, SCL = 0kHz, 32kHz on, SQW off (Note 5) 110 µA Temperature Conversion Current I TC VCC = 3.65V, SCL = 0kHz, 32kHz on, SQW off 575 µA Power-Fail Voltage V PF 2.45 2.575 2.70 V Logic 0 Output 32kHz, INT/SQW, SDA VOL IOL = 3mA 0.4 V Logic 0 Output RST VOL IOL = 1mA 0.4 V Output Leakage Current 32kHz, INT/SQW, SDA ILEAK Output high impedance -1 +1 µA Input Leakage SCL ILI -1 +1 µA RST I/O Leakage IOL RST high impedance (Note 6) -200 +10 µA VIN = VIL(MAX) 50 kΩ WP Input Resistance RIN VIN = VIH(MIN) 1 MΩ

Accurate I2C RTC with Integrated TCXO/Crystal/FRAM ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.7V to 3.63V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VBAT Leakage Current (VCC Active) IBATLKG 25 100 nA Output Frequency fOUT VCC = 3.3V or VBAT = 3.3V 32.768 kHz 0°C to +40°C -2 +2 Frequency Stability vs. Temperature Δf/fOUT VCC = 3.3V or VBAT = 3.3V ppm Frequency Stability vs. Voltage Δf/V 1 ppm/V -40°C 0.7 +25°C 0.1 +70°C 0.4 Frequency Sensitivity per LSB Δf/LSB Specified at: +85°C 0.8 ppm Temperature Sensor Accuracy Temp V CC = 3.3V or VBAT = 3.3V -3 +3 °C Temperature Conversion Time t CONV 125 200 ms (VCC = 0V, VBAT = 2.3V to 3.6V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Active Battery Current I BATA EOSC = 0, BBSQW = 0, SCL = 400kHz (Note 5) VBAT = 3.6V 70 µA Timekeeping Battery Current I BATT EOSC = 0, BBSQW = 0, EN32kHz = 1, SCL = SDA = 0V or SCL = SDA = VBAT (Note 5) VBAT = 3.6V 0.84 3.0 µA Temperature Conversion Current I BATTC EOSC = 0, BBSQW = 0, SCL = SDA = 0V or SCL = SDA = VBAT VBAT = 3.6V 575 µA Data-Retention Current I BATDR EOSC = 1, SCL = SDA = 0V, +25°C 100 nA

Accurate I2C RTC with Integrated TCXO/Crystal/FRAM AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V to 3.63V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Fast mode 100 400 SCL Clock Frequency f SCL Standard mode 0 100 kHz Fast mode 1.3 Bus Free Time Between STOP and START Conditions tBUF Standard mode 4.7 μs Fast mode 0.6 Hold Time (Repeated) START Condition (Note 7) tHD:STA Standard mode 4.0 μs Fast mode 1.3 Low Period of SCL Clock t LOW Standard mode 4.7 μs Fast mode 0.6 High Period of SCL Clock t HIGH Standard mode 4.0 μs Fast mode 0 0.9 Data Hold Time (Notes 8, 9) t HD:DAT Standard mode 0 μs Fast mode 100 Data Setup Time (Note 10) t SU:DAT Standard mode 250 ns Fast mode 0.6 Setup Time for Repeated START Condition tSU:STA Standard mode 4.7 μs Fast mode 300 Rise Time of Both SDA and SCL Signals (Note 11) tR Standard mode 20 + 0.1CB 1000 ns Fast mode 300 Fall Time of Both SDA and SCL Signals (Note 11) tF Standard mode 20 + 0.1CB 300 ns Fast mode 0.6 Setup Time for STOP Condition t SU:STO Standard mode 4.0 μs Capacitive Load for Each Bus Line (Note 11) CB 400 pF

10 I/O Capacitance

INT/SQW, 32kHz, SCL, SDA CI/O Outputs = high impedance pF Pushbutton Debounce PB DB (See the Pushbutton Reset Timing diagram) 250 ms Reset Active Time t RST 250 ms Oscillator Stop Flag (OSF) Delay t OSF (Note 12) 100 ms FRAM Data Retention t DR 10 Years

Accurate I2C RTC with Integrated TCXO/Crystal/FRAM POWER-SWITCH CHARACTERISTICS (TA = -40°C to +85°C, Note 1, see the Power-Switch Timing diagram.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF 300 µs VCC Rise Time; VPF(MIN) to VPF(MAX) tVCCR 0µ s Recovery at Power-Up t REC (Note 13) 2 ms Note 1: Limits at -40°C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground. Note 3: To minimize current drain on VBAT when the internal supply is switched to VBAT, the VIH minimum must be higher than VBAT - 0.6V. Otherwise, there is significant current drain due to the input stage at the SCL and SDA pins. Note 4: The pullup resistor voltage on the 32kHz and INT/SQW pins can be up to 5.5V maximum regardless of the voltage on VCC. Note 5: Current is the averaged input current, which includes the temperature conversion current. Note 6: The RST pin has an internal 50kΩ (nominal) pullup resistor to VCC. Note 7: After this period, the first clock pulse is generated. Note 8: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH(MIN) of the SCL sig- nal) to bridge the undefined region of the falling edge of SCL. Note 9: The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 10: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 11: CB—total capacitance of one bus line in pF. Note 12: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤ VCC ≤ VCC(MAX) and 2.0V ≤ VBAT ≤ 3.6V. Note 13: This delay applies only if the oscillator is enabled and running. If the EOSC bit is a 1, tREC is bypassed and RST immediate- ly goes high. WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.

Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Pushbutton Reset Timing tRSTPBDB RST Power-Switch Timing VCC tVCCF tVCCR tREC VPF(MAX) VPF VPF VPF(MIN) RST

Accurate I2C RTC with Integrated TCXO/Crystal/FRAM SUPPLY CURRENT vs. TEMPERATURE DS32x35 toc03 TEMPERATURE (°C) IBAT (μA) 0.700 0.800 0.900 1.000 0.600 -40.0 VBAT = 3.0V VCC = 0V BSY = 0, SDA = SCL = V BAT OR VCC FREQUENCY DEVIATION vs. TEMPERATURE vs. AGING VALUE DS32x35 toc04 CRYSTAL AGING REGISTER VALUE FREQUENCY DEVIATION (ppm) 96640 32-64 -32-96 -40 -30 -20 -10 -128 128 +85°C -40°C +70°C 0°C +40°C -40°C +85°C +25°C +40°C +25°C +70°C 0°C STANDBY SUPPLY CURRENT vs. SUPPLY VOLTAGE DS32x35 toc01 VCC (V) ICCS (μA) 5.04.03.0 100 150 2.0 RST ACTIVE BSY = 0, SDA = SCL = VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE DS32x35 toc02 VBAT (V) IBAT (μA) 5.04.03.0 0.800 0.900 1.000 1.100 1.200 0.700 2.0 VCC = 0VBSY = 0, SDA = SCL = VBAT OR VCC Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.)

Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Block Diagram N N N RST VCC 32kHz INT/SQW CLOCK AND CALENDAR REGISTERS USER BUFFER (7 BYTES) I2C INTERFACE AND ADDRESS REGISTER DECODE POWER CONTROL VCC WP SCL VBAT GND SCL SDA TEMPERATURE SENSOR FRAM CONTROL LOGIC/ DIVIDER PUSHBUTTON RESET; SQUARE-WAVE BUFFER; INT/SQW CONTROL CONTROL AND STATUS REGISTERS OSCILLATOR AND CAPACITOR ARRAY DS32x35

Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Pin Description PIN NAME FUNCTION 1W P Write Protect. When WP is high, the entire FRAM memory array is write protected. When WP is low, all addresses can be written. This pin is internally pulled down. 7–14 N.C. No Connection. Must be connected to ground. 3 32kHz 32kHz Output. This open-drain pin requires an external pullup resistor. When enabled, the output operates on either power supply. It can be left open if not used. 4V CC DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1µF to 1.0µF capacitor.

5 INT/SQW

Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor connected to V C C or another supply of 5.5V or less. It can be left open if not used. This multifunction pin is determined by the state of the INTCN bit in the Control register (0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency is determined by the RS2 and RS1 bits. When INTCN is set to logic 1, a match between the timekeeping registers and either of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms disabled.

6 RST

Acti ve- Low Reset. Thi s p i n i s an op en- d r ai n i np ut/outp ut. It i nd i cates the status of V C C r el ati ve to the V P F sp eci fi cati on. As V C C fal l s b el ow V P F , the RS T p i n i s d r i ven l ow . W hen V C C exceed s V P F , for tR S T, the op en- d r ai n p ul l d ow n tr ansi stor i s shut off, and the i nter nal p ul l up r esi stor p ul l s the RS T p i n to V C C . The acti ve- l ow , op en- d r ai n outp ut i s com b i ned w i th a d eb ounced p ushb utton i np ut functi on. Thi s p i n can b e acti vated b y a p ushb utton r eset r eq uest. It has an i nter nal 50kΩ nom i nal val ue p ul l up r esi stor to V C C . N o exter nal p ul l up r esi stor s shoul d b e connected . If the E O SC b i t i s 1, tR E C i s b yp assed and RS T i m m ed i atel y g oes hi g h. 15, 19 GND Ground. Must be connected together to ground.

16 V BAT

Backup Power-Supply Input. This pin should be decoupled using a 0.1µF to 1.0µF low-leakage capacitor. If the I2C interface is inactive whenever the device is powered by the VB A T input, the decoupling capacitor is not required. If VB A T is not used, connect to ground. UL recognized to ensure against reverse charging when used with a lithium battery. Go to www.maxim-ic.com/qa/info/ul. 17 SDA Serial Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain pin requires an external pullup resistor. 18, 20 SCL Serial Clock Input. These pins are the clock input for the I2C serial interface and are used to synchronize data movement on the serial interface. Detailed Description The DS32x35 accurate RTC is a temperature-compen- sated clock/calendar that includes an integrated 32.768kHz crystal and a bank of nonvolatile memory in a single package. The nonvolatile memory is available in two sizes: 2048 x 8 or 8192 x 8 bits. The integration of the crystal resonator enhances the long-term accura- cy of the device as well as reduces the piece part count in a manufacturing line. The device is available in both commercial and industrial temperature ranges and is offered in a 300-mil, 20-pin SO package. The DS32x35 includes a bank of nonvolatile memory that does not require a backup energy source to main- tain the memory contents. In addition, there are no read or write cycle limitations. The memory array can be accessed at maximum cycle rates for the life of the product with no wear-out mechanisms. A precision temperature-compensated reference and comparator circuit monitors the status of V CC and auto- matically switches to the backup supply when neces- sary. Other device features include two time-of-day alarms, a selectable output that provides either an interrupt or programmable square wave, and a calibrat- ed 32.768kHz square-wave output. A reset input/output pin provides a power-on reset. Additionally, the reset pin is monitored as a pushbutton input for generating a reset externally. The device is accessed through an I serial interface.

tions are described separately in the following sections. user-initiated temperature conversion is completed. is powered by VBAT. See Table 1. not be accessed when VCC < VCC(MIN). RST is also used to indicate a power-fail condition. the 24-hour or 12-hour format with an AM/PM indicator. selection is controlled by the bit INTCN. Table 1. Device Operation be done to avoid FRAM data errors.

I2C Serial Data Bussection for details. when V CC is below the minimum operating voltage. programmed, and the data may not be retained. registers update during a read. The day-of-week register increments at midnight. time and date entries result in undefined operation. case the main registers update during a read. Table 2. Memory Slave Address

Table 3. RTC Register Map a 1 or 0, but always read back as 0.

10 Hour

10 Hour Hour Alarm 2 Hours 1–12 + AM/PM

The DS32x35 contains two time-of-day/date alarms. Alarm 1 can be set by writing to registers 07h to 0Ah. Alarm 2 can be set by writing to registers 0Bh to 0Dh. will result in illogical operation. Table 4. Alarm Mask Bits X 1 1 1 1 Alarm once per second. X 1 1 1 0 Alarm when seconds match. X 1 1 0 0 Alarm when minutes and seconds match. X 1 0 0 0 Alarm when hours, minutes, and seconds match. 0 0 0 0 0 Alarm when date, hours, minutes, and seconds match. 1 0 0 0 0 Alarm when day, hours, minutes, and seconds match. X 1 1 1 Alarm once per minute (00 seconds of every minute). X 1 1 0 Alarm when minutes match. X 1 0 0 Alarm when hours and minutes match. 0 0 0 0 Alarm when date, hours, and minutes match. 1 0 0 0 Alarm when day, hours, and minutes match.

This bit is clear (logic 0) when power is first applied. always on regardless of the status of the EOSC bit. square-wave or interrupt output when V CC is absent. happen when a conversion is not already in progress. when power is first applied. is set to logic 1 when power is first applied. status register to assert INT/SQW (when INTCN = 1). logic 0, the A2F bit does not initiate an interrupt signal. status register to assert INT/SQW (when INTCN = 1).

1 X X A2F + A1F 1 1 1

Table 5. Interrupt/Square-Wave Output

Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Status Register (0Fh) Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period and may be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltages present on both V CC and V BAT are insufficient to support oscillation. 3) The EOSC bit is turned off in battery-backed mode. 4) External influences on the crystal (i.e., noise, leak- age, etc.). This bit remains at logic 1 until written to logic 0. Bit 3: Enable 32kHz Output (EN32kHz). This bit con- trols the status of the 32kHz pin. When set to logic 1, the 32kHz pin is enabled and outputs a 32.768kHz square-wave signal. When set to logic 0, the 32kHz pin goes to a high-impedance state. The initial power-up state of this bit is logic 1, and a 32.768kHz square-wave signal appears at the 32kHz pin after a V CC is applied to the DS32x35. Bit 2: Busy (BSY). This bit indicates the device is busy executing TCXO functions. It goes to logic 1 when the conversion signal to the temperature sensor is asserted and then is cleared when the device is in the 1-minute idle state. When active, the BSY signal prevents the CONV signal from aborting the execution of the TCXO algorithm and starting a new execution of TCXO function. Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 regis- ters. If the A2IE bit is logic 1 and the INTCN bit is set to logic 1, the INT /SQW pin is also asserted. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 regis- ters. If the A1IE bit is logic 1 and the INTCN bit is set to logic 1, the INT /SQW pin is also asserted. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Aging Offset Register (10h) The Aging Offset register provides an 8-bit code to add to the codes in the capacitance array registers. The code is encoded in two’s complement. One LSB repre- sents one small capacitor to be switched in or out of the capacitance array at the crystal pins. The change in ppm per LSB is different at different temper- atures. The frequency vs. temperature curve is distorted by the values used in this register. At +23°C, one LSB typi- cally provides approximately 0.1ppm change in frequency. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Sign Data Data Data Data Data Data Data Aging Offset (10h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OSF 0 0 0 EN32kHz BSY A2F A1F Status Register (0Fh)

Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Temperature Registers (11h–12h) Temperature is represented as a 10-bit code with a res- olution of +0.25°C and is accessible at location 11h and 12h. The temperature is encoded in two’s comple- ment format. The upper 8 bits are at location 11h, and the lower 2 bits are in the upper nibble at location 12h. Upon power reset, the registers are set to a default temperature of 0°C and the controller starts a tempera- ture conversion. New temperature readings are stored in this register. FRAM Address Map During a multibyte access, the address pointer wraps around to location 00h when it reaches the end of the register space. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Sign Data Data Data Data Data Data Data Temperature Register (Upper Byte) (11h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Data Data 0 00000 Temperature Register (Lower Byte) (12h) ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RANGE 000h D7 D6 D5 D4 D3 D2 D1 D0 00–FF : :::::::: : 7FFh D7 D6 D5 D4 D3 D2 D1 D0 00–FF DS32B35 FRAM Register Map ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RANGE 000h D7 D6 D5 D4 D3 D2 D1 D0 00–FF : :::::::: : 1FFFh D7 D6 D5 D4 D3 D2 D1 D0 00–FF DS32C35 FRAM Register Map

Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low, while the clock line is high, defines a START condition. Stop data transfer: A change in the state of the data line from low to high, while the clock line is high, defines a STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and the STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associ- ated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. Depending upon the state of the R/ W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a num- ber of data bytes. The slave returns an acknowl- edge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. Data is transferred with the most significant bit (MSB) first. The DS32x35 can operate in the following two modes: 1) Slave receiver mode (DS32x35 write mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recog- nized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (see Figures 3, 5, and 7). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains one of the 7-bit DS32x35 addresses. The slave address is 1101000 for the RTC. For the DS32B35 FRAM, the first four bits are 1010, and the next three bits select one of eight blocks of data (see Table 2). For the DS32C35 FRAM, the first seven bits are 1010000. Each slave address is followed by the direction bit (R/ W), which is zero for a write. After receiving and decoding the slave address byte, the device outputs an acknowledge on the SDA line. After the device acknowledges the slave address and write bit, the master transmits a register address to the device. For the DS32C35, the master transmits two bytes for the register address information. This sets the register pointer on the device. After setting the register address, the master then transmits zero or more bytes of data with the DS32x35 acknowl- edging each byte received. The master generates a STOP condition to terminate the data write.

Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. Chip Information SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS Thermal Information Theta-JA: +73°C/W Theta-JC: +23°C/W SCL GND SCL SDAV CC 32kHz N.C. WP TOP VIEW VBAT GND N.C. N.C.N.C. N.C. RST INT/SQW N.C. N.C.N.C. N.C. SO DS32x35 Pin Configuration

Package Information

For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.

Revision History

Rev 0; 12/06: Initial data sheet release.

Ordering Information

PART TEMP RANGE FRAM DENSITY PIN-PACKAGE TOP† MARK DS32B35-33# 0°C to +70°C 2k x 8 20 SO DS32B35 DS32B35-33IND# -40°C to +85°C 2k x 8 20 SO DS32B35 DS32C35-33# 0°C to +70°C 8k x 8 20 SO DS32C35 DS32C35-33IND# -40°C to +85°C 8k x 8 20 SO DS32C35 PACKAGE DOCUMENT NO. 20-pin SO (300 mils) 56-G4009-001 # Denotes a RoHS-compliant device that may include lead that is exempt under RoHS requirements. The lead finish is JESD97 cate- gory e3, and is compatible with both lead-based and lead-free soldering processes. A "#" anywhere on the top mark denotes a RoHS-compliant device. †An “N” anywhere on the top mark denotes an industrial grade device.