DS3232S-

DS3232_08 MAXIM | Alldatasheet

Document overview

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Technical content

Features

♦ Accuracy ±2ppm from 0°C to +40°C ♦ Accuracy ±3.5ppm from -40°C to +85°C ♦ Battery Backup Input for Continuous Timekeeping ♦ Operating Temperature Ranges Commercial: 0°C to +70°C Industrial: -40°C to +85°C ♦ 236 Bytes of Battery-Backed SRAM ♦ Low-Power Consumption ♦ Real-Time Clock Counts Seconds, Minutes, Hours, Day, Date, Month, and Year with Leap Year Compensation Valid Up to 2099 ♦ Two Time-of-Day Alarms ♦ Programmable Square-Wave Output ♦ Fast (400kHz) I 2C Interface ♦ 3.3V Operation ♦ Digital Temp Sensor Output: ±3°C Accuracy ♦ Register for Aging Trim ♦ RST Input/Output ♦ 300-Mil, 20-Pin SO Package ♦ Underwriters Laboratories (UL®) Recognized DS3232 Extremely Accurate I2C RTC with Integrated Crystal and SRAM Rev 4; 10/08 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

DS3232S# 0°C to +70°C 20 SO DS3232 DS3232SN# -40°C to +85°C 20 SO DS3232N UL is a registered trademark of Underwriters Laboratories, Inc. DS3232 VCC SCL RPU RPU = tR / CB RPU INT/SQW 32kHz VBAT PUSH- BUTTON RESET SDA RST N.C. N.C. N.C. N.C. VCC VCC GND VCC μP N.C. N.C. N.C. N.C. N.C. N.C. N.C. SCL RST SDA Typical Operating Circuit # Denotes a RoHS-compliant device that may include lead that is exempt under the RoHS requirements. Lead finish is JESD97 Category e3, and is compatible with both lead-based and lead-free soldering processes. A "#" anywhere on the top mark denotes a RoHS-compliant device. TOP VIEW SCL N.C. SCL SDAV CC 32kHz N.C. N.C. VBAT GND N.C. N.C.N.C. N.C. RST INT/SQW N.C. N.C.N.C. N.C. SO DS3232 Pin Configuration

Extremely Accurate I2C RTC with Integrated Crystal and SRAM ABSOLUTE MAXIMUM RATINGS RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on VCC, VBAT, 32kHz, SCL, SDA, RST, Operating Temperature Range Lead Temperature J-STD-020 Specification PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC 2.3 3.3 5.5 Supply Voltage VBAT 2.3 3.0 5.5 V Logic 1 Input SDA, SCL V IH 0.7 x VCC VCC + 0.3 V Logic 0 Input SDA, SCL V IL -0.3 +0.3 x VCC V

ELECTRICAL CHARACTERISTICS

(VCC = 2.3V to 5.5V, V CC = active supply (see Table 1), T A = -40°C to +85°C, unless otherwise noted.) (Typical values are at VCC = 3.3V, VBAT = 3.0V, and TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC = 3.3V 200 Active Supply Current I CCA 32kHz output off (Notes 3, 4) VCC = 5.5V 325 μA VCC = 3.3V 120 Standby Supply Current I CCS I2C bus inactive, 32kHz output off, SQW output off (Note 4) VCC = 5.5V 160 μA VCC = 3.3V 500 Temperature Conversion Current I CCSCONV I2C bus inactive, 32kHz output off, SQW output off VCC = 5.5V 600 μA Power-Fail Voltage V PF 2.45 2.575 2.70 V ACTIVE SUPPLY (Table 1 ) (2.3V to 5.5V, T A = -40°C to +85°C, unless otherwise noted) (Note 1) Logic 1 Output, 32kHz IOH = -1mA IOH = -0.75mA IOH = -0.14mA VOH Active supply > 3.3V, 3.3V > active supply > 2.7V, 2.7V > active supply > 2.3V 2.0 V

Extremely Accurate I2C RTC with Integrated Crystal and SRAM ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.3V to 5.5V, V CC = active supply (see Table 1), T A = -40°C to +85°C, unless otherwise noted.) (Typical values are at VCC = 3.3V, VBAT = 3.0V, and TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Logic 0 Output, INT/SQW, SDA V OL I OL = 3mA 0.4 V Logic 0 Output, RST, 32kHz V OL I OL = 1mA 0.4 V Output Leakage Current 32kHz, INT/SQW, SDA ILO Output high impedance -1 0 +1 μA Input Leakage SCL I LI -1 +1 μA RST Pin I/O Leakage I OL RST high impedance (Note 5) -200 +10 μA TCXO Output Frequency f OUT V CC = 3.3V or VBAT = 3.3V 32.768 kHz Duty Cycle (Revision A3 Devices) 2.97V VCC < 3.63 31 69 % 0°C to +40°C -2 +2 Frequency Stability vs. Temperature f/fOUT VCC = 3.3V or VBAT = 3.3V -40°C to 0°C and ppm Frequency Stability vs. Voltage f/V V CC = 3.3V or VBAT = 3.3V 1 ppm/V -40°C 0.7 +25°C 0.1 +70°C 0.4 Trim Register Frequency Sensitivity per LSB f/LSB Specified at: +85°C 0.8 ppm Temperature Accuracy Temp V CC = 3.3V or VBAT = 3.3V -3 +3 °C First year ±1.0 Crystal Aging f/f0 After reflow, not production tested 0–10 years ±5.0 ppm (VCC = 0V, VBAT = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VBAT = 3.3V 80 Active Battery Current (Note 4) IBATA EOSC = 0, BBSQW = 0, SCL = 400kHz, BB32kHz = 0 VBAT = 5.5V 200 μA VBAT = 3.4V 1.5 2.5 Timekeeping Battery Current (Note 4) IBATT EOSC = 0, BBSQW = 0, SCL = SDA = 0V, BB32kHz = 0, CRATE0 = CRATE1 = 0 VBAT = 5.5V 1.5 3.0 μA Temperature Conversion Current I BATTC EOSC = 0, BBSQW = 0, SCL = SDA = 0V 600 μA Data-Retention Current I BATTDR EOSC = 1, SCL = SDA = 0V, +25°C 100 nA

Extremely Accurate I2C RTC with Integrated Crystal and SRAM AC ELECTRICAL CHARACTERISTICS (Active supply (see Table 1) = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Fast mode 100 400SCL Clock Frequency f SCL Standard mode 0.04 100 kHz Fast mode 1.3Bus Free Time Between STOP and START Conditions tBUF Standard mode 4.7 µs Fast mode 0.6Hold Time (Repeated) START Condition (Note 6) tHD:STA Standard mode 4.0 µs Fast mode 1.3 25,000Low Period of SCL Clock t LOW Standard mode 4.7 25,000 µs Fast mode 0.6High Period of SCL Clock t HIGH Standard mode 4.0 µs Fast mode 0 0.9Data Hold Time (Notes 7, 8) t HD:DAT Standard mode 0 0.9 µs Fast mode 100Data Setup Time (Note 9) t SU:DAT Standard mode 250 ns Fast mode 0.6Start Setup Time t SU:STA Standard mode 4.7 µs Fast mode 300Rise Time of Both SDA and SCL Signals (Note 10) tR Standard mode 20 + 0.1CB 1000 ns Fast mode 300Fall Time of Both SDA and SCL Signals (Note 10) tF Standard mode 20 + 0.1CB 300 ns Fast mode 0.6Setup Time for STOP Condition t SU:STO Standard mode 4.7 µs Capacitive Load for Each Bus Line (Note 10) CB 400 pF Capacitance for SDA, SCL C I/O 10 pF Pulse Width of Spikes That Must Be Suppressed by the Input Filter tSP 30 ns Pushbutton Debounce PB DB 250 ms Interface Timeout t IF (Note 11) 25 35 ms Reset Active Time t RST 250 ms Oscillator Stop Flag (OSF) Delay t OSF (Note 12) 100 ms Temperature Conversion Time t CONV 125 200 ms POWER-SWITCH CHARACTERISTICS (TA = -40°C to +85°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF 300 µs VCC Rise Time; VPF(MIN) to VPF(MAX) tVCCR 0µ s Recovery at Power-Up t REC (Note 13) 125 300 ms

Extremely Accurate I2C RTC with Integrated Crystal and SRAM Pushbutton Reset Timing tRSTPBDB RST Power-Switch Timing VCC VPF(MAX) RST VPF(MIN) tVCCF tVCCR tREC VPF VPF

Extremely Accurate I2C RTC with Integrated Crystal and SRAM Data Transfer on I2C Serial Bus SCL NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). SDA STOP START REPEATED START tBUF tHD:STA tHD:DAT tSU:DAT tSU:STO tHD:STA tSP tSU:STA tHIGH tR tF tLOW Note 1: Limits at -40°C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground. Note 3: ICCA—SCL clocking at max frequency = 400kHz. Note 4: Current is the averaged input current, which includes the temperature conversion current. Note 5: The RST pin has an internal 50kΩ (nominal) pullup resistor to VCC. Note 6: After this period, the first clock pulse is generated. Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 8: The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 10: CB—total capacitance of one bus line in pF. Note 11: Minimum operating frequency of the I2C interface is imposed by the timeout period. Note 12: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0V ≤ VCC ≤ VCC(MAX) and 2.3V ≤ VBAT ≤ 3.4V. Note 13: This delay only applies if the oscillator is enabled and running. If the EOSC bit is 1, tREC is bypassed and RST immediately goes high. WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.

Extremely Accurate I2C RTC with Integrated Crystal and SRAM STANDBY SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3232 toc01 VCC (V) SUPPLY CURRENT (nA) 100 150 125 2.3 RST ACTIVE SCL = SDA = VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3232 toc02 VBAT (V) SUPPLY CURRENT (nA) 800 900 1000 950 850 750 700 2.3 VCC = 0V BB32kHz = 0 BBSQW = 0 BSY = 0 SUPPLY CURRENT vs. TEMPERATURE DS3232 toc03 TEMPERATURE (°C) SUPPLY CURRENT (μA) 806040-20 02 0 0.700 0.800 0.900 0.600 -40 VCC = 0V BB32kHz = 0 VBAT = 3.4V VBAT = 3.0V FREQUENCY DEVIATION vs. TEMPERATURE vs. AGING DS3232 toc04 TEMPERATURE (°C) FREQUENCY DEVIATION (ppm) 806040-20 02 0 -15 -25 -35 -45 -40 AGING = -128 AGING = -33 AGING = +127 AGING = 0 AGING = +32 Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) DELTA TIME AND FREQUENCY vs. TEMPERATURE TEMPERATURE (°C) DELTA FREQUENCY (ppm) DELTA TIME (MIN/YEAR) 807050 60-10 0 10 20 30 40-30 -20 -180 -160 -140 -120 -100 -80 -60 -40 -20 -200 -80 -60 -40 -20 -100 -40 DS3232 toc05 CRYSTAL +20ppm CRYSTAL -20ppm TYPICAL CRYSTAL, UNCOMPENSATED DS3232 ACCURACY BAND

Extremely Accurate I2C RTC with Integrated Crystal and SRAM Block Diagram N N RST VCC INT/SQW CLOCK AND CALENDAR REGISTERS SRAM USER BUFFER (7 BYTES) I2C INTERFACE AND ADDRESS REGISTER DECODE POWER CONTROL VCC VBAT GND SCL SDA TEMPERATURE SENSOR CONTROL LOGIC/ DIVIDER SQUARE-WAVE BUFFER; INT/SQW CONTROL CONTROL AND STATUS REGISTERS VOLTAGE REFERENCE; DEBOUNCE CIRCUIT; PUSHBUTTON RESET OSCILLATOR AND CAPACITOR ARRAY DS3232 32kHz Detailed Description The DS3232 is a serial RTC driven by a temperature- compensated 32kHz crystal oscillator. The TCXO pro- vides a stable and accurate reference clock, and maintains the RTC to within ±2 minutes per year accu- racy from -40°C to +85°C. The TCXO frequency output is available at the 32kHz pin. The RTC is a low-power clock/calendar with two programmable time-of-day alarms and a programmable square-wave output. The INT/SQW provides either an interrupt signal due to alarm conditions or a square-wave output. The clock/cal- endar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. The internal registers are accessible though an I 2C bus interface. A temperature-compensated voltage reference and comparator circuit monitors the level of V CC to detect

Extremely Accurate I2C RTC with Integrated Crystal and SRAM Pin Description PIN NAME FUNCTION 1, 2, 3 32kHz 32kHz Push-Pull Output. If disabled with either EN32kHz = 0 or BB32kHz = 0, the state of the 32kHz pin will be low. 4 V CC DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1μF to 1.0μF capacitor.

5 INT/SQW

Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor. It can be left open if not used. This multifunction pin is determined by the state of the INTCN bit in the Control Register (0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency is determined by RS2 and RS1 bits. When INTCN is set to logic 1, then a match between the timekeeping registers and either of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms disabled. The pullup voltage can be up to 5.5V, regardless of the voltage on V CC. If not used, this pin can be left floating.

6 RST

Active-Low Reset. This pin is an open-drain input/output. It indicates the status of V CC relative to the VPF specification. As V CC falls below V PF, the RST pin is driven low. When V CC exceeds VPF, for tRST, the RST pin is driven high impedance. The active-low, open-drain output is combined with a debounced pushbutton input function. This pin can be activated by a pushbutton reset request. It has an internal 50k nominal value pullup resistor to V CC. No external pullup resistors should be connected. If the crystal oscillator is disabled, t RST is bypassed and RST immediately goes high.

15 GND Ground

16 V BAT

Backup Power-Supply Input. This pin should be decoupled using a 0.1μF to 1.0μF low-leakage capacitor. If the I2C interface is inactive whenever the device is powered by the V BAT input, the decoupling capacitor is not required. If V BAT is not used, connect to ground. Diodes placed in series between the V BAT pin and the battery can cause improper operation. UL recognized to ensure against reverse charging when used with a lithium battery. Go to www.maxim-ic.com/qa/info/ul. 17 SDA Serial-Data Input/Output. This pin is the data input/output for the I 2C serial interface. This open-drain pin requires an external pullup resistor. The pullup voltage can be up to 5.5V, regardless of the voltage on V CC. 18, 20 SCL Serial-Clock Input. This pin is the clock input for the I 2C serial interface and is used to synchronize data movement on the serial interface. A connection to only one of the pins is required. The other pin must be connected to the same signal or be left floating. Up to 5.5V can be used for this pin, regardless of the voltage on V CC. power failures and to automatically switch to the back- up supply when necessary. The RST pin provides an external pushbutton function and acts as an indicator of a power-fail event. Also available are 236 bytes of gen- eral-purpose battery-backed SRAM. Operation The block diagram shows the main elements of the DS3232. The eight blocks can be grouped into four functional groups: TCXO, power control, pushbutton function, and RTC. Their operations are described sep- arately in the following sections. 32kHz TCXO The temperature sensor, oscillator, and control logic form the TCXO. The controller reads the output of the on-chip temperature sensor and uses a lookup table to determine the capacitance required, adds the aging correction in AGE register, and then sets the capaci- tance selection registers. New values, including changes to the AGE register, are loaded only when a change in the temperature value occurs. The tempera- ture is read on initial application of V CC and once every 64 seconds (default, see the description for CRATE1 and CRATE0 in the control/status register) afterwards.

but greater than VBAT, the DS3232 is powered by V CC. device is powered by VBAT. See Table 1. abled by setting the EOSC bit. the end system is waiting to be shipped to a customer. DS3232 debounces the switch by pulling the RST low. fail signal is generated, which forces the RST pin low. held low for t REC to allow the power supply to stabilize. the 24-hour or 12-hour format with an AM/PM indicator. selection is controlled by the bit INTCN. main registers update during a read. Table 1. Power Control

low while SCL is high, generating a START condition. byte of data is not written. or initialized by writing the appropriate register bytes. Figure 1. Address Map for DS3232 Timekeeping Registers and SRAM Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.

10 Hour

10 Hour Hour Hours 1–12 + AM/PM

10 Hour Hour Alarm 1 Hours 1–12 + AM/PM

10 Hour Hour Alarm 2 Hours 1–12 + AM/PM

The day-of-week register increments at midnight. time and date entries result in undefined operation. ters in case the main registers update during a read. not listed in the table result in illogical operation. a match with day of the week. per-second update of the time and date registers. Table 2. Alarm Mask Bits

The DS3232 has two additional registers (control and control/status) that control the real-time clock, alarms, and square-wave output. Control Register (0Eh) Bit 7: Enable Oscillator ( EOSC). When set to logic 0, the oscillator is started. When set to logic 1, the oscilla- tor is stopped when the DS3232 switches to battery power. This bit is clear (logic 0) when power is first applied. When the DS3232 is powered by V CC, the oscillator is always on regardless of the status of the EOSC bit. When EOSC is disabled, all register data is static. Bit 6: Battery-Backed Square-Wave Enable (BBSQW). When set to logic 1 and the DS3232 is being powered by the V BAT pin, this bit enables the square-wave output or interrupt when V CC is absent. When BBSQW is logic 0, the INT/SQW pin goes high impedance when V CC falls below the power-fail trip point. This bit is disabled (logic 0) when power is first applied. Bit 5: Convert Temperature (CONV). Setting this bit to 1 forces the temperature sensor to convert the temper- ature into digital code and execute the TCXO algorithm to update the capacitance array to the oscillator. This can only happen when a conversion is not already in progress. The user should check the status bit BSY before forcing the controller to start a new TCXO exe- cution. A user-initiated temperature conversion does not affect the internal 64-second (default interval) update cycle. A user-initiated temperature conversion does not affect the BSY bit for approximately 2ms. The CONV bit remains at a 1 from the time it is written until the conver- sion is finished, at which time both CONV and BSY go to 0. The CONV bit should be used when monitoring the status of a user-initiated conversion. Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. The following table shows the square-wave frequencies that can be select- ed with the RS bits. These bits are both set to logic 1 (8.192kHz) when power is first applied. Bit 2: Interrupt Control (INTCN). This bit controls the INT/SQW signal. When the INTCN bit is set to logic 0, a square wave is output on the INT/SQW pin. When the INTCN bit is set to logic 1, a match between the time- keeping registers and either of the alarm registers acti- vates the INT/SQW (if the alarm is also enabled). The corresponding alarm flag is always set regardless of the state of the INTCN bit. The INTCN bit is set to logic 1 when power is first applied. Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied. Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit does not initiate the INT/SQW sig- nal. The A1IE bit is disabled (logic 0) when power is first applied. DS3232 Extremely Accurate I2C RTC with Integrated Crystal and SRAM BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NAME: EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE POR*: 00011100 RS2 RS1 SQUARE-WAVE OUTPUT FREQUENCY 0 0 1Hz 0 1 1.024kHz 1 0 4.096kHz 1 1 8.192kHz SQUARE-WAVE OUTPUT FREQUENCY Control Register (0Eh) *POR is defined as the first application of power to the device, either VBAT or VCC.

Control/Status Register (0Fh) Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period and may be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltages present on both V CC and V BAT are insufficient to support oscillation. 3) The EOSC bit is turned off in battery-backed mode. 4) External influences on the crystal (i.e., noise, leak- age, etc.). This bit remains at logic 1 until written to logic 0. Bit 6: Battery-Backed 32kHz Output (BB32kHz). This bit enables the 32kHz output when powered from V BAT (provided EN32kHz is enabled). If BB32kHz = 0, the 32kHz output is low when the part is powered by V BAT. Bits 5 and 4: Conversion Rate (CRATE1 and CRATE0). These two bits control the sample rate of the TCXO. The sample rate determines how often the tem- perature sensor makes a conversion and applies com- pensation to the oscillator. Decreasing the sample rate decreases the overall power consumption by decreas- ing the frequency at which the temperature sensor operates. However, significant temperature changes that occur between samples may not be completely compensated for, which reduce overall accuracy. When a new conversion rate is written to the register, it may take up to the new conversion rate time before the conversions occur at the new rate. Bit 3: Enable 32kHz Output (EN32kHz). This bit indi- cates the status of the 32kHz pin. When set to logic 1, the 32kHz pin is enabled and outputs a 32.768kHz square-wave signal. When set to logic 0, the 32kHz pin goes low. The initial power-up state of this bit is logic 1, and a 32.768kHz square-wave signal appears at the 32kHz pin after a power source is applied to the DS3232 (if the oscillator is running). Bit 2: Busy (BSY). This bit indicates the device is busy executing TCXO functions. It goes to logic 1 when the conversion signal to the temperature sensor is asserted and then is cleared when the conversion is complete. Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 regis- ters. If the A2IE bit is logic 1 and the INTCN bit is set to logic 1, the INT /SQW pin is also asserted. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 regis- ters. If the A1IE bit is logic 1 and the INTCN bit is set to logic 1, the INT /SQW pin is also asserted. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Extremely Accurate I2C RTC with Integrated Crystal and SRAM BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NAME: OSF BB32kHz CRATE1 CRATE0 EN32kHz BSY A2F A1F POR*: 11001000 Control/Status Register (0Fh) *POR is defined as the first application of power to the device, either VBAT or VCC. CRATE1 CRATE0 SAMPLE RATE (seconds) 00 6 4 0 1 128 1 0 256 1 1 512

The aging offset register takes a user-provided value to add to or subtract from the oscillator capacitor array. The data is encoded in two’s complement, with bit 7 representing the sign bit. One LSB represents the smallest capacitor to be switched in or out of the capacitance array at the crystal pins. The aging offset register capacitance value is added or subtracted from the capacitance value that the device calculates for each temperature compensation. The offset register is added to the capacitance array during a normal tem- perature conversion, if the temperature changes from the previous conversion, or during a manual user con- version (setting the CONV bit). To see the effects of the aging register on the 32kHz output frequency immedi- ately, a manual conversion should be started after each aging offset register change. Positive aging values add capacitance to the array, slowing the oscillator frequency. Negative values remove capacitance from the array, increasing the oscillator frequency. The change in ppm per LSB is different at different temperatures. The frequency vs. temperature curve is shifted by the values used in this register. At +25°C, one LSB typically provides about 0.1ppm change in frequency. Use of the aging register is not needed to achieve the accuracy as defined in the EC tables, but could be used to help compensate for aging at a given tempera- ture. See the Typical Operating Characteristics section for a graph showing the effect of the register on accu- racy over temperature. Temperature Registers (11h–12h) Temperature is represented as a 10-bit code with a res- olution of 0.25°C and is accessible at location 11h and 12h. The temperature is encoded in two’s complement format, with bit 7 in the MSB representing the sign bit. The upper 8 bits, the integer portion, are at location 11h and the lower 2 bits, the fractional portion, are in the upper nibble at location 12h. For example, 00011001 01b = +25.25°C. Upon power reset, the reg- isters are set to a default temperature of 0°C and the controller starts a temperature conversion. The temperature is read on initial application of V CC or I2C access on V BAT and once every 64 seconds after- wards. The temperature registers are updated after each user-initiated conversion and on every 64-second conversion. The temperature registers are read-only. DS3232 Extremely Accurate I2C RTC with Integrated Crystal and SRAM BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NAME: SIGN DATA DATA DATA DATA DATA DATA DATA POR*: 00000000 Aging Offset (10h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NAME: SIGN DATA DATA DATA DATA DATA DATA DATA POR*: 00000000 Temperature Register (Upper Byte) (11h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NAME: DATA DATA 0 0 0 0 0 0 POR*: 00000000 Temperature Register (Lower Byte) (12h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NAME: D7 D6 D5 D4 D3 D2 D1 D0 POR*: XXXXXXXX SRAM (14h–FFh) *POR is defined as the first application of power to the device, either VBAT or VCC.

are defined. The DS3232 works in both modes.

• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low, while the clock line is high, defines a START condition. Stop data transfer: A change in the state of the data line from low to high, while the clock line is high, defines a STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and the STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associ- ated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. Figures 3 and 4 detail how data transfer is accom- plished on the I 2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is Extremely Accurate I2C RTC with Integrated Crystal and SRAM SDA SCL IDLE 1–7 8 9 1–7 8 9 1–7 8 9 START CONDITION STOP CONDITION REPEATED START SLAVE ADDRESS R/W ACK ACK DATA ACK/ NACK DATA MSB FIRST MSB LSB MSB LSB REPEATED IF MORE BYTES ARE TRANSFERRED

Figure 2. I2C Data Transfer Overview

The DS3232 can operate in the following two modes: Slave receiver mode (DS3232 write mode): Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recog- nized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS3232 address, which is 1101000, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte, the DS3232 outputs an acknowledge on SDA. After the DS3232 acknowl- edges the slave address + write bit, the master transmits a word address to the DS3232. This sets the register pointer on the DS3232, with the DS3232 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the DS3232 acknowledging each byte received. The register pointer increments after each data byte is trans- ferred. The master generates a STOP condition to terminate the data write. Slave transmitter mode (DS3232 read mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS3232 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit DS3232 address, which is 1101000, fol- lowed by the direction bit (R/ W), which is 1 for a read. After receiving and decoding the slave address byte, the DS3232 outputs an acknowledge on SDA. The DS3232 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register point- er. The DS3232 must receive a not acknowledge to end a read. Handling, PC Board Layout, and Assembly The DS3232 package contains a quartz tuning-fork crystal. Pick-and-place equipment can be used, but precautions should be taken to ensure that excessive shocks are avoided. Exposure to reflow is limited to 2 times maximum. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connect) pins must be connect- ed to ground. Chip Information TRANSISTOR COUNT: 48,000 SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS Thermal Information Theta-JA: +55.1°C/W Theta-JC: +24°C/W Extremely Accurate I2C RTC with Integrated Crystal and SRAM PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

20 SO — 21-0042

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.

Extremely Accurate I2C RTC with Integrated Crystal and SRAM Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. Marichu Quijano

Revision History

0 9/05 Initial release. — 1 11/05 Changed RoHS note wording for the Ordering Information table. 1 Corrected the Ordering Information part numbers. 1 Changed the reference of Figure 4 to Table 1 in the AC Electrical Characteristics table. 4 Corrected the supply current units from μA to nA and added BSY = 0 to the Supply Current vs. Supply Voltage graph in the Typical Operating Characteristic s. 2 3/06 Added a sentence about limiting exposure to reflow is 2 times maximum to the Handling, PC Board Layout, and Assembly section. 17 Added the Duty Cycle (Revision A3 Devices) parameter to the Electrical Characteristics table; added CRATE0 = CRATE1 = 0 conditions to I BAT. 3 Changed the RST pin description to indicate that the pin immediately goes high if power is applied and the oscillator is disabled. 9 Added a paragraph to the Pushbutton Reset Function section about how the RST output operation does not affect the device’s internal operation. 10 3 10/07 Corrected the date register range for 04h from 00–31 to 01–31 in Figure 1. 11 Updated the Typical Operating Circuit . 1 Removed the V PU parameter from the Recommended DC Operating Conditions table and added verbiage about the pullup to the Pin Description table for INT/SQW, SDA, and SCL. 2, 9 In the Electrical Characteristics table, changed the symbols for Timekeeping Battery Current, Temperature Conversion Current, and Data-Retention Current from IBAT, ITC, and IBATTC to IBATT, IBATTC, and IBATTDR, respectively. Added the Delta Time and Frequency vs. Temperature graph in the Typical Operating Characteristics section. 7 Updated the Block Diagram . 8 Added the VBAT Operation section and improved some sections of text for the Aging Offset Register and Temperature Registers (11h–12h) sections. 10, 15 4 10/08 Updated the I2C timing diagrams (Figures 3, 4, and 5). 17