DS3231M_V01 MAXIM | Alldatasheet

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+Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. Typical Operating Circuit General Description The DS3231M is a low-cost, extremely accurate, I2C real- time clock (RTC). The device incorporates a battery input and maintains accurate timekeeping when main power to the device is interrupted. The integration of the microelec- tromechanical systems (MEMS) resonator enhances the long-term accuracy of the device and reduces the piece- part count in a manufacturing line. The DS3231M is avail- able in the same footprint as the popular DS3231 RTC. The RTC maintains seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. Two programmable time-of- day alarms and a 1Hz output are provided. Address and data are transferred serially through an I 2C bidirectional bus. A precision temperature-compensated voltage refer- ence and comparator circuit monitors the status of V CC to detect power failures, to provide a reset output, and to automatically switch to the backup supply when neces - sary. Additionally, the RST pin is monitored as a pushbutton input for generating a microprocessor reset. See the Block Diagram for more details.

Applications

Ordering Information

  • Highly Accurate RTC With Integrated MEMS Resonator Completely Manages All Timekeeping Functions
  • Complete Clock Calendar Functionality Including Seconds, Minutes, Hours, Day, Date, Month, and Year, with Leap-Year Compensation Up to Year 2100
  • Timekeeping Accuracy ±5ppm (±0.432 Second/Day) from -45°C to +85°C
  • Footprint and Functionally Compatible to DS3231
  • Two Time-of-Day Alarms
  • 1Hz and 32.768kHz Outputs
  • Reset Output and Pushbutton Input with Debounce
  • Digital Temp Sensor with ±3°C Accuracy
  • +2.3V to +5.5V Supply Voltage
  • Simple Serial Interface Connects to Most Microcontrollers
  • Fast (400kHz) I2C Interface
  • Battery-Backup Input for Continuous Timekeeping
  • Low Power Operation Extends Battery-Backup Run Time
  • Operating Temperature Range: -40°C to +85°C
  • 8-Pin or 16-Pin SO Packages
  • Underwriters Laboratories® (UL) Recognized 19-5312; Rev 7; 3/15 Underwriters Laboratories is a registered certification mark of Underwriters Laboratories Inc. DS3231M SCL SDA 32KHZ VBAT INT/SQW RST +3.3V+3.3V CPU I/O PORT INTERRUPTS PART TEMP RANGE PIN-PACKAGE DS3231MZ+ -45NC to +85NC 8 SO DS3231MZ/V+ -45NC to +85NC 8 SO DS3231M+ -45NC to +85NC 16 SO DS3231M ±5ppm, I2C Real-Time Clock

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (TA = -45NC to +85NC, unless otherwise noted.) (Note 2) Electrical Characteristics—Frequency And Timekeeping (VCC or V BAT = +3.3V, T A = -45 NC to +85 NC, unless otherwise noted. Typical values are at V CC = +3.3V, V BAT = +3.0V, and TA = +25NC, unless otherwise noted.) +25NC, unless otherwise noted.) Absolute Maximum Ratings 8 SO 16 SO Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Package Thermal Characteristics (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Logic 1 VIH 0.7 x VCC VCC + 0.3 V Logic 0 VIL -0.3 0.3 x VCC V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1Hz Frequency Tolerance Df/fOUT Measured over R 10s interval Q5 ppm 1Hz Frequency Stability vs. VCC Voltage Df/V Q1 ppm/V Timekeeping Accuracy tKA Q0.432 Seconds/ Day 32kHz Frequency Tolerance Df/fOUT Q2.5 % PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Active Supply Current (I2C Active: Includes Temperature Conversion Current) ICCA VCC = +3.63V 200 µA VCC = VCCMAX 300 Standby Supply Current (I2C Inactive: Includes Temperature Conversion Current) ICCS VCC = +3.63V 130 µA VCC = VCCMAX 200 Temperature Conversion Current (I2C Inactive) ICCSCONV VCC = +3.63V 575 µAVCC = VCCMAX 650 DS3231M ±5ppm, I2C Real-Time Clock www.maximintegrated.com Maxim Integrated │ 2

(TA = -45NC to +85NC, unless otherwise noted.) (Figure 2) +25NC, unless otherwise noted.) (VCC = 0V, VBAT = +2.3V to +5.5V, TA = -45NC to +85NC, unless otherwise noted. Typical values are at VCC = 0V, VBAT = +3.0V, and TA = +25NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power-Fail Voltage VPF 2.45 2.575 2.70 V Logic 0 Output (32KHZ, INT/SQW, SDA) VOL IOL = 3mA 0.4 V Logic 0 Output (RST) VOL IOL = 1mA 0.4 V Output Leakage (32KHZ, INT/SQW, SDA) ILO -0.1 +0.1 µA Input Leakage (SCL) ILI -0.1 +0.1 µA RST I/O Leakage IOL -200 +10 µA VBAT Leakage IBATLKG 25 100 nA Temperature Accuracy TEMPACC VCC or VBAT = +3.3V Q3 NC Temperature Conversion Time tCONV 10 ms Pushbutton Debounce PBDB 250 ms Reset Active Time tRST 250 ms Oscillator Stop Flag (OSF) Delay tOSF (Note 3) 125 200 ms PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Active Battery Current (I2C Active) (Note 4) IBATA VBAT = +3.63V 70 µAVBAT = VBATMAX 150 Timekeeping Battery Current (I2C Inactive) (Note 4) IBATT VBAT = +3.63V, EN32KHZ = 0 2 3.0 µAVBAT = VBATMAX, EN32KHZ = 0 2 3.5 Temperature Conversion Current (I2C Inactive) IBATTC VBAT = +3.63V 575 µAVBAT = VBATMAX 650 Data Retention Current (Oscillator Stopped and I2C Inactive) IBATDR TA = +25NC 100 nA PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC Fall Time, VPFMAX to VPFMIN tVCCF 300 Fs VCC Rise Time, VPFMIN to VPFMAX tVCCR 0 Fs Recovery at Power-Up tREC (Note 5) 250 300 ms DS3231M ±5ppm, I2C Real-Time Clock www.maximintegrated.com Maxim Integrated │ 3

TA = +25NC, unless otherwise noted.) (Note 6, Figure 1) Note 2: All voltages are referenced to ground. Note 3: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set. Note 4: Includes the temperature conversion current (averaged). Note 5: This delay applies only if the oscillator is enabled. If the EOSC bit is 1, tREC is bypassed and RST immediately goes high. The state of RST does not affect the I2C interface or RTC functions. Note 6: Interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with standard mode I2C timing. Note 7: CB: Total capacitance of one bus line in picofarads. Note 8: Guaranteed by design; not 100% production tested. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency fSCL 0 400 kHz Bus Free Time Between STOP and START Conditions tBUF 1.3 Fs Hold Time (Repeated) START Condition tHD:STA 0.6 Fs Low Period of SCL tLOW 1.3 Fs High Period of SCL tHIGH 0.6 Fs Data Hold Time tHD:DAT 0 0.9 Fs Data Set-Up Time tSU:DAT 100 ns START Set-Up Time tSU:STA 0.6 Fs SDA and SCL Rise Time tR (Note 7) 20 + 0.1CB 300 ns SDA and SCL Fall Time tF (Note 7) 20 + 0.1CB 300 ns STOP Set-Up Time tSU:STO 0.6 Fs SDA, SCL Input Capacitance CBIN (Note 8) 10 pF DS3231M ±5ppm, I2C Real-Time Clock www.maximintegrated.com Maxim Integrated │ 4

vs. TEMPERATURE DS3231M toc06 TEMPERATURE (°C) FREQUENCY ERROR (ppm) 500 -10 -50 100 LIMITS VCC = 3.3V RST OUTPUT VOLTAGE vs. POWER SUPPLY VOLTAGE DS3231M toc05 SUPPLY VOLTAGE (V) OUTPUT VOLTAGE (V) VBAT = 3.0V, TA = +25°C TRACKS WITH VCC RST OUTPUT VOLTAGE vs. OUTPUT CURRENT DS3231M toc04 OUTPUT CURRENT (mA) OUTPUT VOLTAGE (V) 4321 0.1 0.2 0.3 0.4 0.5 VCC = 2.45V, VBAT = 3.0V, TA = +25°C INT/SQW OUTPUT VOLTAGE vs. OUTPUT CURRENT DS3231M toc03 OUTPUT CURRENT (mA) OUTPUT VOLTAGE (V) 8642 0.1 0.2 0.3 0.4 0.5 01 0 VCC = 2.3V, VBAT = 0V, TA = +25°C BATTERY-SUPPLY CURRENT vs. BATTERY-SUPPLY VOLTAGE DS3231M toc02 SUPPLY VOLTAGE (V) SUPPLY CURRENT (µA) 543 1.5 2.0 2.5 3.0 3.5 4.0 1.0 VCC = 0V, EN32KHZ = 1, BBSQW = 0 +85°C +25°C -40°C POWER-SUPPLY CURRENT vs. POWER-SUPPLY VOLTAGE DS3231M toc01 SUPPLY VOLTAGE (V) SUPPLY CURRENT (µA) 543 100 110 120 130 140 150 VBAT = 2.3V, EN32KHZ = 1, IOUT = 0mA INCREASE BELOW VPF DUE TO INTERNAL PULLUP RESISTOR ON RST +85°C +25°C -40°C POWER-SUPPLY CURRENT vs. SCL FREQUENCY DS3231M toc07 SCL FREQUENCY (kHz) SUPPLY CURRENT (µA) 300200100 100 110 120 130 140 150 160 170 180 190 200 0 400 TA = +25°C +5.5V +2.7V +3.5V DS3231M ±5ppm, I2C Real-Time Clock Maxim Integrated │ 6 www.maximintegrated.com Typical Operating Characteristics (TA = +25°C, unless otherwise noted.)

N.C. N.C. N.C. N.C. TOP VIEW SO VCC INT/SQW N.C. RST N.C. N.C. N.C. DS3231M DS3231M VBAT GNDRST SCL SDAVCC INT/SQW 32KHZ SO TOP VIEW PIN NAME FUNCTION8 SO 16 SO 1 1 32KHZ 32.768kHz Output (50% Duty Cycle). This open-drain pin requires an external pullup resistor. When enabled with the EN32KHZ bit in the Status register (0Fh), this output operates on either power supply. This pin can be left open circuit if not used. 2 2 VCC DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1 FF to 1.0FF capacitor. Connect to ground if not used. 3 3 INT/ SQW Active-Low Interrupt or 1Hz Square-Wave Output. This open-drain pin requires an external pullup resistor connected to a supply at 5.5V or less. It can be left open if not used. This multifunction pin is determined by the state of the INTCN bit in the Control register (0Eh). When INTCN is set to logic 0, this pin outputs a 1Hz square wave. When INTCN is set to logic 1, a match between the timekeeping registers and either of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms disabled. 4 4 RST Active-Low Reset. This pin is an open-drain input/output. It indicates the status of V CC relative to the VPF specification. As VCC falls below VPF, the RST pin is driven low. When V CC exceeds VPF, for tRST, the RST pin is pulled high by the internal pullup resistor. The active-low, open-drain output is combined with a debounced pushbutton input function. This pin can be activated by a pushbutton reset request. It has an internal 50k I (RPU) nominal value pullup resistor to V CC. No external pullup resistors should be connected. If the oscillator is disabled, t REC is bypassed and RST immediately goes high. — 5–12 N.C. No Connection. These pins must be connected to ground. 5 13 GND Ground 6 14 VBAT Backup Power-Supply Input. When using the device with the VBAT input as the primary power source, this pin should be decoupled using a 0.1FF to 1.0FF low-leakage capacitor. When using the device with the VBAT input as the backup power source, the capacitor is not required. If VBAT is not used, connect to ground. The device is UL recognized to ensure against reverse charging when used with a primary lithium battery. Go to www.maximintegrated.com/qa/info/ul for more information. DS3231M ±5ppm, I2C Real-Time Clock www.maximintegrated.com Maxim Integrated │ 7

The DS3231M is a serial real-time clock (RTC) driven by an internal, temperature-compensated, microelectrome - chanical systems (MEMS) resonator. The oscillator pro - vides a stable and accurate reference clock and main - tains the RTC to within Q0.432 seconds-per-day accu - racy from -45NC to +85NC. The RTC is a low-power clock/ calendar with two programmable time-of-day alarms. INT/ SQW provides either an interrupt signal due to alarm conditions or a 1Hz square wave. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is auto- matically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indi- cator. The internal registers are accessible though an I2C bus interface. A temperature-compensated voltage refer- ence and comparator circuit monitors the level of V CC to detect power failures and to automatically switch to the backup supply when necessary. The RST pin provides an external pushbutton function and acts as an indicator of a power-fail event. Operation The Block Diagram shows the device’s main elements. Each of the major blocks is described separately in the following sections. Block Diagram Pin Description (continued) DS3231M N N TIME-BASE RESONATOR TEMP SENSOR INTERRUPT OR 1Hz SELECT DIVIDER INT/SQW 1Hz DIGITAL ADJUSTMENT FACTORY TRIM N 32KHZ SDA GND SCL VBAT VCC RST RPU CLOCK/CALENDAR WITH ALARM CONTROL AND STATUS REGISTERS I2C INTERFACE POWER CONTROL PIN NAME FUNCTION8 SO 16 SO 7 15 SDA Serial-Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain pin requires an external pullup resistor. The pullup voltage can be up to 5.5V, regardless of the voltage on VCC. 8 16 SCL Serial-Clock Input. This pin is the clock input for the I 2C serial interface and is used to synchronize data movement on the serial interface. The pullup voltage can be up to 5.5V, regardless of the voltage on VCC. DS3231M ±5ppm, I2C Real-Time Clock www.maximintegrated.com Maxim Integrated │ 8

by VCC. If VCC is less than VPF and is less than VBAT, the device is powered by VBAT (see Table 1). When V CC < V PF, the RST output is asserted (active low). When VCC is the presently selected power source, temperature conversions are executed once per second. When VBAT is the presently selected power source, tem- perature conversions are executed once every 10s. To preserve the battery, the first time V BAT is applied to the device the oscillator does not start up until V CC exceeds V PF or until a valid I 2C address is written to the device. Typical oscillator startup time is less than 1s. Approximately 2s after V CC is applied, or a valid I2C address is written, the device makes a temperature measurement and applies the calculated correction to the oscillator. Once the oscillator is running, it continues to run as long as a valid power source is available (V CC or VBAT), and the device continues to measure the tem - perature and correct the oscillator frequency. On the first application of V CC power, or (if V BAT powered) when a valid I2C address is written to the device, the time and date registers are reset to 01/01/00 01 00:00:00 (DD/MM/ YY DOW HH:MM:SS). Initial VBAT Attachment During the initial battery attachment to the DS3231M, it is important to eliminate the effects of contact bounce. Contact bounce occurs when battery contact rapidly and repeatedly alternates between connected and dis - connected during the battery attachment before finally settling to the connected state. This bounce can cause a momentary power interruption to the DS3231M that can result in memory recall corruption in the device. There are two recommended ways to eliminate the effects of contact bounce on the device. The preferred way uses power sequencing by applying VCC to the part before performing the battery attachment. An alternate method to eliminate contact bounce is to filter the signal using a small capacitor between V BAT and ground. For this method, capacitor values between 0.1nf and 1nf are recommended for the supply filtering. VBAT Operation There are several modes of operation that affect the amount of V BAT current that is drawn. While the device is powered by V BAT and the serial interface is active, the active battery current I BATA is drawn. When the serial interface is inactive, the timekeeping current I BATT (which includes the averaged temperature-conversion current I BATTC) is used. The temperature-conversion current I BATTC is specified since the system must be able to support the periodic higher current pulse and still maintain a valid voltage level. The data-retention current IBATDR is the current drawn by the device when the oscillator is stopped ( EOSC = 1). This mode can be used to minimize battery requirements for periods when maintaining time and date information is not necessary, e.g., while the end system is waiting to be shipped to a customer. Pushbutton Reset Function The device provides for a pushbutton switch to be con - nected to the RST input/output pin. When the device is not in a reset cycle, it continuously monitors RST for a low-going edge. If an edge transition is detected, the device debounces the switch by pulling RST low. After the internal timer has expired (PB DB), the device con - tinues to monitor the RST line. If the line is still low, the device continuously monitors the line looking for a rising edge. Upon detecting release, the device forces RST low and holds it low for t RST. RST is also used to indi - cate a power-fail condition. When VCC is lower than VPF, an internal power-fail signal is generated, which forces RST low. When V CC returns to a level above V PF, RST is held low for approximately 250ms (t REC) to allow the power supply to stabilize. If the oscillator is not running when VCC is applied, t REC is bypassed and RST imme- diately goes high. Assertion of the RST output, whether by pushbutton or power-fail detection, does not affect the device’s internal operation. RST output operation and pushbutton monitoring are only available if V CC power is available. Real-Time Clock (RTC) With the 1Hz source from the temperature-compensated oscillator, the RTC provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or the 12-hour format with an AM/PM indicator. The clock pro - vides two programmable time-of-day alarms. INT/SQW can be enabled to generate either an interrupt due to an alarm condition or a 1Hz square wave. This selection is controlled by the INTCN bit in the Control register. I2C Interface The I2C interface is accessible whenever either V CC or VBAT is at a valid level. If a microcontroller connected to the device resets because of a loss of V CC or other event, it is possible that the microcontroller and device’s I2C communications could become unsynchronized, DS3231M ±5ppm, I2C Real-Time Clock www.maximintegrated.com Maxim Integrated │ 10

SCL is high, generating a START condition. Table 2. Timekeeping Registers Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.

24-hour mode, bit 5 is the 20-hour bit (20–23 hours). and date registers must be written within 1s. can be set by writing to registers 0Bh–0Dh. See Table 2. values stored in the time-of-day/date alarm registers. result of a match with day of the week. Table 3. Alarm Mask Bits

Control Register (0Eh) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EOSC BBSQW CONV NA NA INTCN A2IE A1IE 0 0 0 1 1 1 0 0 BIT 7 EOSC: Enable oscillator. When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is stopped when the device switches to V BAT. This bit is clear (logic 0) when power is first applied. When the device is powered by VCC, the oscillator is always on regardless of the status of the EOSC bit. When the oscil- lator is disabled, all register data is static. BIT 6 BBSQW: Battery-backed square-wave enable. When set to logic 1 with INTCN = 0 and VCC < VPF, this bit enables the 1Hz square wave. When BBSQW is logic 0, INT/SQW goes high impedance when VCC falls below VPF. This bit is disabled (logic 0) when power is first applied. BIT 5 CONV: Convert temperature. Setting this bit to 1 forces the temperature sensor to convert the temperature into digital code and execute the temperature compensate algorithm to update the oscillator’s accuracy. The device cannot be forced to execute the temperature-compensate algorithm faster than once per second. A user-initiated temperature conversion does not affect the internal update cycle. The CONV bit remains at a 1 from the time it is written until the temperature conversion is completed, at which time both CONV and BSY go to 0. The CONV bit should be used when monitoring the status of a user-initiated conversion. See Figure 7 for more details. BITS 4:3 NA: Not applicable. These bits have no affect on the device and can be set to either 0 or 1. BIT 2 INTCN: Interrupt control. This bit controls the INT/SQW output signal. When the INTCN bit is set to logic 0, a 1Hz square wave is output on INT/SQW. When the INTCN bit is set to logic 1, a match between the timekeep - ing registers and either of the alarm registers activates the INT/SQW output (if the alarm is also enabled). The corresponding alarm flag is always set regardless of the state of the INTCN bit. The INTCN bit is set to a logic 1 when power is first applied. BIT 1 A2IE: Alarm 2 interrupt enable. When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status reg - ister to assert INT/SQW (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied. BIT 0 A1IE: Alarm 1 interrupt enable. When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status reg - ister to assert INT/SQW (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied . DS3231M ±5ppm, I2C Real-Time Clock www.maximintegrated.com Maxim Integrated │ 13

Figure 7. CONV Control Bit and BSY Status Bit Operation

10 SECONDS

Status Register (0Fh) Aging Offset Register (10h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OSF 0 0 0 EN32KHZ BSY A2F A1F 1 0 0 0 1 X X X BIT 7 OSF: Oscillator stop flag. A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period and could be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time that the oscillator stops. This bit remains at logic 1 until written to logic 0. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltages present on both V CC and VBAT are insufficient to support the oscillator. 3) The EOSC bit is turned off in battery-backed mode. 4) External influences on the oscillator (i.e., noise, leakage, etc.). BITS 6:4 Unused (0). These bits have no meaning and are fixed at 0 when read. BIT 3 EN32KHZ: Enabled 32.768kHz output. This bit enables and disables the 32KHZ output. When set to a logic 0, the 32KHZ output is high impedance. On initial power-up, this bit is set to a logic 1 and the 32KHZ output is enabled and produces a 32.768kHz square wave if the oscillator is enabled. BIT 2 BSY: Busy. This bit indicates the device is busy executing temperature conversion function. It goes to logic 1 when the conversion signal to the temperature sensor is asserted, and then it is cleared when the device has completed the temperature conversion. See the Block Diagram for more details. BIT 1 A2F: Alarm 2 flag. A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. If the A2IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. BIT 0 A1F: Alarm 1 flag. A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the A1IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SIGN DATA DATA DATA DATA DATA DATA DATA 0 0 0 0 0 0 0 0 The Aging Offset register takes a user-provided value to add to or subtract from the factory-trimmed value that adjusts the accuracy of the time base. Use of the Aging Offset register is not needed to achieve the accuracy as defined in the Electrical Characteristics tables. The Aging Offset code is encoded in two’s complement, with bit 7 representing the SIGN bit and a valid range of ±127. One LSB typically represents a 0.12ppm change in frequency. The change in ppm per LSB is the same over the operating tempera - ture range. Positive offsets slow the time base and negative offsets quicken the time base. DS3231M ±5ppm, I2C Real-Time Clock www.maximintegrated.com Maxim Integrated │ 15

Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it immediately initiates a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identi- cally to a normal START condition. See Figure 1 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (see Figure 1). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (see Figure 1) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the pre- vious SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledge (ACK and NACK): An acknowledge (ACK) or not acknowledge (NACK) is always the ninth bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by trans - mitting a 0 during the ninth bit. A device performs a NACK by transmitting a 1 during the ninth bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of informa - tion transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgment is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I 2C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/ W bit in the least significant bit. The device’s slave address is D0h and cannot be modi - fied by the user. When the R/ W bit is 0 (such as in D0h), the master is indicating it writes data to the slave. If R/ W = 1 (D1h in this case), the master is indicating it wants to read from the slave. If an incor - rect slave address is written, the device assumes the master is communicating with another I2C device and ignore the communication until the next START condi- tion is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. I2C Communication See Figure 9 for an I2C communication example. Writing a Single Byte to a Slave: The master must generate a START condition, write the slave address byte (R/ W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave’s acknowl- edgment during all byte write operations. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave, the master generates a START con - dition, writes the slave address byte (R/W = 0), writes the starting memory address, writes multiple data bytes, and generates a STOP condition. Reading a Single Byte from a Slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. However, since requir - ing the master to keep track of the memory address counter is impractical, use the method for manipulat - ing the address counter for reads. DS3231M ±5ppm, I2C Real-Time Clock www.maximintegrated.com Maxim Integrated │ 17

specify the starting memory location. read another byte before terminating the transaction. required, the VBAT decoupling capacitor can be omitted. pullup resistors should not be added. pullup resistor to realize a logic-high level. Figure 9. I2C Transactions

Package Information

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

16 SO W16MK+1 21-0042 90-0107

8 SO S8MK+1 21-0041 90-0096

DS3231M ±5ppm, I2C Real-Time Clock www.maximintegrated.com Maxim Integrated │ 19

Revision History

0 6/10 Initial release — 1 5/11 Updated the Features section; moved the temperature accuracy limit from ±3°C (max) to ±3°C (typ) in the DC Electrical Characteristics—General table; added the Power- Supply Current vs. SCL Frequency graph to the Typical Operating Characteristics section; changed the initial date information to international format in the Power-Supply Configuration section 1, 3, 6, 10 2 10/11 Removed future status from the 8-pin SO package in the Ordering Information table; updated the Typical Operating Circuit; added Note 7 to the C BIN parameter in the AC Electrical Characteristics—I2C Interface table; clarified the 10h register range in Table 2 and the Aging Offset Register (10h) section; corrected the package codes for both SO variants in the Package Information table 1, 4, 11, 15, 3 12/11 Added the automotive qualified 8-pin SO package to the Ordering Information table; changed the lead temperature from +260°C to +300°C in the Absolute Maximum Ratings section 1, 2 4 9/12 Changed the operating temperature range from -40°C to +85°C to -45°C to +85°C 1-4, 8 5 7/13 Added junction temperature and package thermal data 2 6 8/14 Added Initial VBAT Attachment section 10 7 3/15 Updated Benefits and Features section. 1 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. DS3231M ±5ppm, I2C Real-Time Clock © 2015 Maxim Integrated Products, Inc. │ 20 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.