Driver IC

DS320PR822NJXT.B

Texas Instruments

DS320PR822 Linear Redriver for PCIe 5.0, CXL 1.1 With Four 2x2 Crosspoint Mux SEPTEMBER 2022

Manufacturer: Texas Instruments

Document: 38 Pages / 1Mb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse D parts

Online Datasheet

Read DS320PR822NJXT.B online.

DS320PR822 TI | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 38

Technical content

DS320PR822 Linear Redriver for PCIe 5.0, CXL 1.1 With Four 2x2 Crosspoint Mux

1 Features

Linear redriver supporting PCIe 5.0, CXL 2.0, UPI 2.0 up to 32 Gbps
Supports most ac coupled interfaces including DP, SAS, SATA, XFI
Provides four 2x2 Crosspoint mux function
CTLE boosts up to 22 dB at 16 GHz
Ultra-low latency of 100 ps
Low additive random jitter of 75 fs for PRBS data
Excellent return loss of −10 dB at 16 GHz
Single 3.3 V supply
Internal voltage regulator provides immunity to supply noise
Low active power of 160 mW per channel
No heat sink required
Pin-strap, SMBus or EEPROM programming
Automatic receiver detection for PCIe use cases
Protocol agnostic linear redriver allows seamless support for PCIe link training
Support for x2, x4, x8, x16, x24 bus width with one or multiple DS320PR822
Temperature range of –40 °C to 85 °C
5.5 mm × 10 mm, 64 pin WQFN package

2 Applications

Rack server, microserver, and tower server
High performance computing
Hardware accelerator
Network attached storage
Storage area network (SAN) and host bus adapter (HBA) card
Network interface card (NIC)
Desktop PC or motherboard

3 Description

The DS320PR 822 is a low-power high-performance linear repeater or redriver designed to support PCIe 5.0, CXL 2.0, UPI 2.0, and other interfaces up to 32 Gbps. The DS320PR822 provides four 2x2 cross- point mux functionality. The DS320PR 822 receivers deploy continuous time linear equalizers (CTLE) to provide a programmable high-frequency boost. The equalizer can open an input eye that is completely closed due to inter- symbol interference (ISI) induced by an interconnect medium, such as PCB traces. The CTLE receiver is followed by a linear output driver. The linear data- paths of DS320PR822 preserve transmit preset signal characteristics. The linear redriver becomes part of the passive channel that as a whole get link trained for best transmit and receive equalization settings. This transparency in the link training protocol results in best electrical link and lowest possible latency. Low channel-channel cross-talk, low additive jitter and excellent return loss makes the device almost a passive element in the link, but with its useful equalization. The data-path of the device uses an internally regulated power rail that provides high immunity to any supply noise on the board. The device also has low AC and DC gain variation providing consistent equalization in high volume platform deployment. Package Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DS320PR822 WQFN (NJX, 64) 5.50 mm × 10.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. CPU-2 CPU-1 TX RX TX RX RX TX RX TX x16 x16 x16 x16 x16x16 x16x16 DS320PR822 Quad 2x2 x-point DS320PR822 Quad 2x2 x-point Connector-1 PCIe Card-1 (x16) Connector-2 PCIe Card-2 (x16) Typical Application DS320PR822 SNLS714 – SEPTEMBER 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11.1 Receiving Notification of Documentation Updates.. 30

12 Mechanical, Packaging, and Orderable

4 Revision History

September 2022 * Initial Release DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DS320PR822

5 Pin Configuration and Functions

EQ0_1 GAIN1 ALL_DONE_N EQ1_0/ADDR1 EQ0_0/ADDR0 SEL0 6464 6363 6262 6161 6060 5959 5858 5757 5656 RX0P RX0N GND VCC GND TX0P TX0N VCC GND RSVD2 RSVD3 RX1P RX1N RX2P RX2N RX3P RX3N RX4P RX4N RX5P RX5N RX6P RX6N RX7P RX7N GND GND VCC VCC RSVD5 RSVD4 GND TX1P TX1N TX2P TX2N TX3P TX3N TX4P TX4N TX5P TX5N TX6P TX6N TX7P TX7N EQ1_1 SEL1 READ_EN_N RX_DET/SCL MODE GAIN0/SDAPD0 PD1 GND GND GND GND EP=GND Figure 5-1. NJX Package, 64-Pin WQFN (Top View) www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DS320PR822

Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. ALL_DONE_N 31 O, 3.3 V open drain In SMBus/I2C Primary mode: Indicates the completion of a valid EEPROM register load operation. External pullup resistor such as 4.7 kΩ required for operation. High: External EEPROM load failed or incomplete Low: External EEPROM load successful and complete In SMBus/I2C Secondary/Pin mode: This output is High-Z. The pin can be left floating. MODE 61 I, 5-level Sets device control configuration modes. 5-level IO pin as provided in Table 7-4. The pin can be exercised at device power up or in normal operation mode. L0: Pin mode – device control configuration is done solely by strap pins. L1: SMBus/I2C Primary mode – device control configuration is read from external EEPROM. When the DS320PR822 has finished reading from the EEPROM successfully, it will drive the ALL_DONE_N pin LOW. SMBus/I2C secondary operation is available in this mode before, during or after EEPROM reading. Note: during EEPROM reading if the external SMBus/I2C primary wants to access DS320PR822 registers it must support arbitration. L2: SMBus/I2C Secondary mode – device control configuration is done by an external controller with SMBus/I2C primary. L3 and L4 (Float): RESERVED – TI internal test modes. EQ0 / ADDR0 59 I, 5-level In Pin mode: Sets receiver linear equalization (CTLE) boost for channels 0-3 (Bank 0) as provided in Table 7-1. These pins are sampled at device power-up only. In SMBus/I2C mode: Sets SMBus / I2C secondary address as provided in Table 7-5. These pins are sampled at device power-up only. EQ1 / ADDR1 60 I, 5-level EQ0_1 27 I, 5-level Sets receiver linear equalization (CTLE) boost for channels 4-7 (Bank 1) as provided in Table 7-1 in Pin mode. The pin is sampled at device power-up only.EQ1_1 29 I, 5-level GAIN0 / SDA 63 I, 5-level / I/O, 3.3 V LVCMOS, open drain In Pin mode: Flat gain (DC and AC) from the input to the output of the device for channels 0-3 (Bank 0). The pin is sampled at device power-up only. In SMBus/I2C mode: 3.3 V SMBus/I2C data. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus / I2C interface standard. GAIN1 28 I, 5-level Flat gain (DC and AC) from the input to the output of the device for channels 4-7 (Bank 1) in Pin mode. The pin is sampled at device power-up only. GND EP, 9, 12, 21, 24, 32, 41, 44, 53, 56, 64 P Ground reference for the device. EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND return for the device. The EP should be connected to one or more ground planes through the low resistance path. A via array provides a low impedance path to GND. The EP also improves thermal dissipation. PD0 25 I, 3.3 V LVCMOS 2-level logic controlling the operating state of the redriver. Active in all device control modes. The pin has internal 1-MΩ weak pull-down resistor. The pin triggers PCIe Rx detect state machine when toggled. High: power down for channels 0-3 Low: power up, normal operation for channels 0-3 PD1 26 I, 3.3 V LVCMOS 2-level logic controlling the operating state of the redriver. Active in all device control modes. The pin has internal 1-MΩ weak pull-down resistor. The pin triggers PCIe Rx detect state machine when toggled. High: power down for channels 4-7 Low: power up, normal operation for channels 4-7 READ_EN_N 57 I, 3.3 V LVCMOS In SMBus/I2C Primary mode: After device power up, when the pin is low, it initiates the SMBus / I2C Primary mode EEPROM read function. When EEPROM read is complete (indicated by assertion of ALL_DONE_N low), this pin can be held low for normal device operation. During the EEPROM load process the device’s signal path is disabled. In SMBus/I2C Secondary and Pin modes: In these modes the pin is not used. The pin can be left floating. The pin has internal 1-MΩ weak pull-down resistor. DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DS320PR822

Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. SEL0 58 I, 3.3 V LVCMOS The pin selects the mux path for channels 0-3. L: straight data path – RX[0/1/2/3][P/N] connected to TX[0/1/2/3][P/N] through the redriver. H: cross data path – RX[0/1/2/3][P/N] connected to TX[1/0/3/2][P/N] through the redriver. Active in all device control modes. 59 kΩ internal pull-down. Note: the pin also triggers PCIe RX detect state machine when toggled. SEL1 30 I, 3.3 V LVCMOS The pin selects the mux path for channels 4-7. L: straight data path – RX[4/5/6/7][P/N] connected to TX[4/5/6/7][P/N] through the redriver. H: cross data path – RX[4/5/6/7][P/N] connected to TX[5/4/7/6][P/N] through the redriver. Active in all device control modes. 59 kΩ internal pull-down. Note: the pin also triggers PCIe Rx detect state machine when toggled. RX_DET / SCL 62 I, 5-level / I/O, 3.3 V LVCMOS, open drain In Pin mode: Sets receiver detect state machine options as provided in Table 7-3. The pin is sampled at device power-up only. In SMBus/I2C mode: 3.3V SMBus/I2C clock. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus / I2C interface standard. RX0N 2 I Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 0. RX0P 1 I Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 0. RX1N 5 I Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 1. RX1P 4 I Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 1. RX2N 8 I Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 2. RX2P 7 I Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 2. RX3N 11 I Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 3. RX3P 10 I Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 3. RX4N 14 I Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 4. RX4P 13 I Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 4. RX5N 17 I Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 5. RX5P 16 I Non-inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects RXP to RXN. Channel 5. RX6N 20 I Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 6. RX6P 19 I Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 6. RX7N 23 I Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 7. RX7P 22 I Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 7. TX0N 54 O Inverting pin for 100 Ω differential driver output. Channel 0. TX0P 55 O Non-inverting pin for 100 Ω differential driver output. Channel 0. TX1N 51 O Inverting pin for 100 Ω differential driver output. Channel 1. www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DS320PR822

Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. TX1P 52 O Non-inverting pin for 100 Ω differential driver output. Channel 1. TX2N 48 O Inverting pin for 100 Ω differential driver output. Channel 2. TX2P 49 O Non-inverting pin for 100 Ω differential driver output. Channel 2. TX3N 45 O Inverting pin for 100 Ω differential driver output. Channel 3. TX3P 46 O Non-inverting pin for 100 Ω differential driver output. Channel 3. TX4N 42 O Inverting pin for 100 Ω differential driver output. Channel 4. TX4P 43 O Non-inverting pin for 100 Ω differential driver output. Channel 4. TX5N 39 O Inverting pin for 100 Ω differential driver output. Channel 5. TX5P 40 O Non-inverting pin for 100 Ω differential driver output. Channel 5. TX6N 36 O Inverting pin for 100 Ω differential driver output. Channel 6. TX6P 37 O Non-inverting pin for 100 Ω differential driver output. Channel 6. TX7N 33 O Inverting pin for 100 Ω differential driver output. Channel 7. TX7P 34 O Non-inverting pin for 100 Ω differential driver output. Channel 7. VCC 6, 18, 38, 50 P Power supply pins. VCC = 3.3 V ±10%. The VCC pins on this device should be connected through a low-resistance path to the board VCC plane. Install a decoupling capacitor to GND near each VCC pin. RSVD2, 3, 4, 5 3, 15, 35, 47 — Reserved pins – for best signal integrity performance connect the pins to GND. Alternate option would be 0 Ω resistors from pins to GND. (1) I = input, O = output, P = power DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DS320PR822

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCCABSMAX Supply Voltage (VCC) –0.5 4.0 V VIOCMOS,ABSMAX 3.3 V LVCMOS and Open Drain I/O voltage –0.5 4.0 V VIO5LVL,ABSMAX 5-level Input I/O voltage –0.5 2.75 V VIOHS-RX,ABSMAX High-speed I/O voltage (RXnP, RXnN) –0.5 3.2 V VIOHS-TX,ABSMAX High-speed I/O voltage (TXnP, TXnN) –0.5 2.75 V TJ,ABSMAX Junction temperature 150 °C Tstg Storage temperature range –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2 kV may actually have higher performance. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Supply voltage, VCC to GND DC plus AC power should not exceed these limits 3.0 3.3 3.6 V NVCC Supply noise tolerance DC to <50 Hz, sinusoidal1 250 mVpp

50 Hz to 500 kHz, sinusoidal1 100 mVpp

500 kHz to 2.5 MHz, sinusoidal1 33 mVpp Supply noise, >2.5 MHz, sinusoidal1 10 mVpp TRampVCC VCC supply ramp time From 0 V to 3.0 V 0.150 100 ms TA Operating ambient temperature −40 85 °C TJ Operating junction temperature All device modes 125 °C PWLVCMOS Minimum pulse width required for the device to detect a valid signal on LVCMOS inputs PD1/0, SEL1/0, and READ_EN_N 200 μs VCCSMBUS SMBus/I2C SDA and SCL Open Drain Termination Voltage Supply voltage for open drain pull-up resistor 3.6 V FSMBus SMBus/I2C clock (SCL) frequency in SMBus secondary mode 10 400 kHz VIDLAUNCH Source differential launch amplitude 800 1200 mVpp DR Data rate 1 32 Gbps www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: DS320PR822

6.4 Thermal Information

THERMAL METRIC(1) DS320PR822 UNIT NJX, 64 Pins RθJA-High K Junction-to-ambient thermal resistance 22.9 ℃/W RθJC(top) Junction-to-case (top) thermal resistance 9.6 ℃/W RθJB Junction-to-board thermal resistance 7.2 ℃/W ψJT Junction-to-top characterization parameter 1.8 ℃/W ψJB Junction-to-board characterization parameter 7.1 ℃/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 ℃/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.5 DC Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power PACT Device active power 8 channels active, EQ = 0-2 1.15 1.42 W 8 channels active, EQ = 5-19 1.41 1.75 W PRXDET Device power consumption while waiting for far end receiver terminations All channels enabled but no far end receiver detected 166 mW PSTBY Device power consumption in standby power mode All channels disabled (PD1,0 = H) 23 mW Control IO VIH High level input voltage SDA, SCL, PD1, PD0, READ_EN_N, SEL1, SEL0 pins 2.1 V VIL Low level input voltage SDA, SCL, PD1, PD0, READ_EN_N, SEL1, SEL0 pins 1.08 V VOH High level output voltage Rpull-up = 4.7 kΩ (SDA, SCL, ALL_DONE_N pins) 2.1 V VOL Low level output voltage IOL = –4 mA (SDA, SCL, ALL_DONE_N pins) 0.4 V IIH,SEL Input high leakage current for SEL pins VInput = SEL1, SEL0 pins 100 µA IIH Input high leakage current VInput = VCC, (SCL, SDA, PD1, PD0, READ_EN_N pins) 10 µA IIL Input low leakage current VInput = 0 V, (SCL, SDA, PD1, PD0, READ_EN_N, SEL1, SEL0 pins) −10 µA IIH,FS Input high leakage current for fail safe input pins VInput = 3.6 V, VCC = 0 V, (SCL, SDA, , PD1, PD0, READ_EN_N, SEL1, SEL0 pins) 200 µA CIN-CTRL Input capacitance SDA, SCL, PD1, PD0, READ_EN_N, SEL1, SEL0 pins 1.6 pF

5 Level IOs (MODE, GAIN0, GAIN1, EQ0_0, EQ1_0, EQ0_1, EQ1_1, RX_DET pins)

IIH_5L Input high leakage current, 5-level IOs VIN = 2.5 V 10 µA IIL_5L Input low leakage current for all 5-level IOs except MODE. VIN = GND −10 µA IIL_5L,MODE Input low leakage current for MODE pin VIN = GND −200 µA Receiver VRX-DC-CM RX DC Common Mode Voltage Device is in active or standby state 1.4 V ZRX-DC Rx DC Single-Ended Impedance 50 Ω DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DS320PR822

6.5 DC Electrical Characteristics (continued)

over operating free-air temperature and voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ZRX-HIGH-IMP- DC-POS DC input CM input impedance during Reset or power-down Inputs are at VRX-DC-CM voltage 15 kΩ Transmitter ZTX-DIFF-DC DC Differential Tx Impedance Impedance of Tx during active signaling, VID,diff = 1 Vpp 100 Ω VTX-DC-CM Tx DC common mode Voltage 1.0 V ITX-SHORT Tx Short Circuit Current Total current the Tx can supply when shorted to GND 70 mA

6.6 High Speed Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Receiver RLRX-DIFF Input differential return loss 50 MHz to 1.25 GHz −22 dB 1.25 GHz to 2.5 GHz −19 dB 2.5 GHz to 4.0 GHz −16 dB 4.0 GHz to 8.0 GHz −12 dB

8.0 GHz to 16 GHz −9 dB

RLRX-CM Input common-mode return loss 50 MHz to 2.5 GHz −16 dB 2.5 GHz to 8.0 GHz −9 dB

8.0 GHz to 16 GHz −6 dB

Receiver-side pair-to-pair isolation; Port A or Port B Minimum over 10 MHz to 16 GHz range −40 dB Transmitter VTX-AC-CM-PP Tx AC Peak-to-Peak Common Mode Voltage Measured with lowest EQ, GAIN = L4; PRBS-7, 32 Gbps, over at least 106 bits using a bandpass-Pass Filter from 30 kHz - 500 MHz 50 mVpp VTX-CM-DC- ACTIVE-IDLE- DELTA Absolute Delta of DC Common Mode Voltage during L0 and Electrical Idle VTX-CM-DC = |VOUTn+ + VOUTn–|/2, Measured by taking the absolute difference of VTX-CM-DC during PCIe state L0 and Electrical Idle 0 120 mV VTX-RCV- DETECT Amount of Voltage change allowed during Receiver Detection Measured while Tx is sensing whether a low-impedance Receiver is present. No load is connected to the driver output 0 600 mV RLTX-DIFF Output differential return loss 50 MHz to 1.25 GHz −22 dB 1.25 GHz to 2.5 GHz −21 dB 2.5 GHz to 4.0 GHz −19 dB 4.0 GHz to 8.0 GHz −14 dB

8.0 GHz to 16 GHz −10 dB

RLTX-CM Output Common-mode return loss 50 MHz to 2.5 GHz −14 dB 2.5 GHz to 8.0 GHz −10 dB

8.0 GHz to 16 GHz −7 dB

XTTX Transmit-side pair-to-pair isolation Minimum over 10 MHz to 16 GHz range −40 dB Device Datapath TPLHD/PHLD Input-to-output latency (propagation delay) through a data channel For either Low-to-High or High-to-Low transition. 100 140 ps www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: DS320PR822

6.6 High Speed Electrical Characteristics (continued)

over operating free-air temperature and voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LTX-SKEW Lane-to-Lane Output Skew Between any two lanes within a single transmitter. 20 ps TRJ-DATA Additive Random Jitter with data Jitter through redriver minus the calibration trace. 32 Gbps PRBS15. 800 mVpp-diff input swing. 75 fs TRJ-INTRINSIC Intrinsic additive Random Jitter with clock Jitter through redriver minus the calibration trace. 16 GHz CK. 800 mVpp-diff input swing. 40 fs JITTERTOTAL- DATA Additive Total Jitter with data Jitter through redriver minus the calibration trace. 32 Gbps PRBS15. 800 mVpp-diff input swing. 1.5 ps JITTERTOTAL- INTRINSIC Intrinsic additive Total Jitter with clock Jitter through redriver minus the calibration trace. 16 GHz CK. 800 mVpp-diff input swing. 1.7 ps FLAT-GAIN Broadband DC and AC flat gain - input to output, measured at DC Minimum EQ, GAIN1/0 = L0 −5.6 dB Minimum EQ, GAIN1/0 = L1 −3.8 dB Minimum EQ, GAIN1/0 = L2 −1.2 dB Minimum EQ, GAIN1/0 = L3 2.6 dB Minimum EQ, GAIN1/0 = L4 (Float) 0.6 dB EQ-MAX16G EQ boost at max setting (EQ INDEX = 19) AC gain at 16 GHz relative to gain at 100 MHz. 22 dB FLAT- GAINVAR Flat gain variation across PVT measured at DC GAIN1/0 = L4, minimum EQ setting. Max-Min. −2.5 1.5 dB EQ-GAINVAR EQ boost variation across PVT At 16 GHz. GAIN1/0 = L4, maximum EQ setting. Max-Min. −3.0 4.0 dB LINEARITY- DC Output DC Linearity at GAIN1/0 = L4 1700 mVpp LINEARITY- AC Output AC Linearity at 32Gbps at GAIN1/0 = L4 700 mVpp

6.7 SMBUS/I2C Timing Charateristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Secondary Mode tSP Pulse width of spikes which must be suppressed by the input filter 50 ns tHD-STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs THIGH HIGH period of the SCL clock 0.6 µs tSU-STA Set-up time for a repeated START condition 0.6 µs tHD-DAT Data hold time 0 µs TSU-DAT Data setup time 0.1 µs tr Rise time of both SDA and SCL signals Pull-up resistor = 4.7 kΩ, Cb = 10 pF 120 ns tf Fall time of both SDA and SCL signals Pull-up resistor = 4.7 kΩ, Cb = 10 pF 2 ns tSU-STO Set-up time for STOP condition 0.6 µs DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DS320PR822

6.7 SMBUS/I2C Timing Charateristics (continued)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tBUF Bus free time between a STOP and START condition 1.3 µs tVD-DAT Data valid time 0.9 µs tVD-ACK Data valid acknowledge time 0.9 µs Cb Capacitive load for each bus line 400 pF Primary Mode fSCL-M SCL clock frequency 303 kHz tLOW-M SCL low period 1.90 µs THIGH-M SCL high period 1.40 µs tSU-STA-M Set-up time for a repeated START condition 2 µs tHD-STA-M Hold time (repeated) START condition. After this period, the first clock pulse is generated 1.5 µs TSU-DAT-M Data setup time 1.4 µs tHD-DAT-M Data hold time 0.5 µs tR-M Rise time of both SDA and SCL signals Pull-up resistor = 4.7 kΩ, Cb = 10 pF 120 ns TF-M Fall time of both SDA and SCL signals Pull-up resistor = 4.7 kΩ, Cb = 10 pF 2 ns tSU-STO-M Stop condition setup time 1.5 µs EEPROM Timing TEEPROM EEPROM configuration load time Time to assert ALL_DONE_N after READ_EN_N has been asserted. 7.5 ms TPOR Time to first SMBus access Power supply stable after initial ramp. Includes initial power-on reset time. 50 ms www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: DS320PR822

6.8 Typical Characteristics

Figure 6-1 shows typical EQ gain curves versus frequency for different EQ settings. Figure 6-2 shows EQ gain variation over temperature for maximum EQ setting of 19. Figure 6-3 shows typical differential return loss for Rx and Tx pins. Frequency (GHz) EQ Boost (dB) 0 5 10 15 20 25 30 35 40 -20 -15 -10 EQ=0 EQ=1 EQ=2 EQ=3 EQ=4 EQ=5 EQ=6 EQ=7 EQ=8 EQ=9 EQ=10 EQ=11 EQ=12 EQ=13 EQ=14 EQ=15 EQ=16 EQ=17 EQ=18 EQ=19 Figure 6-1. Typical EQ Boost vs Frequency Frequency (GHz) EQ Boost at Max Setting (dB) 0 5 10 15 20 25 30 35 40 -15 -10 Temperature = 25  C Temperature = 0  C Temperature = 85  C Figure 6-2. Typical EQ Boost vs Frequency at Different Temperature with EQ=19 Frequency (GHz) Differential Return Loss (dB) 0 5 10 15 20 25 30 35 40-40 -35 -30 -25 -20 -15 -10 RX SD11TX SD22PCIe 5.0 Mask Figure 6-3. Typical Differential Return Loss DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DS320PR822

6.9 Typical Jitter Characteristics

Figure 6-4 , Figure 6-5, and Figure 6-6 show eye diagrams at BERT source output, through calibration traces, and through 822 respectively. Note: 822 adds little to no random jitter. Residual equalization of ≅4 dB at EQ = 0 setting results in slightly lower deterministic jitter through DUT compared to baseline setup with 7 dB loss. Figure 6-4. At BERT Source Output (1 dB Loss) Figure 6-5. Through Baseline Calibration Trace Setup (7 dB Loss) Figure 6-6. Through DS320PR 822 (7 dB Loss and DUT EQ = 0) www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: DS320PR822

7 Detailed Description

7.1 Overview

The DS320PR822 is an eight-channel multi-rate linear repeater with integrated signal conditioning. The device's signal channels operate independently from one another. Each channel includes a continuous-time linear equalizer (CTLE) and a linear output driver, which together compensate for a lossy transmission channel between the source transmitter and the final receiver. The linearity of the data path is specifically designed to preserve any transmit equalization while keeping receiver equalization effective. The DS320PR822 can be configured three different ways: Pin mode – device control configuration is done solely by strap pins. Pin mode is expected to be good enough for many system implementation needs. SMBus/I2C Primary mode – device control configuration is read from external EEPROM. When the DS320PR822 has finished reading from the EEPROM successfully, it will drive the ALL_DONE_N pin LOW. SMBus/I2C secondary operation is available in this mode before, during, or after EEPROM reading. Note: during EEPROM reading, if the external SMBus/I 2C primary wants to access DS320PR 822 registers, then it must support arbitration. The mode is preferred when software implementation is not desired. SMBus/I2C Secondary mode – provides most flexibility. Requires a SMBus/I 2C primary device to configure DS320PR822 though writing to its secondary address. DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DS320PR822

7.2 Functional Block Diagram

RX_DET/SCL EQ1_0/ADDR1 READ_EN_N ALL_DONE_N GAIN1 EQ1_1 EQ0_0/ADDR0 EQ0_1 Voltage RegulatorVCC MODE PD1 PD0 Shared Digital Core Power-On Reset Always-On 10MHz GND R3P RX3N CTLE Linear Driver TX3P TX3N RX Det RX2P RX2N CTLE Linear Driver TX2P TX2N TermTerm TermRX Det Term RX1P RX1N CTLE Linear Driver TX1P TX1N RX Det RX0P RX0N CTLE Linear Driver TX0P TX0N TermTerm TermRX Det Term RX7P RX7N CTLE Linear Driver TX7P TX7N RX Det RX6P RX6N CTLE Linear Driver TX6P TX6N TermTerm TermRX Det Term RX5P RX5N CTLE Linear Driver TX5P TX5N RX Det RX4P RX4N CTLE Linear Driver TX4P TX4N TermTerm TermRX Det Term DS320PR822

7.3 Feature Description

7.3.1 Linear Equalization

The DS320PR822 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive channel. The receivers implement two stage linear equalizer for wide range of equalization capability. The equalizer stages also provide flexibility to make subtle modifications of mid-frequency boost for best EQ gain profile match with wide range of channel media characteristics. The EQ profile control feature is only available in SMBus/I2C mode. In Pin mode the settings are optimized for FR4 traces. www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: DS320PR822

Table 7-1 provides available equalization boost through EQ control pins or SMBus/I 2C registers. In Pin Control mode EQ1_0 and EQ0_0 pins set equalization boost for channels 0-3 (Bank 0) and EQ1_1 and EQ0_1 for channels 4-7 (Bank 1). In I2C mode individual channels can be independently programmed for EQ boost. Table 7-1. Equalization Control Settings EQUALIZATION SETTING TYPICAL EQ BOOST (dB) EQ INDEX Pin mode SMBus/I2C Mode at 8 GHz at 16 GHz EQ1_0/1 EQ0_0/1 eq_stage1_3:0 eq_stage2_2:0 eq_profile_3:0 eq_stage1_bypass 0 L0 L0 0 0 0 1 3.0 4.0 1 L0 L1 1 0 0 1 4.0 6.0 2 L0 L2 3 0 0 1 5.5 8.0 5 L1 L0 0 0 1 0 6.5 10.5 6 L1 L1 1 0 1 0 7.0 11.5 7 L1 L2 2 0 1 0 7.5 12.5 8 L1 L3 3 0 3 0 8.5 13.0 9 L1 L4 4 0 3 0 9.0 14.0 10 L2 L0 5 1 7 0 10.0 15.0 11 L2 L1 6 1 7 0 10.5 15.5 12 L2 L2 8 1 7 0 11.0 16.5 13 L2 L3 10 1 7 0 12.0 17.0 14 L2 L4 10 2 15 0 12.5 18.0 15 L3 L0 11 3 15 0 13.0 19.0 16 L3 L1 12 4 15 0 14.0 19.5 17 L3 L2 13 5 15 0 14.5 20.5 18 L3 L3 14 6 15 0 15.5 21.0 19 L3 L4 15 7 15 0 16.0 22.0

7.3.2 Flat-Gain

The GAIN1 and GAIN0 pins can be used to set the overall data-path flat gain (DC and AC) of the DS320PR 822 when the device is in Pin mode. The pin GAIN0 sets the Flat-Gain for channels 0-3 (Bank 0) and GAIN1 sets the same for channels 4-7 (Bank 1). In I 2C mode each channel can be independently set. Table 7-2 provides flat gain control configuration settings. In the default recommendation for most systems will be GAIN1,0 = L4 (float) that provides flat gain of 0 dB. The flat-gain and equalization of the DS320PR822 must be set such that the output signal swing at DC and high frequency does not exceed the DC and AC linearity ranges of the devices, respectively. Table 7-2. Flat Gain Configuration Settings Pin mode GAIN0/1 I2C Modeflat_gain_2:0 Flat Gain L0 0 −6 dB L1 1 −4 dB L2 3 −2 dB L4 (float) 5 0 dB (default recommendation) L3 7 +2 dB DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DS320PR822

7.3.3 Receiver Detect State Machine

The DS320PR822 deploys an Rx detect state machine that governs the Rx detection cycle as defined in the PCI express specifications. At power up or after a manual PD0/1 or SEL1/0 toggle the redriver determines whether or not a valid PCI express termination is present at the far end receiver. The RX_DET pin of DS320PR822 provides additional flexibility for system designers to appropriately set the device in desired mode as provided in Table 7-3. PD0 and PD1 pins impact channel groups 0-3 and 4-7 respectively. If all eight channels of DS320PR 822 is used for a same PCI express link, then the PD1 and PD0 pins can be shorted and driven together. For most applications the RX_DET pin can be left floating for default settings. In SMBus/I 2C mode each channel can be configured independently. Table 7-3. Receiver Detect State Machine Settings PD0 PD1 RX_DET Channels 0-3 Rx Common-mode Impedance Channels 4-7 Rx Common-mode Impedance COMMENTS L L L0 Always 50 Ω Always 50 Ω PCI Express Rx detection state machine is disabled. Recommended for non PCIe interface use case where the DS320PR822 is used as buffer with equalization. L L L1 Pre Detect: Hi-Z Post Detect: 50 Ω. Pre Detect: Hi-Z Post Detect: 50 Ω. Outputs polls until 3 consecutive valid detections L L L2 Pre Detect: Hi-Z Post Detect: 50 Ω. Pre Detect: Hi-Z Post Detect: 50 Ω. Outputs polls until 2 consecutive valid detections L L L3 NA NA Reserved L L L4 (Float) Pre Detect: Hi-Z Post Detect: 50 Ω. Pre Detect: Hi-Z Post Detect: 50 Ω. Tx polls every ≅150 µs until valid termination is detected. Rx CM impedance held at Hi-Z until detection Reset by asserting PD0/1 high for 200 µs then low. H L X Hi-Z Pre Detect: Hi-Z Post Detect: 50 Ω. Reset Channels 0-3 signal path and set their Rx impedance to Hi-Z L H X Pre Detect: Hi-Z Post Detect: 50 Ω. Hi-Z Reset Channels 4-7 signal path and set their Rx impedance to Hi-Z. H H X Hi-Z Hi-Z In PCIe applications PD0/1 pins can be connected to PCIe sideband signals PERST# with inverted polarity or one or more appropriate PRSNTx# signals to achieve desired RX detect functionality.

7.3.4 Cross Point

The DS320PR822 provides quad 2x2 cross-point function. Using pin SEL1 and SEL0 pins the 8 channel signal paths can be configured as straight connection or cross connections as shown in Figure 7-1. SEL1 pin impacts channel 0-3 and SEL1 configures channels 4-7. www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: DS320PR822

SEL0=L (Ch 0-3) SEL1=L (Ch 4-7) RX4 RX5 TX4 TX5 RX6 RX7 TX6 TX7 RX0 RX1 TX0 TX1 RX2 RX3 TX2 TX3 SEL0=H (Ch 0-3) SEL1=H (Ch 4-7) RX4 RX5 TX4 TX5 RX6 RX7 TX6 TX7 Figure 7-1. DS320822 Signal Flow Diagram for Cross-Point Mux Operation

7.4 Device Functional Modes

7.4.1 Active PCIe Mode

The device is in normal operation with PCIe state machine enabled by RX_DET = L1/L2/L4. In this mode PD0 and PD1 pins are driven low in a system (for example, by PCIE connector PRSNTx# or fundamental reset PERST# signal). In this mode, the DS320PR 822 redrives and equalizes PCIe Rx or Tx signals to provide better signal integrity.

7.4.2 Active Buffer Mode

The device is in normal operation with PCIe state machine disabled by RX_DET = L0. This mode is recommended for non-PCIe use cases. In this mode the device is working as a buffer to provide linear equalization to improve signal integrity.

7.4.3 Standby Mode

The device is in standby mode invoked by PD1,0 = H. In this mode, the device is in standby mode conserving power.

7.5 Programming

7.5.1 Pin Mode

The DS320PR 822 can be fully configured through pin-strap pins. In this mode the device uses 2-level and 5-level pins for device control and signal integrity optimum settings. DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DS320PR822

7.5.1.1 Five-Level Control Inputs

The DS320PR 822 has eight (EQ0_0, EQ1_0, EQ0_1, EQ1_1, GAIN0, GAIN1, MODE, and RX_DET) 5-level input pins that are used to control the configuration of the device. These 5-level inputs use a resistor divider to help set the 5 valid levels and provide a wider range of control settings. External resistors must be of 10% tolerance or better. The EQ0_0, EQ1_0, EQ0_1, EQ1_1, GAIN0, GAIN1, and RX_DET pins are sampled at power-up only. The MODE pin can be exercised at device power up or in normal operation mode. Table 7-4. 5-Level Control Pin Settings LEVEL SETTING L0 1 kΩ to GND L1 8.25 kΩ to GND L2 24.9 kΩ to GND L3 75 kΩ to GND L4 F (Float)

7.5.2 SMBUS/I2C Register Control Interface

If MODE = L2 (SMBus/I 2C Secondary control mode), then the DS320PR 822 is configured through a standard I2C or SMBus interface that may operate up to 400 kHz. The secondary address of the DS320PR 822 is determined by the pin strap settings on the ADDR1 and ADDR0 pins. Note: secondary addresses to access channels 0-3 (Bank 0) and channels 4-7 (Bank 1) are different. Channel Bank 1 has address which is Channel Bank 0 address +1. The sixteen possible secondary addresses for each channel bank of the DS320PR 822 are provided in Table 7-5. In SMBus/I 2C modes the SCL and SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 k Ω is a good first approximation for a bus capacitance of 10 pF. Table 7-5. SMBUS/I2C Secondary Address Settings ADDR1 ADDR0 7-bit Secondary Address Channels 0-3 (Bank 0) 7-bit Secondary Address Channels 4-7 (Bank 1) L0 L0 0x18 0x19 L0 L1 0x1A 0x1B L0 L2 0x1C 0x1D L0 L3 0x1E 0x1F L0 L4 Reserved Reserved L1 L0 0x20 0x21 L1 L1 0x22 0x23 L1 L2 0x24 0x25 L1 L3 0x26 0x27 L1 L4 Reserved Reserved L2 L0 0x28 0x29 L2 L1 0x2A 0x2B L2 L2 0x2C 0x2D L2 L3 0x2E 0x2F L2 L4 Reserved Reserved L3 L0 0x30 0x31 L3 L1 0x32 0x33 L3 L2 0x34 0x35 L3 L3 0x36 0x37 L3 L4 Reserved Reserved www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: DS320PR822

The DS320PR822 has two types of registers:

Shared Registers: these registers can be accessed at any time and are used for device-level configuration, status read back, control, or to read back the device ID information.
Channel Registers: these registers are used to control and configure specific features for each individual channel. All channels have the same register set and can be configured independent of each other or configured as a group through broadcast writes to Bank 0 or Bank 1. The DS320PR822 features two banks of channels, Bank 0 (Channels 0-3) and Bank 1 (Channels 4-7), each featuring a separate register set and requiring a unique SMBus secondary address. Channel Registers Base Address Channel Bank 0 Access Channel Bank 1 Access 0x00 Channel 0 registers Channel 4 registers 0x20 Channel 1 registers Channel 5 registers 0x40 Channel 2 registers Channel 6 registers 0x60 Channel 3 registers Channel 7 registers 0x80 Broadcast write channel Bank 0 registers, read channel 0 registers Broadcast write channel Bank 1 registers, read channel 4 registers 0xA0 Broadcast write channel 0-1 registers, read channel 0 registers Broadcast write channel 4-5 registers, read channel 4 registers 0xC0 Broadcast write channel 2-3 registers, read channel 2 registers Broadcast write channel 6-7 registers, read channel 6 registers 0xE0 Bank 0 Share registers Bank 1 Share registers

7.5.2.1 Shared Registers

Table 7-6. General Registers (Offset = 0xE2) Bit Field Type Reset Description

7 RESERVED R 0x0 Reserved

6 rst_i2c_regs R/W/SC 0x0 Device reset control: Reset all I2C registers to default values (self-clearing). 5 rst_i2c_mas R/W/SC 0x0 Reset I2C Primary (self-clearing). 4-1 RESERVED R 0x0 Reserved 0 frc_eeprm_rd R/W/SC 0x0 Override MODE and READ_EN_N status to force manual EEPROM configuration load. Table 7-7. EEPROM_Status Register (Offset = 0xE3) Bit Field Type Reset Description 7 eecfg_cmplt R 0x0 EEPROM load complete. 6 eecfg_fail R 0x0 EEPROM load failed. 5 eecfg_atmpt_1 R 0x0 Number of attempts made to load EEPROM image. 4 eecfg_atmpt_0 R 0x0 see MSB 3 eecfg_cmplt R 0x0 EEPROM load complete 2. 2 eecfg_fail R 0x0 EEPROM load failed 2. 1 eecfg_atmpt_1 R 0x0 Number of attempts made to load EEPROM image 2. 0 eecfg_atmpt_0 R 0x0 see MSB Table 7-8. DEVICE_ID0 Register (Offset = 0xF0) Bit Field Type Reset Description 7-4 RESERVED R 0x0 Reserved 3 device_id0_3 R 0x0 Device ID0 [3:1]: 011 2 device_id0_2 R 0x1 see MSB DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DS320PR822

Table 7-8. DEVICE_ID0 Register (Offset = 0xF0) (continued) Bit Field Type Reset Description 1 device_id0_1 R 0x1 see MSB

0 RESERVED R X Reserved

Table 7-9. DEVICE_ID1 Register (Offset = 0xF1) Bit Field Type Reset Description 7 device_id[7] R 0x0 Device ID 0010 1001: DS320PR822 6 device_id[6] R 0x0 see MSB 5 device_id[5] R 0x1 see MSB 4 device_id[4] R 0x0 see MSB 3 device_id[3] R 0x1 see MSB 2 device_id[2] R 0x0 see MSB 1 device_id[1] R 0x0 see MSB 0 device_id[0] R 0x0 see MSB

7.5.2.2 Channel Registers

Table 7-10. RX Detect Status Register (Channel Register Base + Offset = 0x00) Bit Field Type Reset Description 7 rx_det_comp_p R 0x0 Rx Detect positive data pin status: 0: Not detected 1: Detected – the value is latched 6 rx_det_comp_n R 0x0 Rx Detect negative data pin status: 0: Not detected 1: Detected – the value is latched 5-0 RESERVED R 0x0 Reserved Table 7-11. EQ Gain Control Register (Channel Register Base + Offset = 0x01) Bit Field Type Reset Description 7 eq_stage1_bypass R/W 0x0 Enable EQ stage 1 bypass: 0: Bypass disabled 1: Bypass enabled 6 eq_stage1_3 R/W 0x0 EQBoost stage 1 control See Table 7-1 for details5 eq_stage1_2 R/W 0x0 4 eq_stage1_1 R/W 0x0 3 eq_stage1_0 R/W 0x0 2 eq_stage2_2 R/W 0x0 EQ Boost stage 2 control See Table 7-1 for details1 eq_stage2_1 R/W 0x0 0 eq_stage2_0 R/W 0x0 Table 7-12. EQ Gain / Flat Gain Control Register (Channel Register Base + Offset = 0x03) Bit Field Type Reset Description 6 eq_profile_3 R/W 0x0 EQ mid-frequency boost profile See Table 7-1 for details5 eq_profile_2 R/W 0x0 4 eq_profile_1 R/W 0x0 3 eq_profile_0 R/W 0x0 www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: DS320PR822

Table 7-12. EQ Gain / Flat Gain Control Register (Channel Register Base + Offset = 0x03) (continued) Bit Field Type Reset Description 2 flat_gain_2 R/W 0x1 Flat gain select: See Table 7-2 for details1 flat_gain_1 R/W 0x0 0 flat_gain_0 R/W 0x1 Table 7-13. RX Detect Control Register (Channel Register Base + Offset = 0x04) Bit Field Type Reset Description 7-3 RESERVED R 0x0 Reserved 2 mr_rx_det_man R/W 0x0 Manual override of rx_detect_p/n decision: 0: rx detect state machine is enabled 1: rx detect state machine is overridden – always valid RX termination detected 1 en_rx_det_count R/W 0x0 Enable additional RX detect polling 0: Additional RX detect polling disabled 1: Additional RX detect polling enabled 0 sel_rx_det_count R/W 0x0 Select number of valid RX detect polls – gated by en_rx_det_count = 1 0: Device transmitters poll until 2 consecutive valid detections 1: Device transmitters poll until 3 consecutive valid detections Table 7-14. PD Override Register (Channel Register Base + Offset = 0x05) Bit Field Type Reset Description 7 device_en_override R/W 0x0 Enable power down overrides thorugh SMBus/I2C 0: Manual override disabled 1: Manual override enabled 6-0 device_en R/W 0x111111 Manual power down of redriver various blocks – gated by device_en_override = 1 111111: All blocks are enabled 000000: All blocks are disabled Table 7-15. Bias Register (Channel Register Base + Offset = 0x06) Bit Field Type Reset Description 5-3 Bias current R/W 0x100 Control bias current Set 001 for best performance 7,6,2-0 Reserved R/W 0x00000 Reserved

7.5.3 SMBus/I2C Primary Mode Configuration (EEPROM Self Load)

The DS320PR 822 can also be configured by reading from EEPROM. To enter into this mode MODE pin must be set to L1. The EEPROM load operation only happens once after the device's initial power-up. If the DS320PR822 is configured for SMBus Primary mode, then it will remain in the SMBus IDLE state until the READ_EN_N pin is asserted to LOW. After the READ_EN_N pin is driven LOW, the DS320PR 822 becomes an SMBus primary and attempts to self-configure by reading the device settings stored in an external EEPROM (SMBus 8-bit address 0xA0). When the DS320PR 822 has finished reading from the EEPROM successfully, it will drive the ALL_DONE_N pin LOW. SMBus/I 2C secondary operation is available in this mode before, during, or after EEPROM reading. Note: during EEPROM reading, if the external SMBus/I 2C primary wants to access DS320PR822 registers, then it must support arbitration. When designing a system for using the external EEPROM, the user must follow these specific guidelines:

EEPROM size of 2 kb (256 × 8-bit) is recommended.
Set MODE = L1, configure for SMBus Primary mode.
The external EEPROM device address byte must be 0xA0 and capable of 400 kHz operation at 3.3 V supply DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DS320PR822

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The DS320PR822 is a high-speed linear repeater which extends the reach of differential channels impaired by loss from transmission media like PCBs and cables. It can be deployed in a variety of different systems. The following sections outline typical applications and their associated design considerations.

8.2 Typical Applications

The DS320PR822 is a PCI Express linear redriver that can also be configured as interface agnostic redriver by disabling its Rx detect feature. The device can be used in wide range of interfaces including:

Ultra Path Interconnect (UPI) 1.0 and 2.0
DisplayPort 2.0 The DS320PR822 is a protocol agnostic 4-lane linear redriver with PCI Express receiver-detect capability. Its protocol agnostic nature allows it to be used in PCI Express x2, x4, x8, and x16 applications. Figure 8-1 shows how two DS320PR822 can be used to implement 2x2 cross-point for x4 bus width. DS320 PR822 Quad 2x2 X-Point DS320 PR822 Quad 2x2 X-Point TX RX TX RX RX TX RX TX x16 x16 x16 x16 x16 x16 x16x16 Connector-1 PCIe Card-1 CPU-2 CPU-1 Connector-2 PCIe Card-2 Figure 8-1. PCI Express x4 2x2 Cross-point Use Case Using DS320PR822

8.2.1 UPI x24 Lane Cross-Point Configuration

The DS320PR822 can be used in server or motherboard applications as cross point mux to create a flexible CPU to CPU connectivity. The following sections outline detailed procedures and design requirements for a typical UPI x24 lane mux configuration . However, the design recommendations can be used in any lane configuration. DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

Product Folder Links: DS320PR822

8.2.1.1 Design Requirements

As with any high-speed design, there are many factors which influence the overall performance. The following list indicates critical areas for consideration during design.

Use 85 Ω impedance traces when interfacing with PCIe CEM connectors. Length matching on the P and N traces should be done on the single-end segments of the differential pair.
Use a uniform trace width and trace spacing for differential pairs.
Place AC-coupling capacitors near the receiver end of each channel segment to minimize reflections.
For PCIe Gen 3.0, 4.0, and 5.0, AC-coupling capacitors of 220 nF are recommended. Set the maximum body size to 0402 and add a cutout void on the GND plane below the landing pad of the capacitor to reduce parasitic capacitance to GND.
Back-drill connector vias and signal vias to minimize stub length.
Use reference plane vias to ensure a low inductance path for the return current.

8.2.1.2 Detailed Design Procedure

For UPI operation, DS320PR822 is designed with linear data-path to pass the Tx Preset signaling (by CPUs) onto the Rx (of CPUs) for link training to optimize the equalization settings. The linear redriver DS320PR822 helps extend the PCB trace reach distance by boosting the attenuated signals with its equalization, which allows the user to recover the signal by the downstream Rx more easily. The DS320PR822 must be placed in between the CPU Tx and CPU Rx in such a way that signal swing at the device output pins for both Rx and Tx stays within the linearity range of the device. Adjustments to the DS320PR822 EQ setting should be performed based on the channel loss to optimize the eye opening in the Rx partner. The available EQ gain settings are provided in Table 7-1. For most systems the default flat gain setting 0 dB (GAIN = floating) would be sufficient. However, a flat gain attenuation can be utilized to apply extra equalization when needed to keep the data-path linear. The DS320PR822 can be optimized for a given system utilizing its three configuration modes – Pin mode, SMBus/I2C Primary mode, and SMBus/I 2C Secondary mode. In SMBus/I 2C modes the SCL and SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩ is a good first approximation for a bus capacitance of 10 pF. www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: DS320PR822

Figure 8-2 shows a simplified schematic for x24 lane configuration in SMBus/I2C Primary mode. Figure 8-2. Simplified Schematic for UPI x24 Lane Configuration in SMBus/I2C Primary Mode DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

Product Folder Links: DS320PR822

8.2.1.3 Application Curves

The DS320PR 822 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-compliant Tx and Rx are equipped with signal-conditioning functions and can handle channel losses of up to 36 dB at 16 GHz. With the DS320PR 822, the total channel loss between a PCIe root complex and an end point can be extended up to 58 dB at 16 GHz. To demonstrate the reach extension capability of the DS320PR 822, two comparative setups are constructed. In first setup as shown in Figure 8-3 there is no redriver in the PCIe 5.0 link. Figure 8-4 shows eye diagram at the end of the link using SigTest. In second setup as shown in Figure 8-5, the DS320PR822 is inserted in the middle to extend link reach. Figure 8-6 shows SigTest eye diagram. Tek 33 GHz Scope

10 M Math1

capture -> SigTest Phoenix 5.0 Keysight M8040 BERT PCIe 5.0 Comp pa ern P9 800 mV PCIe 5.0 Loss Board PCIe 5.0 Baseboard (CBB) PCIe 5.0 Load Board (CLB) CEM PCIe 5.0 Loss Board Figure 8-3. PCIe 5.0 Link Baseline Setup Without Redriver the Link Elements Figure 8-4. PCIe 5.0 link Baseline Setup Without Redriver Eye Diagram Using SigTest Tek 33GHz Scope 10M Math1 capture -> SigTest Phoenix 5.0 Keysight M8040 BERT PCIe 5.0 Comp pa ern P9 800mV PCIe 5.0 Loss Board PCIe 5.0 Baseboard (CBB) PCIe 5.0 Load Board (CLB) CEM PCIe 5.0 Loss Board DS320PR Redriver Riser card CEM EQ=10, GAIN=L1 Figure 8-5. PCIe 5.0 Link Setup with the DS320PR822 the Link Elements Figure 8-6. PCIe 5.0 Link Setup with the DS320PR822 Eye Diagram Using SigTest Table 8-1 provides the PCIe 5.0 links without and with the DS320PR 822. The illustration shows that redriver is capable of ≅22 dB reach extension at PCIe 5.0 speed with EQ = 10 (EQ gain of 16 dB) and GAIN1,2 = L1 (flat gain of −4 dB). Note: actual reach extension depends on various signal integrity factors. It is recommended to run signal intergrity simulations with all the components in the link to get any guidance. Table 8-1. PCIe 5.0 Reach Extension using the DS320PR822 Setup Pre Channel Loss Post Channel Loss Total Loss Eye at BER 1E-12 SigTest Pass? Baseline – no DUT — — ≅36 dB 14 ps, 41 mV Pass With DUT (DS320PR822) ≅29 dB ≅29 dB ≅58 dB 14 ps, 33 mV Pass www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: DS320PR822

9 Power Supply Recommendations

Follow these general guidelines when designing the power supply: 1. The power supply should be designed to provide the operating conditions outlined in the recommended operating conditions section in terms of DC voltage, AC noise, and start-up ramp time. 2. The DS320PR822 does not require any special power supply filtering, such as ferrite beads, provided that the recommended operating conditions are met. Only standard supply decoupling is required. Typical supply decoupling consists of a 0.1 µF capacitor per VCC pin, one 1.0 µF bulk capacitor per device, and one 10 µF bulk capacitor per power bus that delivers power to one or more DS320PR822 devices. The local decoupling (0.1 µF) capacitors must be connected as close to the VCC pins as possible and with minimal path to the DS320PR822 ground pad. 3. The DS320PR822 voltage regulator output pins require decoupling caps of 0.1 µF near each pin. The regulator is only for internal use. Do not use to provide power to any external component.

10 Layout

10.1 Layout Guidelines

The following guidelines should be followed when designing the layout: 1. Decoupling capacitors should be placed as close to the VCC pins as possible. Placing the decoupling capacitors directly underneath the device is recommended if the board design permits. 2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and impedance controlled. 3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, take care to minimize the via stub, either by transitioning through most or all layers or by back drilling. 4. GND relief can be used (but is not required) beneath the high-speed differential signal pads to improve signal integrity by counteracting the pad capacitance. 5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to the GND planes on other layers. This has the added benefit of improving thermal conductivity from the device to the board. DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

Product Folder Links: DS320PR822

10.2 Layout Example

VCC pins; minimize ground loops Ensure pair-pair gap is > 5W* for minimal pair-pair coupling Top Layer Route high-speed traces as differential coupled microstrips (S=2W*) with tight impedance control (±10%) Use ac-coupling capacitors with 0201 package *W is a trace width. S is a gap between adjacent traces. Ensure high-speed trace length is matched with 5 mils intra-pair; pair-pair skew is less critical Avoid acute angles when routing high- speed traces Add ground pours for additional isolation Bottom Layer Follow connector manufacturer guidelines Use recommended package footprint and ground via placement Figure 10-1. DS320PR822 Layout Example – Sub-Section of a PCIe Riser Card With CEM Connectors www.ti.com DS320PR822 SNLS714 – SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: DS320PR822

11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. DS320PR822 SNLS714 – SEPTEMBER 2022 www.ti.com

Product Folder Links: DS320PR822

www.ti.com 18-Jul-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS320PR822NJXR Active Production WQFN (NJX) | 64 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 5PR8 DS320PR822NJXR.B Active Production WQFN (NJX) | 64 3000 | LARGE T&R - Call TI Call TI -40 to 85 DS320PR822NJXT Active Production WQFN (NJX) | 64 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 5PR8 DS320PR822NJXT.B Active Production WQFN (NJX) | 64 250 | SMALL T&R - Call TI Call TI -40 to 85 DS320PR822NJXTG4 Active Production WQFN (NJX) | 64 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 5PR8 DS320PR822NJXTG4.B Active Production WQFN (NJX) | 64 250 | SMALL T&R - Call TI Call TI -40 to 85 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 18-Jul-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS320PR822NJXR WQFN NJX 64 3000 367.0 367.0 35.0 DS320PR822NJXT WQFN NJX 64 250 210.0 185.0 35.0 DS320PR822NJXTG4 WQFN NJX 64 250 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE 5.6 5.4 10.1 9.9 0.8 0.6 0.05 0.00 2X 8.8 60X 0.4 2X 3.2 64X 0.5 0.3 64X 0.25 0.15 8.6 0.1 4.1 0.1 (0.1) TYP WQFN - 0.8 mm max heightNJX0064A PLASTIC QUAD FLATPACK - NO LEAD 4225514/A 11/2019 0.08 C

0.1 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMM EXPOSED THERMAL PAD SYMM 24 32 5664 SCALE 1.800 AB C

www.ti.com EXAMPLE BOARD LAYOUT 60X (0.4) (R0.05) TYP

0.05 MAX

0.05 MIN

0.575 TYP

1.15 TYP

64X (0.6) 64X (0.2) (5.3) (9.8) (8.6) (4.1) ( 0.2) TYP VIA (0.68) TYP (1.8) TYP (4.05) TYP WQFN - 0.8 mm max heightNJX0064A PLASTIC QUAD FLATPACK - NO LEAD 4225514/A 11/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SEE SOLDER MASK DETAIL 24 32 5664 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 64X (0.6) 64X (0.2) 60X (0.4) (5.3) (9.8) 21X (0.95) 21X (1.16) (R0.05) TYP (1.36) TYP (1.15) TYP WQFN - 0.8 mm max heightNJX0064A PLASTIC QUAD FLATPACK - NO LEAD 4225514/A 11/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 12X EXPOSED PAD 65 66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 24 32 5664

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated

Product Information