DS3205

Features

Document overview

• Manufacturer or author: Todd Zagumny
• PDF pages: 20

Technical content

Features

♦ Compliant to PICMG 3.0 IPMI I2C Requirements ♦ Bidirectional Buffer for SCL and SDA Lines ♦ Compatible with I2C, I2C Fast Mode, SMBus, IPMI, and ATCA® Standards (Up to 400kHz) ♦ Prevents Corruption of System SCL and SDA Lines During Live Insertion/Removal of Boards ♦ Increases Fanout by Connecting Board Bus to Backplane Bus with < 10pF Additional Load ♦ Automatically Delays Initial Bus Connection Until Both Bus Segments Are Idle ♦ SCL and SDA Pins High-Z When VDD = 0V ♦ 1V Precharge on SCL and SDA Lines ♦ ENABLE Input Pin Connects or Isolates Buses ♦ READY Output Pin Indicates “Connected” ♦ FAULT Output Pin Indicates “Stuck Bus” ♦ Optional Rise-Time Accelerators on All Bus Pins ♦ Configurable Rise-Time Accelerator Slew Rate Threshold (0.8V/μs or 1.25V/μs) ♦ Supports Clock Stretching and Multiple Bus Master Arbitration and Synchronization ♦ Optionally Disconnects Board from Backplane When Bus is Stuck Low for ≥ 30ms ♦ Optionally Attempts to Recover a Stuck Bus by Clocking Board SCL ♦ ±15kV ESD Protection (Human Body Model) on Bus Pins ♦ Wide Operating Voltage Range: 2.7V to 5.5V ♦ 5V Tolerant I/Os ♦ Tiny 14-Pin, 3mm x 3mm TDFN Package Rev: 111607 SMBus is a trademark of Intel Corp. ATCA, AdvancedTCA, and CompactPCI are registered trademarks of PCI Industrial Computer Manufacturers Group (PICMG).

Rev: 111607 2 of 20 Table of Contents

Rev: 111607 4 of 20 List of Tables

Rev: 111607 6 of 20 2. Applicable Diagrams Figure 2-1. Block Diagram BACKPLANE-TO-CARD CONNECTION BACKPLANE-TO-CARD CONNECTION SCLIN SCLOUT SDAIN SDAOUT STOP BIT, BUS IDLE, AND CONNECT STATE MACHINE 150K 150K

1 VOLT

Rev: 111607 7 of 20 Figure 2-2. Backplane-to-Card Connection Detail SLEW RATE DETECT SLEW RATE DETECT 150k 150k acc acc fast fastenaena SxIN SxOUT FORCE CLOCK ACIR ACOEASR PRECHARGE REF REFSxIN SxOUT

Rev: 111607 8 of 20 Figure 2-3. DS3205 State Diagram INITIAL BUS WAIT ACTIVE STUCK BUS CLOCKING STUCK BUS DISCONNECT 130µs COMPLETED

16 FORCED

READY = 1 stuck bus = 1 & SBCLK = 1 & SBDIS = 0 stuck bus = 0 + SBCLK = 0 stuck bus = 0 + (SBCLK = 0 & SBDIS = 0) stuck bus = 1 & SBCLK = 0 & SBDIS = 1 (input stop + input idle) & output high FORCE 16 CLOCKS AT SCLOUT PIN input stop = rising edge on SDAIN while SCLIN high input idle = SDAIN and SCLIN high for 140µs stuck bus = SDAOUT or SCLOUT low for 30ms

Rev: 111607 9 of 20 3. Pin Descriptions Table 3-1. Pin Descriptions NAME PIN TYPE FUNCTION ENABLE 1 I Enable Input. This input pin establishes the board-to-backplane connection when driven to a level above VDD/2 (approximately) with 50mV hysteresis. 0 = Disable connection and enter low-power mode. 1 = Enable connection of backplane and board buses. SCLOUT 2 I/O Serial Clock Output. This pin is connected to the board’s SCL signal. SDAOUT 3 I/O Serial Data Output. This pin is connected to the board’s SDA signal. ACIE 4 I Accelerator Current on Inputs Enable. This input pin enables/disables the rise- time accelerators on the bus input pins. 0 = Disable rise-time accelerator on SCLIN and SDAIN. 1 = Enable rise-time accelerator on SCLIN and SDAIN. ACOE 5 I Accelerator Current on Outputs Enable. This input pin enables/disables the rise- time accelerators on the bus output pins. 0 = Disable rise-time accelerator on SCLOUT and SDAOUT. 1 = Enable rise-time accelerator on SCLOUT and SDAOUT. ASR 6 I Accelerator Slew Rate Threshold Select. This input pin selects the rate for the rise-time accelerators. 0 = 0.8V/μs 1 = 1.25V/μs VSS 7 P Ground READY 8 Ood Connected Status Indicator. This is an open-drain output that goes high when the device is in the ACTIVE state. See the state diagram in Figure 2-3. This pin should have an external 10kΩ pullup resistor. 0 = Backplane and board buses not connected. 1 (float) = Backplane and board buses connected. FAULT 9 Ood Active-Low Bus Fault Indicator. This open-drain output pin indicates a “stuck bus” condition when = 0. This pin should have an external 10kΩ pullup resistor. 0 = Either SCLOUT or SDAOUT has been low > 30ms. 1 = No stuck bus fault. SBCLK 10 I Stuck Bus Clocking Enable. Asserting this pin high causes the DS3205 to drive clock pulses onto the SCLOUT pin in an attempt to free a stuck bus when a “stuck bus” condition has been detected. See Section 4 and Figure 2-3 for more information on the stuck bus condition. 0 = Disable automatic clocking during stuck bus fault. 1 = Enable automatic clocking during stuck bus fault. Note: Asserting both SBDIS and SBCLK high at the same time is not valid and can produce unwanted results. SBDIS 11 I Stuck Bus Disconnect Enable. Asserting this pin high causes the DS3205 to disconnect the backplane signals from the board signals when a “stuck bus” condition has been detected. See Section 4 and Figure 2-3 for more information on the stuck bus condition. 0 = Disable automatic disconnect on stuck bus fault. 1 = Enable automatic disconnect on stuck bus fault. Note: Asserting both SBDIS and SBCLK high at the same time is not valid and can produce unwanted results.

Rev: 111607 10 of 20 NAME PIN TYPE FUNCTION SDAIN 12 I/O Serial Data Input. This pin is connected to the backplane SDA signal. SCLIN 13 I/O Serial Clock Input. This pin is connected to the backplane SCL signal. VDD 14 P Power Supply. 2.7V to 5.5V EP — — Exposed Pad I/O = Input/Output I = Input Ood = Output, Open Drain P = Power

Rev: 111607 11 of 20 4. Functional Description

4.1 Overview

See the DS3205 state diagram in Figure 2-3.

4.2 Startup

When the DS3205 is first powered on, it is in a low-pow er state with the SCLIN, SCLOUT, SDAIN, and SDAOUT pins in a high-impedance state. If the ENABLE pin is pulled high, the DS3205 waits until the supply voltage rises above approximately 2V, when the precharge circui try becomes active and forces 1V through 150k Ω resistors into all SCL and SDA pins. The 1V precharge minimizes bus disturbances when the backplane and card are at opposing logic levels. The DS3205 then waits about 130 μs for the external connections and internal circuitry to settle. After this wait time, the DS32 05 enters the BUS WAIT state where it lo oks for either a stop bit on the input (rising edge on the SDAIN pin while SCLIN remains high) or an input bus idle condition (SDAIN and SCLIN both high for 140 μs) while both SDAOUT and SCLOUT pins are high. Once these conditions are met, the precharge circuit is turned off and the DS3205 enters the ACTIVE state. While in the ACTIVE state, the DS3205 establishes a bidirectional connection between the SDAIN and SDAOUT pins and the SCLIN and SCLOUT pins. The voltage on any bus pin is buffered and offset an additional +75mV (approximately) to the other side. Whichever side is pull ed closest to ground has priority. For example, if SCLOUT is pulled closer to ground than SCIN, SCIN is driven to a voltage 75mV higher than SCOUT.

4.3 Rise-Time Accelerators

If current acceleration is enabled through the ACIE or AC OE pins, the DS3205 pulls up more strongly, shortening the rise time compared to using only the external bus pul lup resistors. The pullup pr ovided by the driver during acceleration is approximately 3.5mA instead of its usual 100 μA. This acceleration current on one side of the buffer is activated when the bus voltage on the other side is gr eater than 0.6V and its slew rate is greater than 0.8V/ μs (ASR low) or 1.2V/ μs (ASR high) and the corresponding ACIE and/or ACOE pin is pulled high. The acceleration current is deactivated after the accelerated bus pin rises within 0.9V of V DD. For example, if the ACOE pin is high, when the SCLIN pin rises above 0.6V with a fast slew rate, the SCLOUT pin is pulled up towards V DD with more than 3mA of current. This current ceases when the SCLOUT pin rises to within 0.9V of VDD.

4.4 READY Output Pin

The READY pin is pulled low whenever the DS3205 is not in its ACTIVE state. An external pullup resistor brings the READY pin high when the bidirectional connection is established.

4.5 ENABLE Input Pin

If the ENABLE pin is pulled low, the backplane side di sconnects from the board side and the device enters a low- power state with the READY pin asserted low. Also, the rise-time accelerators and precharge circuitry are disabled. Setting ENABLE low causes the device to disconnect t he board side from the backplane side and enter the low- power mode.

4.6 Stuck Bus Condition

If the SDAOUT and SCLOUT pins remain low for 30ms the bus is assumed to be stuck. This 30ms timeout is restarted only when the SDAOUT and SCLOUT pins are both high. The FAULT pin pulls low and remains low until the bus is unstuck. If the SBCLK pin is high, the DS3205 attempts to unstick the bus by first disconnecting all SDA and SCL pins for 50 μs, then pulls down on the SCLOUT pin 16 times at a 8kHz rate. If the bus becomes unstuck during this process (SDAOUT and SCLOUT both go high ), the DS3205 returns to the BUS WAIT state. The precharge circuitry becomes active, and, as soon as a stop bit or bus idle is detected on the input while both

Rev: 111607 12 of 20 SDAOUT and SCLOUT pins are high, the DS3205 goes to t he ACTIVE state, reestablishing bidirectional buffering. If the bus remains stuck after 16 clocks, the DS3205 sits with all SDA and SCL pins precharged until SDAOUT and SCLOUT go high. If the SBCLK pin is low and the SBDIS pin is high, the DS3205 only precharges the SDA and SCL pins until the bus becomes unstuck. If neither SBCLK nor SBDIS are high, the DS3205 remains in its ACTIVE state, but the FAULT pin pulls low as an alert that the bus is stuck. If the DS3205 is in the STUCK BUS CLOCKING state, se tting the SBCLK pin low forces the part into the BUS WAIT state. If the DS3205 is in the STUCK BUS DISCON NECT state, setting the SBDIS pin low forces the part into the BUS WAIT state. These transiti ons are shown in the state diagram in Figure 2-3. Returning to the BUS WAIT state resets the 30ms stuck bus counter.

4.7 Bus Capacitance Requirements

A minimum of 47pF bus capacitance is required on 5V systems; 3.3V sy stems require a minimum of 22pF for proper operation. Buses with less capacitance should be pr ovisioned with an added capacitor to ground in order to maintain the minimum required capacitance. The DS3205 to lerates capacitance levels slightly marginal with respect to these requirements.

4.8 Pullup Resistor

When SCLIN, SCLOUT, SDAIN, or SDAOUT is driven to a logic-low level, that pin's corresponding output pin is driven to a slightly higher level. For example, if SDAOUT is driven low, SDAIN is driven to a level according to the following formula. VSDAIN = VSDAOUT + 75mV + (VDD / R) × 20Ω EXAMPLE: IF R = bus pullup resistor = 10kΩ IF VDD = 3.3V IF VSDAOUT = 10mV VSDAIN = 91.6mV (typical)

Rev: 111607 13 of 20 5. Operating Parameters ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may c ause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. Exposure to the absolute ma ximum rating conditions for ex tended periods may affect device reliability. Ambient ope rating temperature range when device is mounted on a four-layer JEDEC test board with no airflow. Note 1: Specifications to -40°C are guaranteed by design and not production tested.

5.1 Electrical Characteristics

Table 5-1. Power Supply (VDD = 2.7V to 5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V DD 2.7 5.5 V Supply Current I DD VDD = 5.5V, VSDAIN = VSCLIN = 0V 4 7 mA Shutdown Current I SD VENABLE = 0V, all other pins at VDD or VSS 200 500 μA Table 5-2. Startup Characteristics (VDD = 2.7V to 5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Precharge Voltage V PRE SDA, SCL floating (Note 1) 0.75 1.00 1.25 V ENABLE Threshold Rising V THR (EN, RISE) Enabling VDD / VDD x 0.7 V ENABLE Threshold Falling V THR (EN, FALL) Disabling VDD x 0.3 VDD / 2 V Enable Time t EN ENABLE high ≥ READY 350 420 μs Disable Time t DIS ENABLE low ≥ READY 25 50 ns Bus Idle Time t IDLE 350 430 μs SDAIN to READY After STOP t STOP (Note 2) 0.7 1.0 μs SCLOUT/SDAOUT to READY tREADY 0.6 1.0 μs

Rev: 111607 14 of 20 Table 5-3. I2C Bus Pins Characteristics (VDD = 2.7V to 5.5V, TA = -40°C to +85°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input/Output Offset Voltage V OS 75 mV ENABLE Input Current I EN ENABLE between VSS and VDD -1 +1 μA I2C Capacitance (Note 3) C BUS Applies to SCLIN, SDAIN, SCLOUT, SDAOUT pins; signals between -0.5V and 3.65V, V DD between 0V and 5.5V 3 10 pF Leakage Current on I2C Pins I OFF (BUS) ENABLE = VSS or VDD < VDD,UV -10 +10 μA Output Low Open-Drain Outputs V OL (OD) Applies to READY and FAULT pins, IPULLUP = 3mA 0.4 V I2C Bus VOUTLOW V OL (BUS) I IN = -3mA 0.3 0.5 V I2C Bus Clock See Table 5-5 Bus Stuck Low Timer t STUCK SDAOUT or SCLOUT = low 15 30 45 ms Transient-Boosted Pullup Current IPULL Low to high transition on SDA, SCL pins; V DD = 0.3V 1 mA Table 5-4. Device Control Pins Characteristics (VDD = 2.7V to 5.5V, TA = -40°C to +85°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Logic Input Threshold Voltage V THR (LOG) Applies to SBDIS, SBCLK, ASR, ACOE, and ACIE inputs 1.6 1.8 2.0 V Logic Input Hysteresis V HYS Any logic input pin except ENABLE (Note 3) 50 mV ENABLE Input Threshold See Table 5-2 Input Leakage I IL Applies to SBDIS, SBCLK, ASR, ACOE, ACIE, and ENABLE -10 +10 μA Leakage Current on Open-Drain Outputs IOFF (OD) Applies to READY and FAULT pins, ENABLE = VSS -10 +10 μA Lead Capacitance C IO READY, ENABLE, SBDIS, SBCLK, ASR, ACOE, ACIE, FAULT pins 10 pF

Rev: 111607 15 of 20 Table 5-5. Timing Characteristics (VDD = 2.7V to 5.5V, TA = -40°C to +85°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Frequency f BUS 0 400 kHz Bus Free Time Between START and STOP Condition fBUF (Note 3) 1.3 μs Hold Time After Repeated START Condition t HD,START (Note 3) 0.6 μs Repeated START Condition Setup Time tSU,START (Note 3) 0.6 μs STOP Condition Setup Time t SU,STOP (Note 3) 0.8 μs Clock Low Period t LOW (Note 3) 1.3 μs Clock High Period t HIGH 0.6 μs Clock-Data Fall Time t F (Note 4) 20 + 0.1CB 250 ns Clock-Data Rise Time t R (Notes 3, 4) 20 + 0.1CB ns Note 1: Applies over full operational temperature range. Note 2: Delays that can occur after enable and/or idle time have passed. Note 3: Guaranteed by design. Not production tested. Note 4: CB = Total capacitance of one bus line (pF). Note 5: IPULL varies with temperature and voltage.

Rev: 111607 16 of 20 6. Pin Configuration Figure 6-1. 14-Pin TDFN with Exposed Pad Pin Configuration

Rev: 111607 17 of 20 7. Package Information (The package drawing(s) in this data sheet may not refl ect the most current specif ications. The package number provided for each package is a link to the latest package outline information. Go to www.maxim-ic.com/packages.) 7.1 14-Pin TDFN with Exposed Pad ( 21-0137)

Rev: 111607 18 of 20

Rev: 111607 19 of 20 8. Thermal Information Table 8-1. Thermal Properties—14-Pin TDFN Package PARAMETER VALUE Target Ambient Temperature Range -40°C to +85°C Theta J (Die Junction Temperature Range) -40°C to +125°C

Rev: 111607 20 of 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products. 9. Data Sheet Revision History REVISION DATE DESCRIPTION PAGES CHANGED 111607 Initial data sheet release. —