DS3153N

DS3151_07 MAXIM | Alldatasheet

Document overview

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Technical content

1 of 61 REV: 030607 Note: Some revisions of this device may incorp orate deviations from published s pecifications known as erra ta. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS3151 (single), DS3152 (dual), DS3153 (triple), and DS3154 (quad) line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit paths and a built-in jitter attenuator.

APPLICATIONS

SONET/SDH and PDH Multiplexers Digital Cross-Connects Access Concentrators ATM and Frame Relay Equipment Routers PBXs DSLAMs CSUs/DSUs FUNCTIONAL DIAGRAM

FEATURES

ƒ Single, Dual, Triple, or Quad Integrated Transmitter, Receiver, and Jitter Attenuators for DS3, E3, and STS-1 ƒ Each Port Independently Configurable ƒ Perform Receive Clock/Data Recovery and Transmit Waveshaping ƒ Hardware or CPU Bus Configuration Options ƒ Jitter Attenuators can be Placed in Either the Receive or Transmit Paths ƒ Interface to 75Ω Coaxial Cable at Lengths Up to 380m (DS3), 440m (E3), or 360m (STS-1) ƒ Use 1:2 Transformers on Tx and Rx ƒ Require Minimal External Components ƒ Local and Remote Loopbacks ƒ Low-Power 3.3V Operation (5V Tolerant I/O) ƒ Industrial Temperature Range: -40°C to +85°C ƒ Small Package: 144-Pin, 13mm x 13mm Thermally Enhanced CSBGA ƒ IEEE 1149.1 JTAG Support Features continued on page 5.

ORDERING INFORMATION

PART LIUs TEMP RANGE PIN-PACKAGE DS3151 1 0°C to +70°C 144 TE-CSBGA DS3151N 1 -40°C to +85°C 144 TE-CSBGA DS3152 2 0°C to +70°C 144 TE-CSBGA DS3152N 2 -40°C to +85°C 144 TE-CSBGA DS3153 3 0°C to +70°C 144 TE-CSBGA DS3153N 3 -40°C to +85°C 144 TE-CSBGA DS3154 4 0°C to +70°C 144 TE-CSBGA DS3154N 4 -40°C to +85°C 144 TE-CSBGA RXP RXN TXP TXN CLK DATA CLK DATA LINE IN DS3, E3, OR STS-1 LINE OUT DS3, E3, OR STS-1 RECEIVE CLOCK AND DATA TRANSMIT CLOCK AND DATA EACH LIU STATUS CONTROL Dallas Semiconductor DS315x DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs www.maxim-ic.com DEMO KIT AVAILABLE

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 2 of 61 TABLE OF CONTENTS

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 4 of 61 LIST OF TABLES

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 5 of 61 FEATURES (continued) Receiver ƒ AGC/equalizer block handles from 0 to 15dB of cable loss ƒ Loss-of-lock (LOL) PLL status indication ƒ Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp ƒ Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ITU G.775) ƒ Optional B3ZS/HDB3 decoder ƒ Line-code violation output pin and counter ƒ Binary or bipolar framer interface ƒ On-board 215 - 1 and 223 - 1 PRBS detector ƒ Clock inversion for glueless interfacing ƒ Tri-state clock and data outputs support protection switching applications ƒ Per-channel power-down control Transmitter ƒ Binary or bipolar framer interface ƒ Gapped clock capable up to 51.84MHz ƒ Wide 50 ±20% transmit clock duty cycle ƒ Clock inversion for glueless interfacing ƒ Optional B3ZS/HDB3 encoder ƒ On-board 215 - 1 and 223 - 1 PRBS generator ƒ Complete DS3 AIS generator (ANSI T1.107) ƒ Unframed all-ones generator (E3 AIS) ƒ Line build-out (LBO) control ƒ Tri-state line driver outputs support protection switching applications ƒ Per-channel power-down control ƒ Output driver monitor 1. DETAILED DESCRIPTION The DS3151 (single), DS3152 (dual), DS3153 (triple), and DS3154 (quad) LIUs perform the functions necessary for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit paths and a built-in jitter attenuator. The receiver perfor ms clock and data recovery fr om a B3ZS- or HDB3-coded alternate mark inversion (AMI) signal and monitors for loss of the incoming signal. The receiver optionally performs B3ZS/HDB3 decoding and outputs the recovered data in eith er binary or bipolar format. The transmitter accepts data in either binary or bipolar format, optionally perfo rms B3ZS/HDB3 encoding, and drives standard pulse-shape waveforms onto 75 Ω coaxial cable. The jitter attenuator can be mapped into the receiver data path, mapped into the transmitter data path, or be disabled. The DS315x LIUs conform to the telecommuni cations standards listed in Table 1-A. Figure 1-1 shows the external components required for proper operation.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 6 of 61 Table 1-A. Applicable Telecommunications Standards SPECIFICATION SPECIFICATION TITLE ANSI T1.102-1993 Digital Hierarchy—Electrical Interfaces T1.107-1995 Digital Hierarchy—Formats Specification T1.231-1997 Digital Hierarchy—Layer 1 In-Service Di gital Transmission Performance Monitoring T1.404-1994 Network-to-Customer Installation—DS3 Metallic Interface Specification ITU-T G.703 Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991 G.751 Digital Multiplex Equipment Operating at the Third-Order Bit Rate of 34,368kbps and the Fourth-Order Bit Rate of 139,264kbps and Using Positive Justification, 1993 G.775 Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria, November 1994 G.823 The Control of Jitter and Wander within Digital Networks that are Based on the 2048kbps Hierarchy, 1993 G.824 The Control of Jitter and Wander within Digital Networks that are Based on the 1544kbps Hierarchy, 1993 O.151 Error Performance Measuring Equipment Operating at the Primary Rate and Above, October 1992 ETSI ETS 300 686 Business TeleCommunications; 34Mbps and 140Mbps Digital Leased Lines (D34U, D34S, D140U, and D140S); Network Interface Presentation, 1996 ETS 300 687 Business TeleCommunications; 34Mbps Digital Leased Lines (D34U and D34S); Connection Characteristics, 1996 ETS EN 300 689 Access and Terminals (AT); 34Mbps Digital Leased Lines (D34U and D34S); Terminal equipment interface, July 2001 TBR 24 Business TeleCommunications; 34Mbps Digital Unstructured and Structured Lease Lines; Attachment Requirements for Terminal Equipment Interface, 1997 TELCORDIA GR-253-CORE SONET Transport Systems: Common Generic Criteria, Issue 2, December 1995 GR-499-CORE Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 1, December 1998

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 9 of 61 Figure 3-2. CPU Bus Mode Block Diagram TTSn PRBSn TCLKn TNEGn RCLKn RTSn HW HIZ MOT CS WR/R/W RD/DS A[5:0] D[7:0] INT ALE RST Analog Local Loopback Preamp Clock & Data Recovery Line Driver Waveshaping Clock Invert RXPn RXNn TXPn TXNn RLOSn Power Supply B3ZS/ HDB3 Encoder Mux Mux PRBS Detector B3ZS/HDB3 Decoder Digital LOS Detector squelch Jitter Attenuator (can be placed in either the receive path or the transmit path) Driver Monitor Loopback Control TDMn VDD VSS Remote Loopback CPU Bus Interface and Global Configuration Output Drivers, Clock Invert Digital Local Loopback Automatic Gain Control Adaptive Equalizer ALOS STMCLK Clock Mux E3MCLK T3MCLK TPOSn/TDATn RNEGn/RLCVn RPOSn/RDATn AIS, 100100…, PRBS Pattern Generation Mux Dallas Semiconductor DS315x

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 10 of 61 4. PIN DESCRIPTIONS Table 4-A. Active I/O Pins—H ardware and CPU Bus Modes NAME TYPE FUNCTION HARDWARE MODE CPU BUS MODE TRANSMITTER TCLKn I Transmitter Clock Active Active TPOSn/TDATn I Transmitter Positive AM I/Transmitter Data Active Active TNEGn I Transmitter Negative AMI Active Active TXPn, TXNn O Transmitter Anal og Outputs Active Active TTSn I Transmitter Tri-State Enable Active Active TDMn O Transmitter Driver Monitor Output Active Active TDSAn, TDSBn I Transmitter Data Select Active TLBOn I Transmitter Line Build-Out Enable Active TJAn I Transmitter Jitter Attenuator Enable Active RECEIVER RXPn, RXNn I Receiver Anal og Inputs Active Active RCLKn O Receiver Clock Active Active RPOSn/RDATn O Receiver Positive AMI/Receiver Data Active Active RNEGn/RLCVn O Receiver Ne gative AMI/Line-Code Violation Active Active RTSn I Receiver Tri-State Enable Active Active RLOSn O Receiver LOS Output Active Active RMONn I Receiver Monitor Enable Active RJAn I Receiver Jitter Attenuator Enable Active GLOBAL HIZ I High-Z Enable Active Active RST I Reset Enable Active Active HW I Hardwired Mode Enable Active Active T3MCLK I T3 Master Clock (44.736MHz ±20ppm) Active Active E3MCLK I E3 Master Clock (34.368MHz ±20ppm) Active Active STMCLK I STS-1 Master Clock (51.840MHz ±20ppm) Active Active PRBSn O PRBS Detector Ou tput Active Active LLBn, RLBn I Local Loopback, Remote Loopback Select Active E3Mn, STSn I E3 Mode Enable, STS-1 Mode Enable Active RBIN I Receiver Binary In terface Enable Active TBIN I Transmitter Binary Interface Enable Active RCINV I Receiver Clock Invert Active TCINV I Transmitter Clock Invert Active MOT I Motorola CPU Bus Enable Active ALE I Address Latch Enable Active CS I Chip Select Active WR / R/W I Write Enable / Read/Write Select Active RD/DS I Read Enable/Data Strobe Active A[5:0] I Address Bus Active D[7:0] I/O Data Bus Active INT O Interrupt Output Active Note: In CPU bus mode, status/control pins are replaced by register bits. See Register Map in Section 5. For pin names of the form PINn, n = LIU# = 1, 2, 3, or 4. PIN1 is on LIU 1, PIN2 is on LIU 2, etc.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 11 of 61 Table 4-B. Transmitter Pin Descriptions NAME I/O FUNCTION TCLKn I Transmitter Clock. A DS3 (44.736MHz ±20ppm), E3 (34.368MHz ±20ppm), or STS-1 (51.840MHz ±20ppm) clock should be applied at this signal. Data to be transmitted is clocked into the device at TPOS/TDAT and TNEG either on the rising edge of TCLK (TCINV = 0) or the falling edge of TCLK (TCINV = 1). See Section 7 for additional details. TPOSn/ TDATn I Transmitter Positive AMI/Transmitter Data. When the transmitter is configured to have a bipolar interface (TBIN = 0), a positive pulse is transmitted on the line when TPOS is high. When the transmitter is configured to have a binary interface (TBIN = 1), the data on TDAT is transmitted after B3ZS or HDB3 encoding. TPOS/TDAT is sampled either on the rising edge of TCLK (TCINV = 0) or on the falling edge of TCLK (TCINV = 1). TNEGn I Transmitter Negative AMI. When the transmitter is configured to have a bipolar interface (TBIN = 0), a negative pulse is transmitted on the line when TNEG is high. When the transmitter is configured to have a binary interface (TBIN = 1), TNEG is ignored and should be wired either high or low. TNEG is sampled either on the rising edge of TCLK (TCINV = 0) or on the falling edge of TCLK (TCINV = 1). TXPn, TXNn O3 Transmitter Analog Outputs. These differential AMI outputs are coupled to the outbound 75Ω coaxial cable through a 2:1 step-down transformer (Figure 1-1). These outputs can be tri-stated using the TTS pin or the TTS or TPS configuration bits. TTSn I Transmitter Tri-State Enable (Active Low). TTS tri-states the transmitter outputs (TXP and TXN). This feature supports applications requiring LIU redundancy. Transmitter outputs from multiple LIUs can be wire-ORed together, eliminating external switches. The transmitter continues to operate internally when TTS is active. 0 = tri-state the transmitter output driver 1 = enable the transmitter output driver TDMn O Transmitter Driver Monitor (Active Low, Open Drain). TDM reports the status of the transmit driver monitor. When the transmit driver monitor detects a faulty transmitter, TDM is driven low. TDM requires an external pullup to VDD. TDSAn, TDSBn I Transmitter Data Select. These inputs sele ct the source of the transmit data. See Table 4-F for details. TLBOn I Transmitter Line Build-Out Enable. TLBO indicates cable length for waveform shaping in DS3 and STS-1 modes. TLBO is ignored for E3 mode and should be wired high or low. 0 = cable length ≥ 225ft 1 = cable length < 225ft TJAn I Transmitter Jitter Attenuator Enable 0 = remove jitter attenuator from the transmitter path 1 = insert jitter attenuator into the transmitter path (Note that TJA = 1 takes precedence over RJA = 1.)

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 12 of 61 Table 4-C. Receiver Pin Descriptions NAME I/O FUNCTION RXPn, RXNn I Receiver Analog Inputs. These differential AMI inputs are coupled to the inbound 75Ω coaxial cable through a 1:2 step-up transformer (Figure 1-1). RCLKn O3 Receiver Clock. The recovered clock is output on the RCLK pin. Recovered data is output on the RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1). During a loss of signal (RLOS = 0), the RCLK output signal is derived from the LIU’s master clock. RPOSn/ RDATn O3 Receiver Positive AMI/Receiver Data. When the receiver is configured to have a bipolar interface (RBIN = 0), RPOS pulses high for each positive AMI pulse received. When the receiver is configured to have a binary interface (RBIN = 1), RDAT outputs decoded binary data. RPOS/RDAT is updated either on the falling edge of RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1). RNEGn/ RLCVn O3 Receiver Negative AMI/Line-Code Violation. When the receiver is configured to have a bipolar interface (RBIN = 0), RNEG pulses high for each negative AMI pulse received. When the receiver is configured to have a binary interface (RBIN = 1), RLCV pulses high to flag code violations. See Section 6 for further details on code violations. RNEG/RLCV is updated either on the falling edge of RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1). RTSn I Receiver Tri-State Enable (Active Low). RTS tri-states the RPOS/RDAT, RNEG/RLCV, and RCLK receiver outputs. This feature supports applications requiring LIU redundancy. Receiver outputs from multiple LIUs can be wire-ORed together, eliminating the need for external switches or muxes. The receiver continues to operate internally when RTS is low. 0 = tri-state the receiver outputs 1 = enable the receiver outputs RLOSn O Receiver Loss of Signal (Active Low, Open Drain). RLOS is asserted upon detection of 175 ±75 consecutive zeros in the receive data stream. RLOS is deasserted when there are no excessive zero occurrences over a span of 175 ±75 clock periods. An excessive zero occurrence is defined as three or more consecutive zeros in the DS3 and STS-1 modes or four or more zeros in the E3 mode. See Section 6 for additional details. RMONn I Receive Monitor-Preamp Enable. RMON determines whether or not the receiver’s preamp is enabled to provide flat gain to the incoming signal before the AGC/equalizer block processes it. This feature should be enabled when the device is being used to monitor signals that have been resistively attenuated by a monitor jack. 0 = disable the monitor preamp 1 = enable the monitor preamp RJAn I Receiver Jitter Attenuator Enable 0 = remove jitter attenuator from the receiver path 1 = insert jitter attenuator into the receiver path (Note that TJA = 1 takes precedence over RJA = 1.)

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 13 of 61 Table 4-D. Global Pin Descriptions NAME I/O FUNCTION HIZ IPU High-Z Enable Input (Active Low, Open Drain) 0 = tri-state all output pins (Note that the JTRST pin must be low.) 1 = normal operation RST IPU Reset Input (Active Low, Open Drain, Internal 10kΩ Pullup to VDD). When this global asynchronous reset is pulled low, the internal circuitry is reset and the internal registers (CPU bus mode) are forced to their default values. The device is held in reset as long as RST is low. RST should be held low for at least two master clock cycles. HW I Hardwired Mode Select 0 = CPU bus mode 1 = hardwired mode See Section 3 for details. T3MCLK I T3 Master Clock. A transmission-quality DS3 (44.736MHz ±20ppm, low jitter) clock should be applied at this pin. Wiring T3MCLK high forces LIUs in DS3 mode to use TCLK for receiver clock and data recovery. E3MCLK I E3 Master Clock. A transmission-quality E3 (34.368MHz ±20ppm, low jitter) clock should be applied at this pin. Wiring E3MCLK high forces LIUs in E3 mode to use TCLK for receiver clock and data recovery. STMCLK I STS-1 Master Clock. A transmission-quality STS-1 (51.840MHz ±20ppm, low jitter) clock should be applied at this pin. Wiring STMCLK high forces LIUs in STS-1 mode to use TCLK for receiver clock and data recovery. PRBSn O PRBS Detector Output. This signal reports the status of the PRBS detector. See Section 8 for further details. LLBn, RLBn I Local Loopback Select, Remote Loopback Select {LLB, RLB} = 00 = no loopback 01 = remote loopback 10 = analog local loopback 11 = digital local loopback E3Mn I E3 Mode Enable 0 = DS3 operation 1 = E3 or STS-1 operation STSn I STS-1 Mode Enable When E3M = 1, 0 = E3 operation 1 = STS-1 operation When E3M = 0, STS selects the DS3 AIS pattern. RBIN I Receiver Binary Framer-Interface Enable 0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is disabled. 1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code violations. The B3ZS/HDB3 encoder is enabled. TBIN I Transmitter Binary Framer-Interface Enable 0 = Transmitter framer interface is bipolar on the TPOS and TNEG pins. The B3ZS/HDB3 encoder is disabled. 1 = Transmitter framer interface is binary on the TDAT pin. (TNEG is ignored and should be wired low.) The B3ZS/HDB3 encoder is enabled. RCINV I Receiver Clock Invert 0 = RPOS/RDAT and RNEG/RLCV update on the falling edge of RCLK. 1 = RPOS/RDAT and RNEG/RLCV update on the rising edge of RCLK. TCINV I Transmitter Clock Invert 0 = TPOS/TDAT and TNEG are sampled on the rising edge of TCLK. 1 = TPOS/TDAT and TNEG are sampled on the falling edge of TCLK. MOT I Motorola Bus Mode Enable 0 = Intel bus mode 1 = Motorola bus mode ALE I Address Latch Enable. This signal controls a latch on the A[5:0] inputs. In nonmultiplexed bus applications, ALE should be wired high to make the latch transparent. In multiplexed bus applications, A[5:0] should be wired to D[5:0]. The falling edge of ALE latches the address. CS I Chip Select (Active Low). CS must be asserted in order to read or write internal registers. WR / R/W I Write Enable (Active Low) or Read/Write Select. In Intel bus mode (MOT = 0), WR is asserted to write internal registers. In Motorola bus mode (MOT = 1), R/W determines the type of bus

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 14 of 61 NAME I/O FUNCTION transaction, with R/W = 1 indicating a read and R/W = 0 indicating a write. RD/DS I Read Enable (Active Low) or Data Strobe (Active Low). In Intel bus mode (MOT = 0), RD is asserted to read internal registers. In Motorola bus mode (MOT = 1), the rising edge of DS writes data to internal registers. A[5:0] I Address Bus. These inputs specify the address of the internal register to be accessed. A5 is not present on the DS3152. A5 and A4 are not present on the DS3151. D[7:0] I/O Data Bus. These bidirectional lines are inputs during writes to internal registers. They are outputs during reads from internal registers. INT O Interrupt Output (Active Low, Open Drain). This pin is forced low in response to one or more unmasked, active interrupt sources within the device. INT remains low until the interrupt is serviced or masked. VDD P Positive Supply. 3.3V ±5%. All VDD signals should be wired together. VSS P Ground Reference. All V SS signals should be wired together. Table 4-E. JTAG and Test Pin Descriptions NAME I/O FUNCTION JTCLK I JTAG IEEE 1149.1 Test Serial Clock. JTCLK shifts data into JTDI on the rising edge and out of JTDO on the falling edge. If boundary scan is not used, JTCLK should be pulled high. JTDI I PU JTAG IEEE 1149.1 Test Serial-Data Input (Internal 10kΩ Pullup). Test instructions and data are clocked in on this pin on the rising edge of JTCLK. If boundary scan is not used, JTDI should be left unconnected or pulled high. JTDO O JTAG IEEE 1149.1 Test Serial-Data Output. Test instructions and data are clocked out on this pin on the falling edge of JTCLK. JTRST IPU JTAG IEEE 1149.1 Test Reset (Internal 10kΩ Pullup). This pin is used to asynchronously reset the test access port (TAP) controller. If boundary scan is not used, JTRST can be held low or high. JTMS I PU JTAG IEEE 1149.1 Test Mode Select (Internal 10kΩ Pullup). This pin is sampled on the rising edge of JTCLK and is used to place the port into the various defined IEEE 1149.1 states. If boundary scan is not used, JTMS should be left unconnected or pulled high. TEST IPU Factory Test Pin. Leave unconnected or wire high for normal operation. Note 1: Pin type I = input pin. Pin type O = output pin. Pin type P = power-supply pin. Note 2: Pin type O3 is an output that can be tri-stated. Note 3: Pin type IPU is an input with an internal 10kΩ pullup. Note 4: For pin names of the form PINn, n = LIU# = 1, 2, 3, or 4. PIN1 is on LIU 1, PIN2 is on LIU 2, etc. Note 5: Section 14 shows hardware mode and CPU bus mode pin assignments. Table 4-F. Transmitter Data Select Options TDSA TDSB E3M STS Tx MODE TRANSMIT DATA SELECTED 0 0 X X Any Normal data as input at TPOS and TNEG 0 1 0 0 DS3 0 1 1 0 E3 0 1 1 1 STS-1 Unframed all ones 0 1 0 1 DS3 DS3 AIS per ANSI T1.107 ( Figure 7-2) 1 0 X X Any Unframed 100100… pattern 1 1 1 0 E3 2 23 - 1 PRBS pattern per ITU O.151 1 1 0 X DS3 1 1 1 1 STS-1 215 - 1 PRBS pattern per ITU O.151 Note 1: This coding of the TDSA, TDSB, E3M, and STS bits allows AIS generation to be enabled by holding TDSA = 0 and changing TDSB from 0 to 1. The type of DS3 AIS signal is selected by the STS bit with E3M = 0. Note 2: If E3M and/or STS are changed when {TDSA,TDSB} ≠ 00, TDSA and TDSB must both be cleared to 0. After they are cleared, TDSA and TDSB can be configured to transmit a pattern in the new operating mode. Table 4-G. Receiver PRBS Pattern Select Options E3M STS Rx MODE RECEIVER PRBS PATTERN SELECTED 1 0 E3 2 23 - 1 PRBS pattern per ITU O.151

0 X DS3

1 1 STS-1 215 - 1 PRBS pattern per ITU O.151

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 15 of 61 5. REGISTER DESCRIPTIONS When the DS315x is configured in CPU bu s mode (HW = 0), the registers shown in Table 5-A are accessible through the CPU bus interface. All regi sters for the LIU ports are forced to their default values during an internal power-on reset or when the RST pin is driven low. Setting an LIU’s RST bit hi gh forces all registers for that LIU to their default values. All register bits marked “—” must be written 0 and ignored when read. The TEST registers must be left at their reset value of 00h for normal operation. On the DS3153, only registers for LIUs 1, 2, and 3 are available. Writes into LIU 4 address space are ignored. Reads from LIU 4 address space return all zeros. On the DS3152, address line A5 is not present, limiting the address space to the LIU 1 and 2 regist ers. On the DS3151, address lines A5 and A4 are not present, limiting the address space to the LIU 1 registers. Table 5-A. Register Map ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LIU 1 00h GCR1 E3M STS LLB RLB TDSA TDSB — RST 01h TCR1 — TBIN TCINV TJA TPD TTS TLBO — 02h RCR1 ITU RBIN RCINV RJA RPD RTS RMON RCVUD 03h SR1 — — TDM PRBS — — RLOL RLOS 04h SRL1 — — TDML PRBSL PBERL RCVL RLOLL RLOSL 05h SRIE1 — — TDMIE PRBSIE PBERIE RCVIE RLOLIE RLOSIE 06h RCVL1 RCV[7] RCV[6] RCV[5] RCV[4] RCV[3] RCV[2] RCV[1] RCV[0] 07h RCVH1 RCV[15] RCV[14] RCV[13] RCV[12] RCV[11] RCV[10] RCV[9] RCV[8] LIU 2 10h GCR2 E3M STS LLB RLB TDSA TDSB -- RST 11h TCR2 — TBIN TCINV TJA TPD TTS TLBO -- 12h RCR2 ITU RBIN RCINV RJA RPD RTS RMON RCVUD 13h SR2 — — TDM PRBS — — RLOL RLOS 14h SRL2 — — TDML PRBSL PBERL RCVL RLOLL RLOSL 15h SRIE2 — — TDMIE PRBSIE PBERIE RCVIE RLOLIE RLOSIE 16h RCVL2 RCV[7] RCV[6] RCV[5] RCV[4] RCV[3] RCV[2] RCV[1] RCV[0] 17h RCVH2 RCV[15] RCV[14] RCV[13] RCV[12] RCV[11] RCV[10] RCV[9] RCV[8] LIU 3 20h GCR3 E3M STS LLB RLB TDSA TDSB — RST 21h TCR3 — TBIN TCINV TJA TPD TTS TLBO — 22h RCR3 ITU RBIN RCINV RJA RPD RTS RMON RCVUD 23h SR3 — — TDM PRBS — — RLOL RLOS 24h SRL3 — — TDML PRBSL PBERL RCVL RLOLL RLOSL 25h SRIE3 — — TDMIE PRBSIE PBERIE RCVIE RLOLIE RLOSIE 26h RCVL3 RCV[7] RCV[6] RCV[5] RCV[4] RCV[3] RCV[2] RCV[1] RCV[0] 27h RCVH3 RCV[15] RCV[14] RCV[13] RCV[12] RCV[11] RCV[10] RCV[9] RCV[8] LIU 4 30h GCR4 E3M STS LLB RLB TDSA TDSB — RST 31h TCR4 — TBIN TCINV TJA TPD TTS TLBO — 32h RCR4 ITU RBIN RCINV RJA RPD RTS RMON RCVUD 33h SR4 — — TDM PRBS — — RLOL RLOS 34h SRL4 — — TDML PRBSL PBERL RCVL RLOLL RLOSL 35h SRIE4 — — TDMIE PRBSIE PBERIE RCVIE RLOLIE RLOSIE 36h RCVL4 RCV[7] RCV[6] RCV[5] RCV[4] RCV[3] RCV[2] RCV[1] RCV[0] 37h RCVH4 RCV[15] RCV[14] RCV[13] RCV[12] RCV[11] RCV[10] RCV[9] RCV[8] Note 1: Underlined bits are read-only; all other bits are read-write. Note 2: The registers are named REGn, where n = the LIU number (1, 2, 3, or 4). Note 3: The bit names are the same for each LIU register set.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 16 of 61 Status Register Description The status registers have two types of status bits. Real-time status bits—located in the SRn registers—indicate the state of a signal at the time it wa s read. Latched status bits—located in the SRLn registers—are set when a signal changes state (low-to-high, high-to-low, or both, depending on the bit) and cleared when written with a logic 1 value. After clearing, latched status bits remain cleared until the signal changes state again. Interrupt-enable bits— located in the SRIEn registers—control whether or not the INT pin is driven low when latched register bits are set. Figure 5-1. Status Register Logic Register Name: GCRn Register Description: Global Configuration Register Register Address: 00h, 10h, 20h, 30h Bit 7 6 5 4 3 2 1 0 Name E3M STS LLB RLB TDSA TDSB — RST Default 0 0 0 0 0 0 — 0 Bit 7: E3 Mode Enable (E3M) 0 = DS3 operation 1 = E3 or STS-1 operation Bit 6: STS-1 Mode Enable (STS) When E3M = 1, 0 = E3 operation 1 = STS-1 operation When E3M = 0, STS selects the DS3 AIS pattern ( Table 4-F). Bits 5, 4: Local Loopback, Remote Loopback Select (LLB, RLB) 00 = no loopback 01 = remote loopback 10 = analog local loopback 11 = digital local loopback Bits 3, 2: Transmitter Data Select (TDSA, TDSB). See Table 4-F for details. Bit 0: Reset (RST). When this bit is high, the digital logic of the LIU is held in reset and all registers for that LIU (except the RST bit) are forced to their default val ues. RST is cleared to 0 at power-up and when the RST pin is activated. 0 = normal operation 1 = reset LIU WR WR EVENT LATCHED STATUS REGISTER SET ON EVENT DETECT CLEAR ON WRITE LOGIC 1 INT ENABLE REGISTER SR SRL INT OTHER INT SOURCE REAL-TIME STATUS LATCHED STATUS

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 17 of 61 Register Name: TCRn Register Description: Transmitter Configuration Register Register Address: 01h, 11h, 21h, 31h Bit 7 6 5 4 3 2 1 0 Name — TBIN TCINV TJA TPD TTS TLBO — Default 0 0 0 0 0 1 0 — Bit 6: Transmitter Binary Interface Enable (TBIN) 0 = Transmitter framer interface is bipolar on th e TPOS and TNEG pins. The B3ZS/HDB3 encoder is disabled. 1 = Transmitter framer interface is binary on the TDAT pin. The B3ZS/HDB3 encoder is enabled. Bit 5: Transmitter Clock Invert (TCINV) 0 = TPOS/TDAT and TNEG are sampled on the rising edge of TCLK. 1 = TPOS/TDAT and TNEG are sampled on the falling edge of TCLK. Bit 4: Transmitter Jitter Attenuator Enable (TJA) 0 = Remove jitter attenuator from the transmitter path. 1 = Insert jitter attenuator into the transmitter path. Bit 3: Transmitter Power-Down Enable (TPD) 0 = enable the transmitter 1 = power-down the transmitter (output driver tri-stated) Bit 2: Transmitter Tri-State Enable (TTS). This bit is set to 1 on reset, which tri-states the transmitter TXP and TXN pins. The transmitter circuitry is left powered up in this mode. The TTS input pin is inverted and logically ORed with this bit. 0 = enable the transmitter output driver 1 = tri-state the transmitter output driver Bit 1: Transmitter Line Build-Out (TLBO). TLBO indicates cable length for waveform shaping in DS3 and STS-1 modes. TLBO is ignored in E3 mode. 0 = cable length ≥ 225ft 1 = cable length < 225ft

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 18 of 61 Register Name: RCRn Register Description: Receiver Configuration Register Register Address: 02h, 12h, 22h, 32h Bit 7 6 5 4 3 2 1 0 Name ITU RBIN RCINV RJA RPD RTS RMON RCVUD Default 0 0 0 0 0 1 0 0 Bit 7: ITU CV Mode (ITU). This bit controls what types of bipolar violations (BPVs) are flagged as code violations on the RLCV pin and counted in the RCV register. It also controls whether or not excessive zero (EXZ) events are flagged and counted. An EXZ event is the occurrence of a third consecutive zero (DS3 or STS-1 modes) or fourth consecutive zero (E3 mode) in a sequence of zeros. 0 = In all three modes (DS3, E3, and STS-1) BPVs that are not part of a valid codeword are flagged and counted. EXZ events are also flagged and counted. 1 = In DS3 and STS-1 modes, BPVs that are not part of valid codewords are flagged and counted. In E3 mode, BPVs that are the same polarity as the last BPV are flagged and counted. EXZ events are not flagged and counted in any mode. Bit 6: Receiver Binary Interface Enable (RBIN) 0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is disabled. 1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code violations. The B3ZS/HDB3 encoder is enabled. Bit 5: Receiver Clock Invert (RCINV) 0 = RPOS/RDAT and RNEG/RLCV are sampled on the falling edge of RCLK. 1 = RPOS/RDAT and RNEG/RLCV are sampled on the rising edge of RCLK. Bit 4: Receiver Jitter Attenuator Enable (RJA). (Note that TJA = 1 takes precedence over RJA = 1.) 0 = remove jitter attenuator from the receiver path 1 = insert jitter attenuator into the receiver path Bit 3: Receiver Power-Down Enable (RPD) 0 = enable the receiver 1 = power-down the receiver (RPOS/RDAT, RNEG/RLCV, and RCLK tri-stated) Bit 2: Receiver Tri-State Enable (RTS). This signal is set to 1 on reset, which tri-states the receiver RPOS/RDAT, RNEG/RLCV, and RCLK pins. The receiver is left powered up in this mode. The RTS pin is inverted and logically ORed with this bit. 0 = enable the receiver outputs 1 = tri-state the receiver outputs (RPOS/RDAT, RNEG/RLCV, and RCLK) Bit 1: Receiver Monitor Preamp Enable (RMON) 0 = disable the monitor preamp 1 = enable the monitor preamp Bit 0: Receive Code-Violation Counter Update (RCVUD). When this control bit transitions from low to high, the RCVLn and RCVHn registers are loaded with the current code-violation count, and the internal code-violation counter is cleared. 0→1 = Update RCV registers and clear internal code-violation counter

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 19 of 61 Register Name: SRn Register Description: Status Register Register Address: 03h, 13h, 23h, 33h Bit 7 6 5 4 3 2 1 0 Name — — TDM PRBS — — RLOL RLOS Default — — 0 0 — — 1 1 Bit 5: Transmitter Driver Monitor (TDM). This read-only status bit indicates the current state of the transmit driver monitor. 0 = the transmitter is operating normally 1 = the transmitter has a fault condition Bit 4: PRBS Detector Output (PRBS). This read-only status bit indicates the current state of the receiver’s PRBS detector. See Table 4-G for the expected PRBS pattern. 0 = in sync with expected pattern 1 = out of sync, expected pattern not detected Bit 1: Receiver Loss of Lock (RLOL). This read-only status bit indicates th e current state of the receiver clock recovery PLL. 0 = the receiver PLL is locked onto the incoming signal 1 = the receiver PLL is not locked onto the incoming signal Bit 0: Receiver Loss of Signal (RLOS). This read-only status bit indicates the current state of the receiver loss-of- signal detector. 0 = signal present 1 = loss of signal

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 20 of 61 Register Name: SRLn Register Description: Status Register Latched Register Address: 04h, 14h, 24h, 34h Bit 7 6 5 4 3 2 1 0 Name — — TDML PRBSL PBERL RCVL RLOLL RLOSL Default — — 0 0 0 0 0 0 Bit 5: Transmitter Driver Monitor Latched (TDML). This latched status bit is set to one when the TDM status bit changes state (low to high or high to low). TDML is cleared when the host processor writes a one to it and is not set again until TDM changes state again. When TDML is set, it can cause a hardware interrupt to occur if the TDMIE interrupt-enable bit is set to one. The interrupt is cleared when TDML is cleared or TDMIE is set to zero. Bit 4: PRBS Detector Output Latched (PRBSL). This latched status bit is set to one when the PRBS status bit changes state (low to high or high to low). PRBSL is clea red when the host processor writes a one to it and is not set again until PRBS changes state again. When PRBSL is set, it can cause a hardware interrupt to occur if the PRBSIE interrupt-enable bit is set to one. The interrupt is cleared when PRBSL is cleared or PRBSIE is set to zero. Bit 3: PRBS Detector Bit Error Latched (PBERL). This latched status bit is set to one when the PRBS detector is in sync and a bit error has been detecte d. PBERL is cleared when t he host processor writes a one to it and is not set again until another bit error is detected. When PBERL is set, it can cause a hardware interrupt to occur if the PBERIE interrupt-enable bit is set to one. The interrupt is cleared when PBERL is cleared or PBERIE is set to zero. Bit 2: Receiver Code Violation Latched (RCVL). This latched status bit is se t to one when the RCV status bit goes high. RCVL is cleared when the host processor writes a one to it and is not set again until RCV goes high again. When RCVL is set, it can cause a har dware interrupt to occur if the RCVIE interrupt-enable bit is set to one. The interrupt is cleared when RCVL is cleared or RCVIE is set to zero. Bit 1: Receiver Loss-of-Clock Lock Latched (RLOLL). This latched status bit is set to one when the RLOL status bit changes state (low to high or high to low). RLOLL is cleared when the host processor writes a one to it and is not set again until RLOL changes state again. When RLOLL is set, it can cause a hardware interrupt to occur if the RLOLIE interrupt-enable bit is set to one. The interrupt is cleared when RLOLL is cleared or RLOLIE is set to zero. Bit 0: Receiver Loss-of-Signal Latched (RLOSL). This latched status bit is set to one when the RLOS status bit changes state (low to high or high to low). RLOSL is clea red when the host processor writes a one to it and is not set again until RLOS changes state agai n. When RLOSL is set, it can cause a hardware interrupt to occur if the RLOSIE interrupt-enable bit is set to one. The interrupt is cleared when RLOSL is cleared or RLOSIE is set to zero.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 21 of 61 Register Name: SRIEn Register Description: Status Register Interrupt Enable Register Address: 05h, 15h, 25h, 35h Bit 7 6 5 4 3 2 1 0 Name — — TDMIE PRBSIE PBERIE RCVIE RLOLIE RLOSIE Default — — 0 0 0 0 0 0 Bit 5: Transmitter Driver Monitor Interrupt Enable (TDMIE) 0 = mask TDML interrupt 1 = enable TDML interrupt Bit 4: PRBS Detector Interrupt Enable (PRBSIE) 0 = mask PRBSL interrupt 1 = enable PRBSL interrupt Bit 3: PRBS Detector Bit-Error Interrupt Enable (PBERIE) 0 = mask PBERL interrupt 1 = enable PBERL interrupt Bit 2: Receiver Line-Code Violation Interrupt Enable (RCVIE) 0 = mask RCVL interrupt 1 = enable RCVL interrupt Bit 1: Receiver Loss-of-Clock Lock Interrupt Enable (RLOLIE) 0 = mask RLOLL interrupt 1 = enable RLOLL interrupt Bit 0: Receiver Loss-of-Signal Interrupt Enable (RLOSIE) 0 = mask RLOSL interrupt 1 = enable RLOSL interrupt Register Name: RCVLn Register Description: Receiver Code-Violation Count Register (Low Byte) Register Address: 06h, 16h, 26h, 36h Bit 7 6 5 4 3 2 1 0 Name RCV[7] RCV[6] RCV[5] RCV[4] RCV[3] RCV[2] RCV[1] RCV[0] Default 0 0 0 0 0 0 0 0 Register Name: RCVHn Register Description: Receiver Code-Violation Count Register (High Byte) Register Address: 07h, 17h, 27h, 37h Bit 7 6 5 4 3 2 1 0 Name RCV[15] RCV[14] RCV[13] RCV[12] RCV[11] RCV[10] RCV[9] RCV[8] Default 0 0 0 0 0 0 0 0 Bits 15 to 0: Receiver Code-Violation Counter Register (RCV[15:0]). The RCV registers form a 16-bit register for reading the line-code violation counter value. The re gisters are updated with the line-code violation counter value when the RCVUD control bit is toggled low to hi gh. After the RCV registers are updated, the line-code violation counter is cleared. The counter operates in two modes, depending on the setting of the ITU bit in the RCR register. See the RCR register description for details about the ITU control bit.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 22 of 61 6. RECEIVER Interfacing to the Line. The receiver can be transformer-coupled or c apacitor-coupled to the line. Typically, the receiver interfaces to the incoming coaxial cable (75 Ω) through a 1:2 step-up transformer. Figure 1-1 shows the arrangement of the transformer and ot her recommended interface components. Table 11-A specifies the required characteristics of the transformer. The receiver expect s the incoming signal to be in B3ZS- or HDB3-coded AMI format. Optional Preamp. The receiver can be used in monitoring applications, which typically have series resistors with a resistive loss of approximately 20dB. When the RMON input pin is high, the receiver compensates for this resistive loss by applying approximately 14dB of flat gain to the incoming signal before sending the signal to the AGC/equalizer block where additional flat gain is applied as needed. Automatic Gain Control (AGC) and Adaptive Equalizer. The AGC circuitry applies flat (frequency independent) gain to the incoming signal to compensate for flat losses in the transmission channel and variations in transmission power. Since the incoming signal also experiences frequen cy-dependent losses as it passes through the coaxial cable, the adaptive equalizer circuitry applies frequency-dependent gain to offset line losses and restore the signal. The AGC/equalizer circuitry automatically adapts to coaxial ca ble losses from 0 to 15dB, which translates into 0 to 380 meters (DS3), 0 to 440 meters (E3), or 0 to 360 mete rs (STS-1) of coaxial cable (AT&T 734A or equivalent). The AGC and the equalizer work simultaneously but indepen dently to supply a signal of nominal amplitude and pulse shape to the clock and data recovery block. The AGC/equalizer block automatically handles direct (0 meters) monitoring of the transmitter output signal. Clock and Data Recovery (CDR). The CDR block takes the amplified, equalized signal from the AGC/equalizer block and produces separate cl ock, positive data, and negative data signal s. The CDR requires a master clock. If the signal on the appropriate MCLK pin is toggling, the LI U selects the MCLK signal as its master clock. If the appropriate MCLK pin is wired high, the LIU uses the signal on the TCLK pin as the master clock. The appropriate MCLK is selected based on the settings of the E3M and STS mode pins or register bits. The receiver locks onto the incoming signal using a clock reco very PLL. The status of the PLL lock is indicated in the RLOL status bit. The RLOL bit is set when the difference between recovered clock frequency and MCLK frequency is greater than 7900ppm and cleared when the difference is less than 7700ppm. A change of state of the RLOL status bit can cause an interrupt on the INT pin if enabled to do so by the RLOLIE interrupt-enable bit. Note that if MCLK is not present, or MCLK is high and TCLK is not present, RLOL is not set. Loss-of-Signal (LOS) Detector. The receiver contains analog and digital LOS detectors. The analog LOS detector resides in the AGC/equalizer block. If the incoming signal level is less than a signal level approximately 24dB below nominal, analog LOS (ALOS) is declared. The ALOS signal cannot be directly examined, but when ALOS occurs the AGC/equalizer mutes the recovered data, forcing all zero s out of the data recovery circuitry and causing digital LOS (DLOS), which is indicated by the RLOS pin and the RLOS status bit. ALOS clears when the incoming signal level is greater than or equal to a signal level approximately 18dB below nominal. The digital LOS detector declares DLOS when it detects 175 ±75 consecutive zeros in the recovered data stream. When DLOS occurs, the receiver asserts the RLOS pin (hardware mode) or the RLOS status bit (CPU bus mode). DLOS is cleared when there are no EXZ occurrences over a span of 175 ±75 clock periods. An EXZ occurrence is defined as three or more consecutive zeros in the DS3 and STS-1 modes and four or more consecutive zeros in the E3 mode. The RLOS pin goes inactive (high) when the DLOS condition is cleared. In CPU bus mode, a change of the RLOS status bit can cause an interrupt on the INT pin if enabled to do so by the RLOSIE interrupt-enable bit. The requirements of ANSI T1.231 and ITU-T G.775 for DS3 LOS defects are met by the DLOS detector, which asserts RLOS when it counts 175 ±75 consecutive zeros coming out of t he CDR block and clears RLOS when it counts 175 ±75 consecutive pulse intervals without excessive zero occurrences. The requirements of ITU-T G.775 for E3 LOS defects ar e met by a combination of the ALOS detector and the DLOS detector, as follows:

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 23 of 61 For E3 RLOS Assertion: 1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or equal to a signal level approximately 24dB below nominal, and mutes the data coming out of the clock and data recovery block. (24dB below nominal in the “tolerance range” of G.775, where LOS may or may not be declared.) 2) The DLOS detector counts 175 ±75 consecutive zeros coming out of t he CDR block and asserts RLOS. (175 ±75 meets the 10 ≤ N ≤ 255 pulse-interval duration requirement of G.775.) For E3 RLOS Clear: 1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is greater than or equal to a signal level approximately 18dB below nominal, and enables data to come out of the CDR block. (18dB is in the “tolerance range” of G.775, where LOS may or may not be declared.) 2) The DLOS detector counts 175 ±75 consecutive pulse intervals wit hout EXZ occurrences and deasserts RLOS. (175 ±75 meets the 10 ≤ N ≤ 255 pulse-interval duration requirement of G.775.) The DLOS detector supports the requi rements of ANSI T1.231 for STS-1 LOS defects. At STS-1 rates, the time required for the DLOS detector to count 175 ±75 consecutive zeros falls in the range of 2.3 ≤ T≤ 100μs required by ANSI T1.231 for declaring an LOS defect. Although the time required for the DLOS detector to count 175 ±75 consecutive pulse intervals with no excessive zeros is less than the 125 μs–250μs period required by ANSI T1.231 for clearing an LOS defect, a period of this length where LOS is inactive can easily be timed in software. During LOS, the RCLK output pin is de rived from the LIU’s master clock. The ALOS detector has a longer time constant than the DLOS detector. Thus, when the inco ming signal is lost, the DLOS detector activates first (asserting the RLOS pin or bit), followed by the ALOS detector. When a signal is restored, the DLOS detector does not get a valid signal that it can qualify for no EXZ occu rrences until the ALOS detector has seen the signal rise above a signal level approximately 18dB below nominal. Framer Interface Format and the B3ZS/HDB3 Decoder. The recovered data can be output in either binary or bipolar format. To select the bipolar interface format, pull the RBIN pin low (hardware mode) or clear the RBIN configuration bit (CPU bus mode). In bipolar format, the B3ZS/HDB3 decoder is disabled and the recovered data is buffered and output on the RPOS and RNE G outputs. Received positive-polarit y pulses are indicated by RPOS = 1, while negative-polarity pulses are indicated by RNEG = 1. In bipolar interface format, the receiver simply passes on the received data and does not check it for BPV or EXZ occurrences. To select the binary interface format, pull the RBIN pin high (hardware mode) or set the RBIN configuration bit (CPU bus mode). In binary format, the B3ZS/HBD3 decoder is enabled, and the recovered data is decoded and output as a binary value on the RDAT pin. Code violations are flagged on the RLCV pin. In the discussion that follows, a valid pulse that conforms to the AMI rule is denoted as B. A BPV pulse that violates the AMI rule is denoted as V. In DS3 and STS-1 modes, B3ZS decoding is performed. RLCV is asserted during any RCLK cycle where the data on RDAT causes ones of the following code violations: ƒ Hardware mode or ITU bit set to 0 – A BPV immediately preceded by a valid pulse (B, V). – A BPV with the same polarity as the last BPV. – The third zero in an EXZ occurrence. ƒ ITU bit set to 1 – A BPV immediately preceded by a valid pulse (B, V). – A BPV with the same polarity as the last BPV. In E3 mode, HDB3 decoding is performed. RLCV is as serted during any RCLK cy cle where the data on RDAT causes one of the following code violations: ƒ Hardware mode or ITU bit set to 0 – A BPV immediately preceded by a valid pulse (B, V) or by a valid pulse and a zero (B, 0, V). – A BPV with the same polarity as the last BPV. – The fourth zero in an EXZ occurrence (only in hardware mode or when ITU = 0).

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 24 of 61 ƒ ITU bit set to 1 – A BPV with the same polarity as the last BPV. When RLCV is asserted to flag a BPV, the RDAT pin outputs a one. The state bit that tracks the polarity of the last BPV is toggled on every BPV, whether part of a valid B3ZS/HDB3 codeword or not. To support a glueless interface to a variety of neighbor ing components, the polarity of RCLK can be inverted. Normally, data is output on the RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK. To output data on these pins on the rising edge of RCLK, pull the RCINV pin high (hardware mode) or set the RCINV configuration bit (CPU bus mode). The RCLK, RPOS/RDAT, and RNEG/RLCV pins can be tri-st ated to support protection switching and redundant- LIU applications. This tri-stating capability supports system configurations where two or more LIUs are wire-ORed together and a system processor sele cts one to be active. To tri-st ate RCLK, RPOS/RDAT, and RNEG/RLCV, assert the RTS pin or the RTS configuration bit. Receive Line-Code Violation Counter. The line-code violation counter is always enabled regardless of the settings of the RBIN pin or the RBIN co nfiguration bit. The receiver has an inte rnal 16-bit saturating counter and a 16-bit latch, which the CPU can read as registers RCVH and RCVL. The value of the internal counter is latched into the RCVH/RCVL register and cleared when the receive code-violation counter update bit, RCVUD, is changed from a zero to a one. The RCVUD bit must be cleared back to a zero before a new update can occur. If there is an LCV increment pulse and an update pulse in the same clock peri od, the counter is preset to a one rather than cleared so that the LCV is not missed. The counter is increment ed when the RLCV pin flags a code violation as described in the Framer Interface Format and the B3ZS/HDB3 Decoder section. The counter saturates at 65,535 (0FFFFh) and does not roll over. Receiver Power-Down. To minimize power consumption when the re ceiver is not being used, assert the RPD configuration bit (CPU bus mode). When the receiver is powered down, the RCLK, RPOS/RDAT, and RNEG/RLCV pins are tri-stated. In addition, the RXP and RXN pins become high impedance. Receiver Jitter Tolerance. The receiver exceeds the input jitter tolerance requirements of all applicable telecommunication standards in Table 1-A. See Figure 6-1. Figure 6-1. Receiver Jitter Tolerance 10 100 1k 10k 100k 1M 60k22.3k2.3k669 0.1 1.0 300k 800k 30030 0.1 0.15 0.3 1.5E3 G.823 DS3 GR-499 Cat II DS3 GR-499 Cat I DS315x JITTER TOLERANCE

15 STS-1 GR253

FREQUENCY (Hz) JITTER TOLERANCE (UIP-P)

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 25 of 61 7. TRANSMITTER Transmit Clock. The clock applied at the TCLK input clocks in data on the TPOS/TDAT and TNEG pins. If the jitter attenuator is not enabled in the transmit path, the si gnal on TCLK is the transmit line clock and must be transmission quality (i.e., ±20ppm frequency accuracy and low jitter). If the jitter attenuator is enabled in the transmit path, the signal on TCLK can be jittery and/or periodically gapped (not exceeding 8UI), but must still have an average frequency within ±20ppm of the nominal line rate. When ena bled in the transmit path, the jitter attenuator generates the transmit line clock from the signal applied on the appropriate MCLK pin. The signal on the MCLK pin must, therefore, be a transmission-quality clock (±20ppm frequency accuracy and low jitter). The polarity of TCLK can be inverted to support gluel ess interfacing to a variety of neighboring components. Normally data is sampled on the TPOS/TDAT and TNEG pins on the rising edge of TCLK. To sample data on the falling edge of TCLK, pull the TCINV pin high (hardware mode) or set the TCINV configuration bit (CPU bus mode). Framer Interface Format and the B3ZS/HDB3 Encoder. Data to be transmitted can be input in either binary or bipolar format. To select the binary interface format, pull the TBIN pin high (hardware mode) or set the TBIN configuration bit (CPU bus mode). In binary format, the B3ZS/HBD3 encoder is enabled, and the data to be transmitted is sampled on the TDAT pin. The TNEG pin is ignored in binary interface mode and should be wired low. In DS3 and STS-1 modes, the B3ZS/HDB3 encoder operates in the B3 ZS mode. In E3 mode the encoder operates in HDB3 mode. To select the bipolar interface format, pull the TBIN pin low (hardware mode) or clear the TBIN configuration bit (CPU bus mode). In bipolar format, the B3ZS/HDB3 encode r is disabled and the data to be transmitted is sampled on the TPOS and TNEG pins. Positive-polarity pulses are indicated by TPOS = 1, wh ile negative-polarity pulses are indicated by TNEG = 1. Pattern Generation. The transmitter can generate several patterns internally, including unframed all ones (E3 AIS), 100100…, and DS3 AIS. See Figure 7-2 for the structure of the DS3 AIS signal. The TDSA and TDSB input pins (hardware mode) or the TDSA and TDSB control bits (CPU bus mode) are used to select these patterns. Table 4-F indicates the possible selections. Waveshaping, Line Build-Out, Line Driver. The waveshaping block converts the transmit clock, positive data, and negative data signals into a single AMI signal with the waveshape required for interfacing to DS3/E3/STS-1 lines. Table 7-A through Table 7-E and Figure 7-1 show the waveform template specifications and test parameters. Because DS3 and STS-1 signals must meet the waveform templates at the cross-connect through any cable length from 0 to 450ft, the waveshaping circuitr y includes a selectable LBO feature. For cable lengths of 225ft or greater, the TLBO pin (hardware mode) or the TLBO configuration bit (CPU bus mode) should be low. When TLBO is low, output pulses are driven onto the coaxial cable without any preattenuation. For cable lengths less than 225ft, TLBO should be high to enable the LBO circuitry. When TLBO is high, pulses are preattenuated by the LBO circuitry before being driven onto the coaxial cable. The LBO circuitr y provides attenuation that mimics the attenuation of 225ft of coaxial cable. The transmitter line driver can be disabled and t he TXP and TXN outputs tri-stated by asserting the TTS input or the TTS configuration bit. Powering down the transmitter th rough the TPD configuration bit (CPU bus mode) also tri-states the TXP and TXN outputs. Interfacing to the Line. The transmitter interfaces to the out going DS3/E3/STS-1 coaxial cable (75 Ω) through a 2:1 step-down transformer connected to the TXP and TXN pins. Figure 1-1 shows the arrangement of the transformer and other recommended interface components. Table 11-A specifies the required characteristics of the transformer. Transmit Driver Monitor. If the transmit driver monitor detects a faulty transmitter, it activates the TDM output (hardware mode or CPU bus mode) or sets the TDM status bit and optionally activates the INT output (CPU bus mode). When the transmitter is tri-stated, the transmit driver monitor is also disabled. The transmitter is declared to be faulty when the transmitter outputs see a load of less than ~25Ω.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 26 of 61 Transmitter Power-Down. To minimize power consumption when the transmitter is not being used, assert the TPD configuration bit (CPU bus mode only). When the transmitter is powered down, the TXP and TXN pins are put in a high-impedance state and the transmit amplifiers are powered down. Transmitter Jitter Generation (Intrinsic). The transmitter meets the jitter generation requirements of all applicable standards, with or without the jitter attenuator enabled. Transmitter Jitter Transfer. Without the jitter attenuator enabled in the transmit side, the transmitter passes jitter through unchanged. With the jitter attenuator enabled in the transmit side, the transmitter meets the jitter transfer requirements of all applicable telecommunication standards in Table 1-A. See Figure 9-1. Table 7-A. DS3 Waveform Template TIME (IN UNIT INTERVALS) NORM ALIZED AMPLITUDE EQUATION UPPER CURVE LOWER CURVE Governing Specifications: ANSI T1.102 and Bellcore GR-499. Table 7-B. DS3 Waveform Test Parameters and Limits PARAMETER SPECIFICATION Rate 44.736Mbps (±20ppm) Line Code B3ZS Transmission Medium Coaxial cable (AT&T 734A or equivalent) Test Measurement Point At the end of 0 to 450ft of coaxial cable Test Termination 75Ω (±1%) resistive Pulse Amplitude Between 0.36V and 0.85V Pulse Shape An isolated pulse (preceded by two zeros and followed by one or more zeros) falls within the curves listed in Table 7-A. Unframed All-Ones Power Level at 22.368MHz Between -1.8dBm and +5.7dBm Unframed All-Ones Power Level at 44.736MHz At least 20dB less than the power measured at 22.368MHz Pulse Imbalance of Isolated Pulses Ratio of positive and negative pulses must be between 0.90 and 1.10. Table 7-C. STS-1 Waveform Template TIME (IN UNIT INTERVALS) NORM ALIZED AMPLITUDE EQUATIONS UPPER CURVE LOWER CURVE Governing Specifications: Bellcore GR-253 and Bellcore GR-499 and ANSI T1.102.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 28 of 61 Figure 7-2. DS3 AIS Structure M 1 S u b f r a m e (1) Info Bits (1) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (1) Info Bits M 2 S u b f r a m e (1) Info Bits (1) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (1) Info Bits M 3 S u b f r a m e (0) Info Bits (1) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (1) Info Bits M 4 S u b f r a m e (0) Info Bits (1) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (1) Info Bits M 5 S u b f r a m e (0) Info Bits (1) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (1) Info Bits M 6 S u b f r a m e (1) Info Bits (1) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (1) Info Bits M 7 S u b f r a m e (0) Info Bits (1) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (0) Info Bits (1) Info Bits Note 1: X1 is transmitted first. Note 2: The 84 info bits contain the repetitive sequence 1010…, where the first 1 in the sequence immediately follows each X, P, F, C, or M bit. 8. DIAGNOSTICS PRBS Generator and Detector. Each LIU has built-in pseudorandom bit sequence (PRBS) generator and detector circuitry for physical layer testing. The device generates and detects unframed 2 15 - 1 (DS3 or STS-1) or 2 23 - 1 PRBS, according to the ITU O.151 specification. To transmit a PRBS pattern, pull the TDSA and TDSB pins high (hardware mode) or set configuration bi ts TDSA and TDSB (CPU bus mode). As Table 4-F shows, the PRBS generator automatically generates 215 - 1 for DS3 and STS-1 modes and 223 - 1 for E3 mode. The PRBS detector, which is always enabled (Table 4-G), reports its status through the PRBS output pin (hardware and CPU bus modes) or through the PRBS and PBER status bits (CPU bus mode). When the PRBS detector is out of synchronization, the PRBS pin is forced high. When the detector syncs to an incoming PRBS pattern, the PRBS pin is driven low, then pulses high, synchronous with RCLK, for each bit error detected. See Figure 8-1 and Figure 8-2 for details. In CPU bus mode, the PRBS status bit is se t to one when the detector is out of synchronization and set to zero when the detector syncs to an incoming PRBS pattern. A change of state of the PRBS bit can cause an interrupt on the INT pin if the PRBSIE interrupt-enable bit is set to one. A pattern bit error can also cause an interrupt if the PBERIE interrupt-enable bit is set to one. The PRBS detecto r also declares sync in the presence of an incoming all-ones pattern.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 30 of 61 the JA must take its master clock from the MCLK pin. T he clock and data recovery block also uses the selected master clock. The JA has a loop bandwidth of master_c lock / 2,058,874 (see corner frequencies in Figure 9-1 ). The JA attenuates jitter at frequencies higher than the loop band width, while allowing jitter (and wander) at lower frequencies to pass through relatively unaffected. Figure 9-1. Jitter Attenuation/Jitter Transfer 10. RESET LOGIC There are four sources for reset: an internal power-on reset (POR) circuit, the reset pin RST, the JTAG reset pin JTRST, and the RST bit in each LIU’s global configuration regi ster (GCR). The chip is divided into three zones for reset: the digital logic, the analog circuits, and the JTAG l ogic. The digital logic includes the status and control registers, the B3ZS/HDB3 encoder and decoder, the PRBS generator and detec tor, and the LOS detect logic. The analog circuits include clock and data recovery, jitter attenuator, and transmit waveform generation. The JTAG logic consists of the common boundary scan controller and the boundary scan cells at each pin. The POR circuit resets the digital logic, analog circuits, and JTAG logic zones. The RST pin resets the digital logic and the analog circuits but not the JTAG logic. The JTRST pin resets only the JTAG logic. Each LIU’s RST register bit resets the digital logic for that LIU, including resetting the LIU’s registers to the default state (except for the RST bit). The POR signal and RST pin require an active master clock source for the LIU to properly reset. 10 100 1k 10k 100k 1M 21.7Hz (DS3) 16.7Hz (E3) 25.2Hz (STS-1) 1k -30 -20 -10 E3 [TBR24 (1997)] FREQUENCY (Hz) JITTER ATTENUATION (dB) CATEGORY I DS315x TYPICAL RECEIVER JITTER TRANSFER WITH JITTER ATTENUATOR DISABLED >150k DS315x DS3/E3/STS-1 MINIMUM JITTER ATTENUATION WITH JITTER ATTENUATOR ENABLED 40Hz CATEGORY I 27Hz STS-1 [GR-253 (1999)] CATEGORY II 40k 59.6k CATEGORY II

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 31 of 61 11. TRANSFORMERS Table 11-A. Transformer Characteristics PARAMETER VALUE Turns Ratio 1:2ct ±2% Bandwidth 75Ω 0.250MHz to 500MHz (typ) Primary Inductance 19μH (min) Leakage Inductance 0.150μH (max) Interwinding Capacitance 10pF (max) Isolation Voltage 1500V RMS (min) Table 11-B. Recommended Transformers MANUFACTURER NO. OF TRANSFORMERS PART TEMP RANGE PIN-PACKAGE/ SCHEMATIC

1 PE-65968 0°C to +70°C 6 SMT

1 PE-65969 0°C to +70°C 6 Thru-Hole

8 T3049 0°C to +70°C 32 SMT

1 TG07-0206NS 0°C to +70°C 6 SMT

1 TD07-0206NE 0°C to +70°C 6 DIP

Note: Table subject to change. Industrial temper ature range and other multiples (dual, quad) are also available. Contact the manufac turers for

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 32 of 61 12. JTAG TEST ACCESS PO RT AND BOUNDARY SCAN

12.1 JTAG Description

The DS315x LIUs suppor t the standard inst ruction codes SAMPLE/PRELOA D, BYPASS, and EXTEST. Optional public instructions included ar e HIGHZ, CLAMP, and IDCODE. Figure 12-1 features a block diagram. The LIUs contain the following items, which meet the requirement s set by the IEEE 1149.1 Standa rd Test Access Port and Boundary Scan Architecture: Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register The TAP has the necessary interface pins, namely JTCLK, JTRST, JTDI, JTDO, and JTMS. Details on these pins can be found in Section 4. Details about the boundary scan architecture and the TAP can be found in IEEE 1149.1- 1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. Figure 12-1. JTAG Block Diagram BOUNDARY SCAN REGISTER IDENTIFICATION REGISTER BYPASS REGISTER INSTRUCTION REGISTER TEST ACCESS PORT CONTROLLER MUX SELECT TRI-STATE JTDI 10k JTMS 10k JTCLK JTRST 10k JTDO

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 33 of 61

12.2 JTAG TAP Controller State Machine Description

This section discusses the operation of the TAP controlle r state machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. Each of the states denoted in Figure 12-2 are described in the following pages. Figure 12-2. JTAG TAP Controller State Machine Test-Logic-Reset. Upon device power-up, the TAP c ontroller starts in the Test-Logi c-Reset state. The instruction register contains the IDCODE instruction. All system logic on the device operates normally. Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The instruction and test registers remain idle. Select-DR-Scan. All test registers retain their pr evious state. With JTMS low, a rising edge of JTCLK moves the controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the Select- IR-SCAN state. Capture-DR. Data can be parallel loaded into the test data regi sters selected by the cu rrent instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or to the Exit1-DR state if JTMS is high. Test-Logic-Reset Run-Test/Idle Select DR-Scan Capture-DR Shift-DR Exit1- DR 1 Pause-DR Exit2-DR Update-DR Select IR-Scan Capture-IR Shift-IR Exit1-IR 1 Pause-IR Exit2-IR Update-IR

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 34 of 61 Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO and shifts data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is not placed in the serial path, it maintains its previous state. Exit1-DR. While in this state, a rising edge on JTCLK with JT MS high puts the controller in the Update-DR state, which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Pause-DR state. Pause-DR. Shifting of the test registers is halted while in this state. All test register s selected by the current instruction retain their previous stat e. The controller remains in this state while JTMS is low. A rising edge on JTCLK with JTMS high puts the controller in the Exit2-DR state. Exit2-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state and terminates the scanning process. A rising edge on JT CLK with JTMS low puts the controller in the Shift-DR state. Update-DR. A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of the test registers into the data output latches. This pr events changes at the parallel output because of changes in the shift register. A rising edge on JTCLK with JTMS low pu ts the controller in the Run-Test-Idle state. With JTMS high, the controller enters the Select-DR-Scan state. Select-IR-Scan. All test registers retain their previous state. The instruction register remains unchanged during this state. With JTMS low, a rising edge on JTCLK moves the c ontroller into the Capture-IR state and initiates a scan sequence for the instruction register. JTMS high duri ng a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state. Capture-IR. The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is hi gh on the rising edge of JTCL K, the controller enters the Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller enters the Shift-IR state. Shift-IR. In this state, the instruction regi ster’s shift register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK toward the seri al output. The parallel register and the test registers remain at their previous states. A rising edge on JTCLK with JTMS high moves the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS low keeps the contro ller in the Shift-IR state, while moving data one stage through the instruction shift register. Exit1-IR. A rising edge on JTCLK with JTMS low puts the controll er in the Pause-IR state. If JTMS is high on the rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process. Pause-IR. Shifting of the instruction register is halted tempor arily. With JTMS high, a rising edge on JTCLK puts the controller in the Exit2-IR state. Th e controller remains in the Pause-IR state if JTMS is low during a rising edge on JTCLK. Exit2-IR. A rising edge on JTCLK with JTMS high puts the cont roller in the Update-IR state. The controller loops back to the Shift-IR state if JTMS is low during a rising edge of JTCLK in this state. Update-IR. The instruction shifted into the instruction shift r egister is latched into the parallel output on the falling edge of JTCLK as the controller enters th is state. Once latched, this instruct ion becomes the current instruction. A rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state. Wi th JTMS high, the controller enters the Select-DR-Scan state.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 35 of 61

12.3 JTAG Instruction Regi ster and Instructions

The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low sh ifts data one stage toward the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to the Update- IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction parallel output. Table 12-A shows the instructions supported by the DS315x and their respective operational binary codes. Table 12-A. JTAG Instruction Codes INSTRUCTIONS SELECTED REGISTER INSTRUCTION CODES SAMPLE/PRELOAD Boundary Scan 010 BYPASS Bypass 111 EXTEST Boundary Scan 000 CLAMP Bypass 011 HIGHZ Bypass 100 IDCODE Device Identification 001 SAMPLE/PRELOAD. SAMPLE/RELOAD is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the device’ s normal operation by using the C apture-DR state. SAMPLE/PRELOAD also allows the DS315x to shift data into the boundary scan register through JTDI using the Shift-DR state. EXTEST. EXTEST allows testing of the interconnections to t he device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled through the Update-IR state, the parallel outputs of the digital output pins are driven. The boundary sc an register is connected between JTDI and JTDO. The Capture-DR samples all digital inputs into the boundary scan register. BYPASS. When the BYPASS instruction is latched into the paralle l instruction register, JTDI connects to JTDO through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device’s normal operation. IDCODE. When the IDCODE instruction is latched into the pa rallel instruction register , the identification test register is selected. The device identif ication code is loaded into the identifi cation register on the rising edge of JTCLK, following entry into the Capture-DR state. Shift-DR can be used to shif t the identification code out serially through JTDO. During Test-Logic-Reset, the identification c ode is forced into the instruction register’s parallel output. HIGHZ. All digital outputs are placed into a high-impedance st ate. The bypass register is connected between JTDI and JTDO. CLAMP. All digital output pins output data from the boundar y scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs do not change during the CLAMP instruction. Table 12-B. JTAG ID Code PART REVISION DEVICE CODE MANUFACTURER CODE REQUIRED DS3154 Consult factory 0000000000110011 00010100001 1 DS3153 Consult factory 0000000000110010 00010100001 1 DS3152 Consult factory 0000000000110000 00010100001 1 DS3151 Consult factory 0000000000100000 00010100001 1

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 36 of 61

12.4 JTAG Test Registers

IEEE 1149.1 requires a minimum of two te st registers—the bypass register and the boundary sc an register. An optional test register, the identification register, has been included in the device design. It is used with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller. Bypass Register. This single 1-bit shift register, used with the BYPASS, CLAMP, and HIGHZ instructions, provides a short path between JTDI and JTDO. Boundary Scan Register. This register contains a shift register path and a latched parallel output for control cells Identification Register. This register contains a 32-bit shift regi ster and a 32-bit latched parallel output. It is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 37 of 61 13. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to VSS (except VDD) -0.3V to +5.5V Supply Voltage Range (VDD) with Respect to VSS -0.3V to +3.63V Ambient Operating Temperature Range -40°C to +85°C Junction Operating Temperature Range -40°C to +125°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JE DEC J-STD-020A Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Ambient ope rating temperature range when device is mounted on a four-layer JEDEC test board with no airflow. Note: The typical values listed in Tables 13-A through 13-I are not production tested. Table 13-A. Recommended DC Operating Conditions (TA = -40°C to +85°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Logic 1 V IH 2.0 5.5 V Logic 0 V IL -0.3 +0.8 V Supply Voltage V DD 3.135 3.3 3.465 V Table 13-B. DC Characteristics (VDD = 3.3V ±5%, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DS3151 75 100 DS3152 150 200 DS3153 225 300 Supply Current (Note 1) I DD DS3154 300 400 mA DS3151 65 80 DS3152 120 150 DS3153 180 225 Supply Current, Transmitters Tri-Stated (All TTSn Low) (Note 2) IDDTTS DS3154 240 300 mA Power-Down Current (All TPD, RPD Control Bits High) IDDPD DS315x (Note 2) 55 70 mA Lead Capacitance C IO 7 pF Input Leakage I IL (Note 3) -50 +10 μA Output Leakage (when High-Z) I LO (Note 3) -10 +10 μA Output Voltage (IO = -4.0mA) V OH 2.4 V DD V Output Voltage (IO = +4.0mA) V OL 0 0.4 V Note 1: TCLKn = STMCLK = 51.84MHz; TXPn/TXNn driving all ones into 75Ω resistive loads; analog loopback enabled; all other inputs at VDD or grounded; all other outputs open. Note 2: TCLKn = STMCLK = 51.84MHz; other inputs at VDD or grounded; digital outputs left open circuited. Note 3: 0V < VIN < VDD.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 38 of 61 Table 13-C. Framer Interface Timing (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Figure 13-1 and Figure 13-2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS (Note 4) 22.4 (Note 5) 29.1 RCLK/TCLK Clock Period t1 (Note 6) 19.3 ns RCLK Duty Cycle t2/t1, t3/t1 (Notes 7, 8) 45 50 55 % TCLK Duty Cycle t2/t1, t3/t1 (Note 8) 30 70 % MCLK Duty Cycle t2/t1, t3/t1 (Note 8) 30 70 % TPOS/TDAT, TNEG to TCLK Setup Time t4 (Notes 8, 9) 2 ns TPOS/TDAT, TNEG Hold Time t5 (Notes 8, 9) 2 ns RCLK to RPOS/RDAT, RNEG/RLCV, and PRBS Value Change t6 (Notes 7, 8, 10) 2 6 ns RCLK Rise and Fall Time t7 (Notes 8, 11) 5 ns TCLK Rise and Fall Time t8 (Notes 8, 12) 5 ns Note 4: DS3 mode. Note 5: E3 mode. Note 6: STS-1 mode. Note 7: Outputs loaded with 25pF, measured at 50% threshold. Note 8: Not tested during production test. Note 9: When TCINV = 0, TPOS/TDAT and TNEG are sampled on the rising edge of TCLK. When TCINV = 1, TPOS/TDAT and TNEG are sampled on the falling edge of TCLK. Note 10: When RCINV = 0, RPOS/RDAT and RNEG/RLCV are updated on the falling edge of RCLK. When RCINV = 1, RPOS/RDAT and RNEG/RLCV are updated on the rising edge of RCLK. Note 11: Outputs loaded with 25pF, measured between VOL (max) and VOH (min). Note 12: Measured between VIL (max) and VIH (min). Figure 13-1. Transmitter Framer Interface Timing Diagram TCLK (INVERTED) TPOS/TDAT, TNEG t4 t5 t2 t3 TCLK (NORMAL)

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 39 of 61 Figure 13-2. Receiver Framer Interface Timing Diagram Table 13-D. Receiver Input Characteristics—DS3 and STS-1 Modes (VDD = 3.3V ±5%, TA = -40°C to +85°C.) PARAMETER MIN TYP MAX UNITS Receive Sensitivity (Length of Cable) 900 1200 ft Signal-to-Noise Ratio, Interfering Signal Test (Notes 13, 14) 10 Input Pulse Amplitude, RMON = 0 (Notes 14, 15) 1000 mVpk Input Pulse Amplitude, RMON = 1 (Note 14, 15) 200 mVpk Analog LOS Declare, RMON = 0 (Note 16) -24 dB Analog LOS Clear, RMON = 0 (Note 16) -21 dB Analog LOS Declare, RMON = 1 (Note 16) -38 dB Analog LOS Clear, RMON = 1 (Note 16) -35 dB Intrinsic Jitter Generation (Note 14) 0.03 UI P-P Table 13-E. Receiver Input Characteristics—E3 Mode (VDD = 3.3V ±5%, TA = -40°C to +85°C.) PARAMETER MIN TYP MAX UNITS Receive Sensitivity (Length of Cable) 900 1200 ft Signal-to-Noise Ratio, Interfering Signal Test (Notes 13, 14) 12 Input Pulse Amplitude, RMON = 0 (Notes 14, 15) 1300 mVpk Input Pulse Amplitude, RMON = 1 (Notes 14, 15) 260 mVpk Analog LOS Declare, RMON = 0 (Note 16) -24 dB Analog LOS Clear, RMON = 0 (Note 16) -21 dB Analog LOS Declare, RMON = 1 (Note 16) -38 dB Analog LOS Clear, RMON = 1 (Note 16) -35 dB Intrinsic Jitter Generation (Note 14) 0.03 UI P-P Note 13: An interfering signal (2 - 1 PRBS for DS3/STS-1, 2 - 1 PRBS for E3, B3ZS/HDB3 encoded, compliant waveshape, nominal bit rate) is added to the wanted signal. The combined si gnal is passed through 0 to 900ft of c oaxial cable and presented to the DS3154 receiver. This spec indicates the lowest signal-to-noise ratio that results in a bit error ratio <10 Note 14: Not tested during production test. Note 15: Measured on the line side (i.e., the BNC connecto r side) of the 1:2 receive transformer ( Figure 1-1). During measurement, incoming data traffic is unframed 2 - 1 PRBS for DS3/STS-1 and unframed 2 - 1 PRBS for E3. Note 16: With respect to nominal 800mVpk signal for DS3/STS-1 and nominal 1000mVpk signal for E3. RCLK (NORMAL) RPOS/RDAT, RNEG/RLCV t2 t3 RCLK (INVERTED)

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 40 of 61 Table 13-F. Transmitter Output Characteristics—DS3 and STS-1 Modes (VDD = 3.3V ±5%, TA = -40°C to +85°C.) PARAMETER MIN TYP MAX UNITS DS3 Output Pulse Amplitude, TLBO = 0 (Note 17) 700 800 900 mVpk DS3 Output Pulse Amplitude, TLBO = 1 (Note 17) 520 700 800 mVpk STS-1 Output Pulse Amplitude, TLBO = 0 (Note 17) 700 800 1100 mVpk STS-1 Output Pulse Amplitude, TLBO = 1 (Note 17) 520 700 850 mVpk Ratio of Positive and Negative Pulse-Peak Amplitudes 0.9 1.1 DS3 Unframed All-Ones Power Level at 22.368MHz, 3kHz Bandwidth -1.8 +5.7 dBm DS3 Unframed All-Ones Power Level at 44.736MHz vs. Power Level at 22.368MHz, 3kHz Bandwidth -20 dB Intrinsic Jitter Generation (Note 18) 0.02 0.05 UI P-P Table 13-G. Transmitter Output Characteristics—E3 Mode (VDD = 3.3V ±5%, TA = -40°C to +85°C.) PARAMETER MIN TYP MAX UNITS Output Pulse Amplitude (Note 17) 900 1000 1100 mVpk Pulse Width 14.55 ns Ratio of Positive and Negative Pulse Amplitudes (at Centers of Pulses) 0.95 1.05 Ratio of Positive and Negative Pulse Widths (at Nominal Half Amplitude) 0.95 1.05 Intrinsic Jitter Generation (Note 18) 0.02 0.05 UI P-P Note 17: Measured on the line side (i.e., the BNC connector side) of the 2:1 transmit transformer (Figure 1-1). Note 18: Measured with jitter-free clock applied to TCLK and a bandpass jitter filter with 10Hz and 800kHz cutoff frequencies. Not tested during production test. Table 13-H. CPU Bus Timing (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Figure 13-3 and Figure 13-4) PARAMETER SYMBOL MIN TYP MAX UNITS Setup Time for A[5:0] Valid to CS Active (Notes 19, 20) t1 0 ns Setup Time for CS Active to RD, WR, or DS Active t2 0 ns Delay Time from RD or DS Active to D[7:0] Valid t3 65 ns Hold Time from RD or WR or DS Inactive to CS Inactive t4 0 ns Delay from CS or RD or DS Inactive to D[7:0] Invalid or Tri-State (Note 21) t5 2 20 ns Wait Time from WR or DS Active to Latch D[7:0] t6 65 ns D[7:0] Setup Time to WR or DS Inactive t7 10 ns D[7:0] Hold Time from WR or DS Inactive t8 2 ns A[5:0] Hold Time from WR or RD or DS Inactive t9 5 ns RD, WR, or DS Inactive Time t10 75 ns Muxed Address Valid to ALE Falling (Note 22) t11 10 ns Muxed Address Hold Time (Note 22) t12 10 ns ALE Pulse Width (Note 22) t13 30 ns Setup Time for ALE High or Muxed Address Valid to CS Active (Note 22) t14 0 ns Note 19: D[7:0] loaded with 50pF when tested as outputs. Note 20: If a gapped clock is applied on TCLK and diagnostic loopback is enabled, read cycle time must be extended by the length of the largest TCLK gap. Note 21: Not tested during production test. Note 22: In nonmultiplexed bus applications (Figure 13-3), ALE should be wired high. In multiplexed bus applications (Figure 13-4), A[5:0] should be wired to D[5:0] and the falling edge of ALE latches the address.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 41 of 61 Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed) ADDRESS VALID DATA VALID A[5:0] D[7:0] WR CS RD t2 t3 t4 t10 INTEL READ CYCLE ADDRESS VALID A[5:0] D[7:0] RD CS WR t2 t6 t4 t7 t8 t10 INTEL WRITE CYCLE

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 42 of 61 Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed)(continued) ADDRESS VALID DATA VALID A[5:0] D[7:0] R/W CS DS t2 t3 t4 t10 MOTOROLA READ CYCLE ADDRESS VALID A[5:0] D[7:0] R/W CS DS t2 t6 t4 t7 t8 t10 MOTOROLA WRITE CYCLE

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 43 of 61 Figure 13-4. CPU Bus Timing Diagram (Multiplexed) ADDRESS VALID DATA VALID A[5:0] D[7:0] WR CS RD t2 t3 t4 t10 ALE t11 t12 t13 t14 t14 NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST. NOTE: TO AVOID BUS CONTENTION, STOP DRIVING A[5:0] BEFORE RD GOES LOW. INTEL READ CYCLE D[7:0] RD CS WR t2 t6 t4 t7 t8 t10 ADDRESS VALID A[5:0] ALE t11 t12 t13 t14 t14 NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST. INTEL WRITE CYCLE

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 44 of 61 Figure 13-4. CPU Bus Timing Diagram (Multiplexed) (continued) MOTOROLA READ CYCLE DATA VALID D[7:0] R/W CS DS t2 t3 t4 t10 ADDRESS VALID A[5:0] ALE t11 t12 t13 t14 t14 NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST. NOTE: TO AVOID BUS CONTENTION, STOP DRIVING A[5:0] BEFORE RD GOES LOW. D[7:0] R/W A[5:0] CS DS t2 t6 t4 t7 t8 t10 ADDRESS VALID ALE t11 t12 t13 t14 t14 MOTOROLA WRITE CYCLE NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 45 of 61 Table 13-I. JTAG Interface Timing (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Figure 13-5) PARAMETER SYMBOL MIN TYP MAX UNITS JTCLK Clock Period t1 1000 ns JTCLK Clock High/Low Time (Note 23) t2/t3 50 500 ns JTCLK to JTDI, JTMS Setup Time t4 50 ns JTCLK to JTDI, JTMS Hold Time t5 50 ns JTCLK to JTDO Delay t6 2 50 ns JTCLK to JTDO High-Z Delay (Note 24) t7 2 50 ns JTRST Width Low Time t8 100 ns Note 23: Clock can be stopped high or low. Note 24: Not tested during production test. Figure 13-5. JTAG Timing Diagram JTDO t4 t5 t2 t3 JTDI, JTMS, JTRST JTRST JTCLK

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 46 of 61 14. PIN ASSIGNMENTS Table 14-A lists pin assignments sorted by signal name. Table 14-B lists pin assignments sorted by pin number. DS3154 has all four LIUs. DS3153 has only LIUs 1, 2, and 3. DS3152 has only LIUs 1 and 2. DS3151 has only LIU 1. Figure 14-1 through Figure 14-8 show pinouts for the four devices in both hardware and CPU bus modes. Table 14-A. Pin Assignments Sorted by Signal Name PIN NAME HARDWARE MODE CPU BUS MODE LIU 1 LIU 2 LIU 3 LIU 4 A[0] N Y K6 A[1] N Y L6 A[2] N Y K7 A[3] N Y L7 A[4] N Y K8 A[5] N Y L8 ALE N Y C7 CS N Y B7 D[0] N Y E3 D[1] N Y F2 D[2] N Y F3 D[3] N Y G2 D[4] N Y G3 D[5] N Y H2 D[6] N Y H3 D[7] N Y J3 E3MCLK Y Y E12 E3Mn Y N F3 G10 C7 K6 HIZ Y Y J8 HW Y Y E9 INT N Y C5 JTCLK Y Y E4 JTDI Y Y H4 JTDO Y Y J4 JTMS Y Y D5 JTRST Y Y D4 LLBn Y N B5 L8 E11 H2 MOT N Y C6 PRBSn Y Y B1 L12 A11 M2 RBIN Y N D9 RCINV Y N J9 RCLKn Y Y C1 K12 A10 M3 RD N Y B6 RJAn Y N B4 L9 D11 J2 RLBn Y N C5 K8 E10 H3 RLOSn Y Y A1 M12 A12 M1 Table 14-A. Pin Assignments Sorted by Signal Name (continued)

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 47 of 61 PIN NAME HARDWARE MODE CPU MODE LIU 1 LIU 2 LIU 3 LIU 4 RNEGn Y Y C3 K10 C10 K3 RPOSn Y Y C2 K11 B10 L3 RST Y Y H1 RTSn Y Y B2 L11 B11 L2 RXNn Y Y A2 M11 B12 L1 RXPn Y Y A3 M10 C12 K1 STMCLK Y Y M8 STSn Y N F2 G11 B7 L6 T3MCLK Y Y A5 TBIN Y N D8 TCINV Y N H9 TCLKn Y Y E1 H12 A8 M5 TDMn Y Y D3 J10 C9 K4 TDSAn Y N G2 F11 B6 L7 TDSBn Y N G3 F10 C6 K7 TEST Y Y J5 TJAn Y N C4 K9 D10 J3 TLBOn Y N E3 H10 C8 K5 TNEGn Y Y D2 J11 B9 L4 TPOSn Y Y D1 J12 A9 M4 TTSn Y Y E2 H11 B8 L5 TXNn Y Y G1 F12 A6 M7 TXPn Y Y F1 G12 A7 M6 VDD Y Y D6, E5, E6, F4, F5, F6 , G7, G8, G9, H7, H8, J7 VSS Y Y D7, E7, E8, F7, F8, F9 , G4, G5, G6, H5, H6, J6 WR N Y B5

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 48 of 61 Table 14-B. Pin Assignments Sorted by Pin Number DS3154 DS3153 DS3152 DS3151 PIN HARDWARE MODE CPU BUS MODE HARDWARE MODE CPU BUS MODE HARDWARE MODE CPU BUS MODE HARDWARE MODE CPU BUS MODE A1 RLOS1 RLOS1 RLOS1 RLOS1 RLOS1 RLOS1 RLOS1 RLOS1 A2 RXN1 RXN1 RXN1 RXN1 RXN1 RXN1 RXN1 RXN1 A3 RXP1 RXP1 RXP1 RXP1 RXP1 RXP1 RXP1 RXP1 A5 T3MCLK T3MCLK T3MCLK T3MCLK T3MCLK T3MCLK T3MCLK T3MCLK B1 PRBS1 PRBS1 PRBS1 PRBS1 PRBS1 PRBS1 PRBS1 PRBS1 B2 RTS1 RTS1 RTS1 RTS1 RTS1 RTS1 RTS1 RTS1 B5 LLB1 WR LLB1 WR LLB1 WR LLB1 WR B6 TDSA3 RD TDSA3 RD N.C. RD N.C. RD B7 STS3 CS STS3 CS N.C. CS N.C. CS C1 RCLK1 RCLK1 RCLK1 RCLK1 RCLK1 RCLK1 RCLK1 RCLK1 C2 RPOS1 RPOS1 RPOS1 RPOS1 RPOS1 RPOS1 RPOS1 RPOS1 C3 RNEG1 RNEG1 RNEG1 RNEG1 RNEG1 RNEG1 RNEG1 RNEG1 C5 RLB1 INT RLB1 INT RLB1 INT RLB1 INT C6 TDSB3 MOT TDSB3 MOT N.C. MOT N.C. MOT C7 E3M3 ALE E3M3 ALE N.C. ALE N.C. ALE D1 TPOS1 TPOS1 TPOS1 TPOS1 TPOS1 TPOS1 TPOS1 TPOS1 D2 TNEG1 TNEG1 TNEG1 TNEG1 TNEG1 TNEG1 TNEG1 TNEG1 D3 TDM1 TDM1 TDM1 TDM1 TDM1 TDM1 TDM1 TDM1 D4 JTRST JTRST JTRST JTRST JTRST JTRST JTRST JTRST D5 JTMS JTMS JTMS JTMS JTMS JTMS JTMS JTMS D6 V DD V DD VDD VDD VDD VDD VDD VDD D7 V SS V SS VSS VSS VSS VSS VSS VSS E1 TCLK1 TCLK1 TCLK1 TCLK1 TCLK1 TCLK1 TCLK1 TCLK1 E2 TTS1 TTS1 TTS1 TTS1 TTS1 TTS1 TTS1 TTS1 E3 TLBO1 D0 TLBO1 D0 TLBO1 D0 TLBO1 D0 E4 JTCLK JTCLK JTCLK JTCLK JTCLK JTCLK JTCLK JTCLK E5 V DD VDD VDD VDD VDD VDD VDD VDD E6 V DD VDD VDD VDD VDD VDD VDD VDD E7 V SS VSS VSS VSS VSS VSS VSS VSS E8 V SS VSS VSS VSS VSS VSS VSS VSS E9 HW HW HW HW HW HW HW HW

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 49 of 61 DS3154 DS3153 DS3152 DS3151 PIN HARDWARE MODE CPU BUS MODE HARDWARE MODE CPU BUS MODE HARDWARE MODE CPU BUS MODE HARDWARE MODE CPU BUS MODE E12 E3MCLK E3MCLK E3MCLK E3MCLK E3MCLK E3MCLK E3MCLK E3MCLK F1 TXP1 TXP1 TXP1 TXP1 TXP1 TXP1 TXP1 TXP1 F2 STS1 D1 STS1 D1 STS1 D1 STS1 D1 F3 E3M1 D2 E3M1 D2 E3M1 D2 E3M1 D2 F4 V DD VDD VDD VDD VDD VDD VDD VDD F5 V DD VDD VDD VDD VDD VDD VDD VDD F6 V DD VDD VDD VDD VDD VDD VDD VDD F7 V SS VSS VSS VSS VSS VSS VSS VSS F8 V SS VSS VSS VSS VSS VSS VSS VSS F9 V SS VSS VSS VSS VSS VSS VSS VSS F12 TXN2 TXN2 TXN2 TXN2 TXN2 TXN2 N.C. N.C. G1 TXN1 TxN1 TXN1 TXN1 TXN1 TXN1 TXN1 TXN1 G2 TDSA1 D3 TDSA1 D3 TDSA1 D3 TDSA1 D3 G3 TDSB1 D4 TDSB1 D4 TDSB1 D4 TDSB1 D4 G4 V SS VSS VSS VSS VSS VSS VSS VSS G5 V SS VSS VSS VSS VSS VSS VSS VSS G6 V SS VSS VSS VSS VSS VSS VSS VSS G7 V DD VDD VDD VDD VDD VDD VDD VDD G8 V DD VDD VDD VDD VDD VDD VDD VDD G9 V DD VDD VDD VDD VDD VDD VDD VDD G12 TXP2 TXP2 TXP2 TXP2 TXP2 TXP2 N.C. N.C. H1 RST RST RST RST RST RST RST RST H4 JTDI JTDI JTDI JTDI JTDI JTDI JTDI JTDI H5 V SS V SS VSS VSS VSS VSS VSS VSS H6 V SS V SS VSS VSS VSS VSS VSS VSS H7 V DD V DD VDD VDD VDD VDD VDD VDD H8 V DD V DD VDD VDD VDD VDD VDD VDD H11 TTS2 TTS2 TTS2 TTS2 TTS2 TTS2 N.C. N.C. H12 TCLK2 TCLK2 TCLK2 TCLK 2 TCLK2 TCLK2 N.C. N.C. J4 JTDO JTDO JTDO JTDO JTDO JTDO JTDO JTDO J5 TEST TEST TEST TEST TEST TEST TEST TEST J6 V SS V SS V SS V SS V SS V SS V SS V SS J7 V DD V DD VDD VDD VDD VDD VDD VDD J8 HIZ HIZ HIZ HIZ HIZ HIZ HIZ HIZ J9 RCINV N.C RCINV N. C RCINV N.C RCINV N.C J10 TDM2 TDM2 TDM2 TDM2 TDM2 TDM2 N.C. N.C. J11 TNEG2 TNEG2 TNEG2 TNEG 2 TNEG2 TNEG2 N.C. N.C. J12 TPOS2 TPOS2 TPOS2 TPOS2 TPOS2 TPOS2 N.C. N.C. K8 RLB2 A4 RLB2 A4 RLB2 A4 N.C. N.C.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 50 of 61 DS3154 DS3153 DS3152 DS3151 PIN HARDWARE MODE CPU BUS MODE HARDWARE MODE CPU BUS MODE HARDWARE MODE CPU BUS MODE HARDWARE MODE CPU BUS MODE K10 RNEG2 RNEG2 RNEG2 RNEG2 RNEG2 RNEG2 N.C. N.C. K11 RPOS2 RPOS2 RPOS2 RPOS 2 RPOS2 RPOS2 N.C. N.C. K12 RCLK2 RCLK2 RCLK2 RCLK2 RCLK2 RCLK2 N.C. N.C. L11 RTS2 RTS2 RTS2 RTS2 RTS2 RTS2 N.C. N.C. L12 PRBS2 PRBS2 PRBS2 PRBS2 PRBS2 PRBS2 N.C. N.C. M8 STMCLK STMCLK STMCLK STMCLK STMCLK STMCLK STMCLK STMCLK M10 RXP2 RXP2 RXP2 RXP2 RXP2 RXP2 N.C. N.C. M11 RXN2 RXN2 RXN2 RXN2 RXN2 RXN2 N.C. N.C. M12 RLOS2 RLOS2 RLOS2 RLOS2 RLOS2 RLOS2 N.C. N.C.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 51 of 61 Figure 14-1. DS3151 Hardware Mode Pin Assignment RLOS1 RXN1 RXP1 RMON1 T3MCLK N.C. N.C. N.C. N.C. A10 N.C. A11 N.C. A12 N.C. PRBS1 RTS1 N.C. RJA1 LLB1 N.C. N.C. N.C. N.C. B10 N.C. B11 N.C. B12 N.C. RCLK1 RPOS1 RNEG1 TJA1 RLB1 N.C. N.C. N.C. N.C. C10 N.C. C11 N.C. C12 N.C. TPOS1 TNEG1 TDM1 JTRST JTMS VDD VSS TBIN RBIN D10 N.C. D11 N.C. D12 N.C. TCLK1 TTS1 TLBO1 JTCLK VDD VDD VSS VSS HW E10 N.C. E11 N.C. E12 E3MCLK TXP1 STS1 E3M1 VDD VDD VDD VSS VSS VSS F10 N.C. F11 N.C. F12 N.C. TXN1 TDSA1 TDSB1 VSS VSS VSS VDD VDD VDD G10 N.C. G11 N.C. G12 N.C. RST N.C. N.C. JTDI VSS VSS VDD VDD TCINV H10 N.C. H11 N.C. H12 N.C. N.C. N.C. N.C. JTDO TEST VSS VDD HIZ RCINV J10 N.C. J11 N.C. J12 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. K10 N.C. K11 N.C. K12 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. L10 N.C. L11 N.C. L12 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. STMCLK N.C. M10 N.C. M11 N.C. M12 N.C. High-Speed Analog High-Speed Digital Low-Speed Digital VDD VSS

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 52 of 61 Figure 14-2. DS3151 CPU Bus Mode Pin Assignment RLOS1 RXN1 RXP1 N.C. T3MCLK N.C. N.C. N.C. N.C. A10 N.C. A11 N.C. A12 N.C. PRBS1 RTS1 N.C. N.C. WR RD CS N.C. N.C. B10 N.C. B11 N.C. B12 N.C. RCLK1 RPOS1 RNEG1 N.C. INT MOT ALE N.C. N.C. C10 N.C. C11 N.C. C12 N.C. TPOS1 TNEG1 TDM1 JTRST JTMS VDD VSS N.C. N.C. D10 N.C. D11 N.C. D12 N.C. TCLK1 TTS1 JTCLK VDD VDD VSS VSS HW E10 N.C. E11 N.C. E12 E3MCLK TXP1 VDD VDD VDD VSS VSS VSS F10 N.C. F11 N.C. F12 N.C. TXN1 VSS VSS VSS VDD VDD VDD G10 N.C. G11 N.C. G12 N.C. RST JTDI VSS VSS VDD VDD N.C. H10 N.C. H11 N.C. H12 N.C. N.C. N.C. JTDO TEST VSS VDD HIZ N.C. J10 N.C. J11 N.C. J12 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. K10 N.C. K11 N.C. K12 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. L10 N.C. L11 N.C. L12 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. STMCLK N.C. M10 N.C. M11 N.C. M12 N.C. High-Speed Analog High-Speed Digital Low-Speed Digital VDD VSS

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 53 of 61 Figure 14-3. DS3152 Hardware Mode Pin Assignment RLOS1 RXN1 RXP1 RMON1 T3MCLK N.C. N.C. N.C. N.C. A10 N.C. A11 N.C. A12 N.C. PRBS1 RTS1 N.C. RJA1 LLB1 N.C. N.C. N.C. N.C. B10 N.C. B11 N.C. B12 N.C. RCLK1 RPOS1 RNEG1 TJA1 RLB1 N.C. N.C. N.C. N.C. C10 N.C. C11 N.C. C12 N.C. TPOS1 TNEG1 TDM1 JTRST JTMS VDD VSS TBIN RBIN D10 N.C. D11 N.C. D12 N.C. TCLK1 TTS1 TLBO1 JTCLK VDD VDD VSS VSS HW E10 N.C. E11 N.C. E12 E3MCLK TXP1 STS1 E3M1 VDD VDD VDD VSS VSS VSS F10 TDSB2 F11 TDSA2 F12 TXN2 TXN1 TDSA1 TDSB1 VSS VSS VSS VDD VDD VDD G10 E3M2 G11 STS2 G12 TXP2 RST N.C. N.C. JTDI VSS VSS VDD VDD TCINV H10 TLBO2 H11 TTS2 H12 TCLK2 N.C. N.C. N.C. JTDO TEST VSS VDD HIZ RCINV J10 TDM2 J11 TNEG2 J12 TPOS2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. RLB2 TJA2 K10 RNEG2 K11 RPOS2 K12 RCLK2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. LLB2 RJA2 L10 N.C. L11 RTS2 L12 PRBS2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. STMCLK RMON2 M10 RXP2 M11 RXN2 M12 RLOS2 High-Speed Analog High-Speed Digital Low-Speed Digital VDD VSS

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 54 of 61 Figure 14-4. DS3152 CPU Bus Mode Pin Assignment RLOS1 RXN1 RXP1 N.C. T3MCLK N.C. N.C. N.C. N.C. A10 N.C. A11 N.C. A12 N.C. PRBS1 RTS1 N.C. N.C. WR RD CS N.C. N.C. B10 N.C. B11 N.C. B12 N.C. RCLK1 RPOS1 RNEG1 N.C. INT MOT ALE N.C. N.C. C10 N.C. C11 N.C. C12 N.C. TPOS1 TNEG1 TDM1 JTRST JTMS VDD VSS N.C. N.C. D10 N.C. D11 N.C. D12 N.C. TCLK1 TTS1 JTCLK VDD VDD VSS VSS HW E10 N.C. E11 N.C. E12 E3MCLK TXP1 VDD VDD VDD VSS VSS VSS F10 N.C. F11 N.C. F12 TXN2 TXN1 VSS VSS VSS VDD VDD VDD G10 N.C. G11 N.C. G12 TXP2 RST JTDI VSS VSS VDD VDD N.C. H10 N.C. H11 TTS2 H12 TCLK2 N.C. N.C. JTDO TEST VSS VDD HIZ N.C. J10 TDM2 J11 TNEG2 J12 TPOS2 N.C. N.C. N.C. N.C. N.C. N.C. K10 RNEG2 K11 RPOS2 K12 RCLK2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. L10 N.C. L11 RTS2 L12 PRBS2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. STMCLK N.C. M10 RXP2 M11 RXN2 M12 RLOS2 High-Speed Analog High-Speed Digital Low-Speed Digital VDD VSS

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 55 of 61 Figure 14-5. DS3153 Hardware Mode Pin Assignment RLOS1 RXN1 RXP1 RMON1 T3MCLK TXN3 TXP3 TCLK3 TPOS3 A10 RCLK3 A11 PRBS3 A12 RLOS3 PRBS1 RTS1 N.C. RJA1 LLB1 TDSA3 STS3 TTS3 TNEG3 B10 RPOS3 B11 RTS3 B12 RXN3 RCLK1 RPOS1 RNEG1 TJA1 RLB1 TDSB3 E3M3 TLBO3 TDM3 C10 RNEG3 C11 N.C. C12 RXP3 TPOS1 TNEG1 TDM1 JTRST JTMS VDD VSS TBIN RBIN D10 TJA3 D11 RJA3 D12 RMON3 TCLK1 TTS1 TLBO1 JTCLK VDD VDD VSS VSS HW E10 RLB3 E11 LLB3 E12 E3MCLK TXP1 STS1 E3M1 VDD VDD VDD VSS VSS VSS F10 TDSB2 F11 TDSA2 F12 TXN2 TXN1 TDSA1 TDSB1 VSS VSS VSS VDD VDD VDD G10 E3M2 G11 STS2 G12 TXP2 RST N.C. N.C. JTDI VSS VSS VDD VDD TCINV H10 TLBO2 H11 TTS2 H12 TCLK2 N.C. N.C. N.C. JTDO TEST VSS VDD HIZ RCINV J10 TDM2 J11 TNEG2 J12 TPOS2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. RLB2 TJA2 K10 RNEG2 K11 RPOS2 K12 RCLK2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. LLB2 RJA2 L10 N.C. L11 RTS2 L12 PRBS2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. STMCLK RMON2 M10 RXP2 M11 RXN2 M12 RLOS2 High-Speed Analog High-Speed Digital Low-Speed Digital VDD VSS

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 56 of 61 Figure 14-6. DS3153 CPU Bus Mode Pin Assignment RLOS1 RXN1 RXP1 N.C. T3MCLK TXN3 TXP3 TCLK3 TPOS3 A10 RCLK3 A11 PRBS3 A12 RLOS3 PRBS1 RTS1 N.C. N.C. WR RD CS TTS3 TNEG3 B10 RPOS3 B11 RTS3 B12 RXN3 RCLK1 RPOS1 RNEG1 N.C. INT MOT ALE N.C. TDM3 C10 RNEG3 C11 N.C. C12 RXP3 TPOS1 TNEG1 TDM1 JTRST JTMS VDD VSS N.C. N.C. D10 N.C. D11 N.C. D12 N.C. TCLK1 TTS1 JTCLK VDD VDD VSS VSS HW E10 N.C. E11 N.C. E12 E3MCLK TXP1 VDD VDD VDD VSS VSS VSS F10 N.C. F11 N.C. F12 TXN2 TXN1 VSS VSS VSS VDD VDD VDD G10 N.C. G11 N.C. G12 TXP2 RST JTDI VSS VSS VDD VDD N.C. H10 N.C. H11 TTS2 H12 TCLK2 N.C. N.C. JTDO TEST VSS VDD HIZ N.C. J10 TDM2 J11 TNEG2 J12 TPOS2 N.C. N.C. N.C. N.C. N.C. N.C. K10 RNEG2 K11 RPOS2 K12 RCLK2 N.C. N.C. N.C. N.C. N.C. N.C. L10 N.C. L11 RTS2 L12 PRBS2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. STMCLK N.C. M10 RXP2 M11 RXN2 M12 RLOS2 High-Speed Analog High-Speed Digital Low-Speed Digital VDD VSS

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 57 of 61 Figure 14-7. DS3154 Hardware Mode Pin Assignment RLOS1 RXN1 RXP1 RMON1 T3MCLK TXN3 TXP3 TCLK3 TPOS3 A10 RCLK3 A11 PRBS3 A12 RLOS3 PRBS1 RTS1 N.C. RJA1 LLB1 TDSA3 STS3 TTS3 TNEG3 B10 RPOS3 B11 RTS3 B12 RXN3 RCLK1 RPOS1 RNEG1 TJA1 RLB1 TDSB3 E3M3 TLBO3 TDM3 C10 RNEG3 C11 N.C. C12 RXP3 TPOS1 TNEG1 TDM1 JTRST JTMS VDD VSS TBIN RBIN D10 TJA3 D11 RJA3 D12 RMON3 TCLK1 TTS1 TLBO1 JTCLK VDD VDD VSS VSS HW E10 RLB3 E11 LLB3 E12 E3MCLK TXP1 STS1 E3M1 VDD VDD VDD VSS VSS VSS F10 TDSB2 F11 TDSA2 F12 TXN2 TXN1 TDSA1 TDSB1 VSS VSS VSS VDD VDD VDD G10 E3M2 G11 STS2 G12 TXP2 RST LLB4 RLB4 JTDI VSS VSS VDD VDD TCINV H10 TLBO2 H11 TTS2 H12 TCLK2 RMON4 RJA4 TJA4 JTDO TEST VSS VDD HIZ RCINV J10 TDM2 J11 TNEG2 J12 TPOS2 RXP4 N.C. RNEG4 TDM4 TLBO4 E3M4 TDSB4 RLB2 TJA2 K10 RNEG2 K11 RPOS2 K12 RCLK2 RXN4 RTS4 RPOS4 TNEG4 TTS4 STS4 TDSA4 LLB2 RJA2 L10 N.C. L11 RTS2 L12 PRBS2 RLOS4 PRBS4 RCLK4 TPOS4 TCLK4 TXP4 TXN4 STMCLK RMON2 M10 RXP2 M11 RXN2 M12 RLOS2 High-Speed Analog High-Speed Digital Low-Speed Digital VDD VSS

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 58 of 61 Figure 14-8. DS3154 CPU Bus Mode Pin Assignment RLOS1 RXN1 RXP1 N.C. T3MCLK TXN3 TXP3 TCLK3 TPOS3 A10 RCLK3 A11 PRBS3 A12 RLOS3 PRBS1 RTS1 N.C. N.C. WR RD CS TTS3 TNEG3 B10 RPOS3 B11 RTS3 B12 RXN3 RCLK1 RPOS1 RNEG1 N.C. INT MOT ALE N.C. TDM3 C10 RNEG3 C11 N.C. C12 RXP3 TPOS1 TNEG1 TDM1 JTRST JTMS VDD VSS N.C. N.C. D10 N.C. D11 N.C. D12 N.C. TCLK1 TTS1 JTCLK VDD VDD VSS VSS HW E10 N.C. E11 N.C. E12 E3MCLK TXP1 VDD VDD VDD VSS VSS VSS F10 N.C. F11 N.C. F12 TXN2 TXN1 VSS VSS VSS VDD VDD VDD G10 N.C. G11 N.C. G12 TXP2 RST JTDI VSS VSS VDD VDD N.C. H10 N.C. H11 TTS2 H12 TCLK2 N.C. N.C. JTDO TEST VSS VDD HIZ N.C. J10 TDM2 J11 TNEG2 J12 TPOS2 RXP4 N.C. RNEG4 TDM4 N.C. N.C. K10 RNEG2 K11 RPOS2 K12 RCLK2 RXN4 RTS4 RPOS4 TNEG4 TTS4 N.C. L10 N.C. L11 RTS2 L12 PRBS2 RLOS4 PRBS4 RCLK4 TPOS4 TCLK4 TXP4 TXN4 STMCLK N.C. M10 RXP2 M11 RXN2 M12 RLOS2 High-Speed Analog High-Speed Digital Low-Speed Digital VDD VSS

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 59 of 61 15. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) BOTTOM VIEW 12 11 10 9 8 7 6 5 4 3 2 1 1.00 A1 BALL PAD CORNER A B C D E F G H J K L M (1.00) (1.00) 1.00 13.00 13.00 Note: All dimensions in millimeters.

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 60 of 61 16. THERMAL INFORMATION Table 16-A. Thermal Properties, Natural Convection PARAMETER MIN TYP MAX UNITS Ambient Temperature (Note 1) -40 +85 °C Junction Temperature -40 +125 °C Theta-JA (θJA), Still Air (Note 2) 22.4 °C/W Psi-JB 9.2 °C/W Psi-JT 1.6 °C/W Note 1: The package is mounted on a four-layer JEDEC standard test board with no airflow and dissipating maximum power. Note 2: Theta-JA (θJA) is the junction-to-ambient thermal resi stance, when the package is mounted on a four -layer JEDEC standard test board with no airflow and dissipating maximum power. Table 16-B. Theta-JA (θJA) vs. Airflow FORCED AIR (m/s) THETA-JA (θJA) 0 22.4°C/W 1 19.0°C/W 2.5 17.2°C/W

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 61 of 61 Maxim/Dallas Semiconductor cannot assume re sponsibility for use of any circuitry ot her than circuitry entirely embodied in a Ma xim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. 17. REVISION HISTORY REVISION DESCRIPTION

012103 DS3154 new product release

DS3151/DS3152/DS3153 new product releases. Electrical Characteristics section, Notes 1 and 2: Changed 44.73MHz to 51.84MHz; added indication that specs are lower for rev A2; “all ones driven into RXPn/RXNn (1.0V square wave)” changed to “analog loopback enabled” to match production test methodology. Table 13-B, Input leakage, IIL: -10μA min changed to -50μA min. Table 13-B: Replaced TBD values for IDD, IDDTS, and IDDPD (DS3151/DS3152/DS3153); changed IDDPD spec from 38 typ and 50 max to 45 typ and 70 max. Table 14-A and Table 14-B: Changed pins RBIN, RCINV, TBIN, and TCINV to “N.C.” to reflect they are not available in CPU bus mode. 072303 Figure 1-1: Labeled capacitors connected to transformer center taps as “(optional)”. Section 6, Optional Pre-Amp Paragraph: Clarified that the pre-amp contributes +14dB of flat gain. Table 11-A: Changed leakage inductance to 0.150μH max. Table 11-B: Reformatted table and added row for Pulse Engineering’s T3049 octal transformer. Table 13-H: Reworded Note 20. 120303 GCR Register Definition (page 16): Clarified that the RST bit holds the digital logic of the LIU in reset rather than the whole LIU. Table 13-B: Changed DS3151 IDD from 130mA (max) to 100mA (max). Changed DS3151 IDDTTS from 105mA (max) to 80mA (max). Removed sentences in Notes 1 and 2 that labeled the IDD and IDDTTS specs for rev A1 devices. 052404 Added typical IDD and IDDTTS numbers to Table 13-B. 110404 Table 13-D and Table 13-E: Changed ALOS set and clear thresholds to typical numbers. Figure 13-4: Added second note to the Read Cycle timing diagrams.

062705 Page 18: RCINV bit description: Changed 0 = rising edge to falling edge; changed 1 = falling edge to

rising edge. 030607 Page 39: In Table 13-D and Table 13-E, changed the TYP receiver input characteristics to show increased sensitivity: Analog LOS Declare, RMON = 0 from -23 to -24 Analog LOS Clear, RMON = 0 from -20 to -21 Analog LOS Declare, RMON = 1 from -37 to -38 Analog LOS Clear, RMON = 1 from -34 to -35