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Features
Three Input Clocks Differential or CMOS/TTL Format Any Frequency from 2kHz to 750MHz Fractional Scaling for 64B/66B and FEC Scaling (e.g., 64/66, 237/255, 238/255) or Any Other Downscaling Requirement Continuous Input Clock Quality Monitoring Three 2/4/8kHz Frame Sync Inputs High-Performance DPLL Hitless Reference Switching on Loss of Input Automatic or Manual Phase Build-Out Holdover on Loss of All Inputs Programmable Bandwidth, 0.5mHz to 400Hz Two Digital Frequency Synthesizers Produce Any 2kHz Multiple Up to 77.76MHz Per-DFS Phase Adjustment High-Performance Output APLL Output Frequencies to 750MHz High Resolution Fractional Scaling for FEC and 64B/66B (e.g., 255/237, 255/238, 66/64) or Any Other Scaling Requirement Less than 1ps RMS Output Jitter Four Output Clocks in Two Groups Nearly Any Frequency from < 1Hz to 750MHz Each Group Slaves to a DFS Clock, Any APLL Clock, or Any Input Clock (Divided and Scaled) Each Has a Differential Output (3 CML, 4 LVDS/ LVPECL) and Separate CMOS/TTL Output 32-Bit Frequency Divider Per Output Two Sync Pulse Outputs: 8kHz and 2kHz IEEE 1588 Clock Features Steerable by Software with 2 -8ns Time Resolution and 2-32ns Frequency Resolution 4ns Input Timestamp Accuracy and Output Edge Placement Accuracy Programmable Clock and Time-Alignment I/O to Synchronize All 1588 Devices in Large Systems Supports 1588 OC, BC, and TC Architectures General Features Suitable Line Card IC or Timing Card IC for Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU Accepts and Produces Nearly Any Frequency from 1Hz Up to 750MHz Internal Compensation for Local Oscillator Frequency Error SPI™ Processor Interface 1.8V Operation with 3.3V I/O (5V Tolerant) 19-5712; Rev 1; 3/11 ABRIDGED DATA SHEET
Typical Application Example, Traditional Frequency Synchronization Typical Application Example, Frequency and Time Synchronization system time, e.g. 1 PPS to all port cardsline clocks, e.g. 25MHzfrom port cards, for SyncE or 1588+SyncE operation DS31415 SPI Local OSC TCXO or OCXO system clock, e.g. 25MHz other clocks Processor 1588 Software packet data to/from central switch function DPLL 1588 Clock ABRIDGED DATA SHEET
Filtering, Holdover, Hitless Switching, PBO, Frequency Conversion, Manual Phase Adjust Microprocessor Port (SPI or I2C Serial) and HW Control and Status Pins RST CS CPHA SCLK SDI SDO INTREQ SRCSW JTAG SYNC1 TEST GPIO[4:1] SRFAIL LOCK SYNC3 IC1 POS/NEG IC2 POS/NEG SYNC2 OC1POS/NEG OC4 CPOL JTRST JTMS JTCLK JTDI JTDO Divider 4 OC1 DS31415 lowest jitter path PLL Bypass OC4POS/NEG IC3 POS/NEG Divider 1 Divider Muxes Dif Mux Input Clock Block Frequency Scaler, Activity Monitor, Freq. Monitor, Optional Inversion (per input clock) Clock Selector status clkin 1588 Clock tainSYNCx out1 out2 ICx OCx ICx OCx to Divider Muxes MCLK Master Clock APLL Local Oscillator TCXO or OCXO MCLKOSC OSCFREQ[2:0] FSYNC MFSYNC 1588 out1 MFSYNC 1588 out2 DFS 1 APLL1 DFS 4 DFS Muxes ABRIDGED DATA SHEET
Three input clocks, differential or CMOS/TTL signal format Input clocks can be any frequency from 2kHz up to 750MHz Per-input fractional scaling (i.e., multiplying by N D where N is a 16-bit integer and D is a 32-bit integer and N < D) to undo 64B/66B and FEC scaling (e.g., 64/66, 238/255, 237/255, 236/255) Special mode allows locking to 1Hz input clocks All inputs constantly monitored by programm able activity monitors and frequency monitors Fast activity monitor can disqualify the select ed reference after a few missing clock cycles Frequency measurement and frequency moni tor thresholds with 0.2ppm resolution Three optional 2/4/8kHz frame-sync inputs DPLL Features Very high-resolution DPLL architecture Sophisticated state machine autom atically transitions between free-run, locked, and holdover states Revertive or nonrevertive reference selection algorithm Programmable bandwidth from 0.5mHz to 400Hz Separately configurable acquisition bandwidth and locked bandwidth Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20 Multiple phase detectors: phase/frequency and multicycle Phase/frequency locking ( 360 capture) or nearest edge phase locking (180 capture) Multicycle phase detection and locking (up to 8191UI) improves jitter tolerance and lock time Phase build-out in response to reference switching for true hitless switching Less than 1ns output clock phase transient during phase build-out Output phase adjustment up to 200ns in 6ps steps with respect to selected input reference High-resolution frequen cy and phase measurement Holdover frequency averaging over 1-se cond, 5.8-minute, and 93.2-minute intervals Fast detection of input clock failure and transition to holdover mode Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks Digital Frequency Synthesizer Features Two independently programmable DFS engines Each DFS can synthesize any 2kHz multiple up to 77.76MHz Per-DFS phase adjust (1/256UI steps) Approximately 40ps RMS output jitter Output APLL Features Simultaneously produce four different output frequencies from the same reference clock Standard telecom output frequencies include 622. 08MHz, 155.52MHz, and 19.44MHz for SONET/SDH and 156.25MHz, 125MHz, and 25MHz for Synchronous Ethernet Very high-resolution fractional scaling (i.e., noninteger multiplication) Less than 1ps RMS output jitter ABRIDGED DATA SHEET
Four output clock signals in two groups Output clock group OC1 has a very high-s peed differential output (current-mode logic, ≤ 750MHz) and a separate CMOS/TTL output (≤ 125MHz) Output clock group OC4 has a high-s peed differential output (LVDS/LVPECL, ≤ 312.5MHz) and a separate CMOS/TTL output (≤ 125MHz) Each output can be any frequency fr om < 1Hz to max frequency stated above Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, microprocessor clock frequencies, and much more Internal clock muxing allows each output group to slave to its associated DFS block, an APLL output, or any input clock (after being divided and scaled) Outputs sourced directly from the AP LL have less than 1ps RMS output jitter Outputs sourced directly from DFS engines have approximately 40ps RMS output jitter Optional 32-bit frequency divider per output 8kHz frame sync and 2kHz multiframe sync outputs have programmable polarity and pulse width and can be disciplined by a 2kHz or 8kHz frame sync input Per-output delay adjustment Per-output enable/disable All outputs disabled during reset
1588 Clock Features
Initialized and steered by software on an exter nal processor to follow an external 1588 master 2 -8ns time resolution and 2-32ns frequency resolution 4ns accuracy for input signal timestamping and output signal edge placement Three time/frequency controls: direct time write, high-resolution frequency adjustment, and time adjustment (i.e., frequency adjustment for an exact duration to achieve gradual, precise time change) Programmable clock and time-alignment I/O to synchronize all 1588 elements in large systems o Can frequency-lock to an input clock signal from a master elsewhere in the system o Can timestamp (TS) an input alignment signal to time-lock to a master elsewhere in the system (e.g., 1PPS) o Can provide an output clock signal to slave co mponents elsewhere in the system (e.g., 25MHz) o Can provide an output time alignment signal to slaves elsewhere in the system (e.g., 1PPS) Two flexible programmable event generators (PEG ) can output one pulse per second (1PPS), one pulse per period, and a wide variety of clock signals Full support for dual redundant timing cards for high-reliability, fault-tolerant systems Compatible with a wide variety of 1588 system architec tures for 1588 ordinary clocks, boundary clocks and transparent clocks General Features SPI serial microprocessor interface Four general-purpose I/O pins Register set can be write protected local oscillator On-chip watchdog circuit for the local oscillator Internal compensation for local oscillator frequency error Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet, go to www.maxim-ic.com/DS31415 and click on Request Full Data Sheet. ABRIDGED DATA SHEET