DS3100DK MAXIM | Alldatasheet
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1 of 32 REV: 110206 GENERAL DESCRIPTION The DS3100DK is an easy-to-use demo and evaluation kit for the DS3100 Stratum 3/3E timing card IC. A surface-mounted DS3100 and careful layout provide maximum signal integrity. An on-board Dallas 8051-compatible microcontroller and included software give point-and-click access to configuration and status registers from a personal computer. LEDs on the board indicate interrupt, power-supply function, and GPIO status. The board provides BNC and bantam connectors for the composite clock and BITS interfaces. Single-ended and LVDS clocks are accessed via SMB connect ors. All LEDs and connectors are clearly labeled with silkscreening to identify associated signals. DEMO KIT CONTENTS DS3100DK PCB CD_ROM Includes: DS3100 Software DS3100 Initialization File DS3100DK Data Sheet DS3100 Data Sheet/Errata Sheet
FEATURES
Soldered DS3100 for Best Signal Integrity SMB Connectors, BNC, Bantam, Transformers, and Termination Ease Connectivity Careful Layout for Analog Signal Paths On-Board Stratum 3 Oscillator with Footprints for Stratum 3E Oscillators DS3100 Configured for CPU Bus Operation for Complete Control Over the Device On-Board Dallas Microcontroller and Included Software Provide Point-and-Click Access to the DS3100 Register Set LEDs for Interrupt, Power Supplies, and GPIO Included International Power Supply Banana Jack VDD and GND Connectors Support Use of Lab Power Supplies Easy-to-Read Silkscreen Labels Identify the Signals Associated with All Connectors, Jumpers and LEDs Header Provided for Master/Slave Connection to a Second DS3100DK Software Provides GUI Fields for Most Commonly Used Features Plus Full Read/Write Access to the Entire Register Set Software Support for Creating and Running Configuration Scripts Saves Time During Evaluation MINIMUM SYSTEM REQUIREMENTS PC Running Windows® XP or Windows 2000 Display with 1024 x 768 Resolution or Higher Available Serial (COM) Port DB-9 Serial Cable
ORDERING INFORMATION
DS3100DK Demo kit for DS3100 DS3100DK Stratum 3/E3 Timing Card IC Demo Kit www.maxim-ic.com Windows is a registered trademark of Microsoft Corp.
1.1 Input and Output Clocks
There are 13 SMB connectors at the top of the board labeled IC1–IC4, IC7–IC14, and SYNC2K that provide a single-ended clock input to the DS3100. All single-ended clock inputs are connected to the DS3100 with a 50 Ω characteristic impedance trace and terminated with 50 Ω at the device. Four additional SMB connectors labeled IC5P, IC5N, IC6P, and IC6N provide differential clock in puts to the DS3100. These differential inputs have 50 Ω trace impedance and 50Ω termination at the device (i.e., 100Ω differential). On the other end of the PCB are eight SMB clock out put connectors labeled OC1–OC5 and OC9, OC10, and OC11. All single-ended clock outputs are buffered at the DS3100 and connected to the SMB connector via a 50 Ω characteristic impedance trace. Four additional SMB connectors labeled OC6P, OC6N, OC7P, and OC7N provide connections to the differential outputs from the DS3100.
1.2 Jumpers, Headers, and Switch Settings
Jumpers JMP1 to JMP4 (upper right of board) provide inpu t settings to the four DS3100 GPIO pins. If a jumper is installed the corresponding GPIO input is high. With no jumper the GPIO pin defaults low. LEDs DS5–DS8 indicate the logic level of the GPIO pins (LED lit means GPIO pin is high). Switches SW 7 to SW9 set the SONSDH, SRCSW and MASTSLV pins, respectively, high or low as in dicated by the silkscreen. Headers J1 and J2 provide access to BITS1 and BITS2 framer signals, respectively. Header J51 provides access to the JTAG port of the DS3100. Header J15 provides interface to a master or slave board depending on position of switch SW6.
1.3 Composite Clock Interface
Bantam jacks J89 and J90 provide access to composite clock inputs IC1A and IC2A through a 2:1 transformer. Jumpers JMP7 and JMP6 configure termination for IC1A and IC2A respectively. Silkscreen text indicates which jumper is necessary to set the interface at 110Ω, 120Ω, or 133Ω. Bantam jack J117 provides an interface through a 1:1 transformer to the OC8 composite clock output. Jumpers JMP8, JMP9, and JMP10 provide different attenuation configurations that are repr esented in silkscreen (Rs = 91 Ω with no jumper installed). See the schematics for additional details on the composite clock termination circuitry.
1.4 BITS Interfaces
The BITS1 DS1/E1 LIU uses bantam connectors J85 and J55 or BNC connectors J83 and J57 for transmit and receive interfaces, respectively. The BITS2 LIU uses bant am connectors J86 and J56 or BNC connectors J84 and J58 for transmit and receive, respectively. There is a dual transformer package for each BITS transceiver (component T1 for BITS1 and T2 for BITS2). See the schema tics for additional details on the BITS termination circuitry.
1.5 Microcontroller
The DS87C520 microcontroller has factory-installed firm ware in on-chip nonvolatile memory. This firmware translates memory access requests from the RS-232 serial port or USB port into register accesses on the DS3100. When the microcontroller starts up it turns on DS16 to indicate that the controller is working correctly. A pushbutton switch labeled RESET (SW5) at the right middle of the board resets the microcontroller as well as the DS3100.
1.6 Power-Supply Connectors
The included international power supply can be connected to jack J3 to power the board or a 5V lab power supply can be connected across the red (J13) and black (J19) banana jacks. The 5V input is then regulated to 3.3V and 1.8V and distributed to board components.
- BASIC HARDWARE SETUP The following steps provide a quick start to using the DS3100DK. 1) Configure the board for serial (RS-232) communicati on by placing jumpers to connect the left and middle pins of JMP62 and JMP63 (near the serial connector). USB operation is not yet supported. 2) Ensure switch SW6 (near the OC1 and OC 2 connectors) is in the “MAS” position. 3) Set switch SW9 (MASTSLV) in the “1” (master) position. 4) Set switch SW8 in “0” (normal operation) position. 5) Set switch SW7 to “1” to have the 1.544/2.048MHz frequency options in the DS3100 default to 1.544MHz. Set SW7 to “0” for 2.048MHz. 6) Connect a standard DB-9 serial cable between t he serial port connector on the DS3100DK and an available serial port on the host computer. (Be sure t he cable is a standard straight-through cable rather than a null-modem cable. Null-modem cables prevent proper operation.) 7) Attach the appropriate AC power supply prong s to the included international power supply. 8) Plug the power supply into an AC power outlet and c onnect the DC output of the supply to connector J3 (PWR in Figure 1-1). At this point the power indicator LEDs DS1–DS4 should be lit. Microcontroller status LED DS16 (to the right of the USB connector) should also be lit. 3. INSTALLING AND RU NNING THE SOFTWARE At this time the DS3100 demo kit software only runs on Windows 2000 or Windows XP operating systems. To install the demo kit software, run SETUP.EXE from the di sk included in the DS3100DK box or from the zip file downloadable on our website at www.maxim-ic.com/DS3100DK. After software installation is complete, set up the har dware as described above and run the software by double- clicking the DS3100 Demo Kit icon on the Windows desktop or by selecting Start→Programs→Dallas Semiconductor→DS3100 Demo Kit. When the main window appears, select the correct serial port in the box in the lower right corner. When communication has been properly established between the software and the hardware, the ID field in the upper-left corner should indicate 3100 rev x, where x = 0 for a revision A1 device, and x = 1 for a revision A2 device. The demo kit software always starts in demo mode (wit h the DEMO MODE checkbox in the upper-left corner checked) in case a user wants to look at the softwar e without having the DK hardware connected to the PC. To connect the software with the demo kit hardware, uncheck the DEMO MODE box. The software optionally initializes the DS3100 device and then reads the state of the device to get ready for use.
3.1 Command Line Options
The demo kit software has these command line options: -l <filepath> specifies an alternate log file example: “DS3100DK.exe –l mylog.mfg -p[port#] sets the serial (COM) port number example: “DS3100DK.exe –p2” sets COM2 To add command line options to a shortcut, such as the DS3100 demo kit shortcut that the installer adds to the desktop, right click on the shortcut and select Properties. In the Shortcut tab, at the end of the text in the Target textbox, add a space followed by the command line option.
- OVERVIEW OF THE SOFTWARE INTERFACE
4.1 Global Configuration
In the upper-left corner of the main window are several global status and configuration fields including the device ID and REV, the status of the MASTSLV pin (MCR3:MAST SLV), the software DEMO MODE check box, and the 1.544MHz vs. 2.048MHz frequency selection bit (MCR3:SONSDH).
4.2 Input Clock Monitor, Divider, and Selector
This box occupying the left-center section of the main window contains the most frequently used configuration and status associated with input clocks IC1–IC14. At the far left, inputs IC1 and IC2 can be configured for either composite clock (on the IC1A and IC2A pins, respective ly) or CMOS (on the IC1 and IC2 pins, respectively). Similarly, IC5 and IC6 can be configured for LVDS or PECL operation. Just to the right of the input clock numbers 1–14 are software LEDs that indicate the state of each input as reported by its input monitor. These LEDs ar e red in the absence of any other c ondition. When a clock of the correct frequency is applied to an input, the associated LED turns yellow when activity is detected and, about 10 seconds later, it turns green if the input clock frequency is with in range. If an input is disqualified by one of the DPLLs because the DPLL could not lock to it, the LED turns magenta. In the middle of the box, the FREQ and LK MODE fields c onfigure the frequency and lock mode (direct-lock, DIVN, or LOCK8K) for each input clock. At the bottom is a fiel d to configure the DIVN divi der used for inputs configured for DIVN mode. All the fields in the box containing t he PRIORITY fields display information about either the T0 DPLL or the T4 DPLL, depending on which of two radio buttons is select ed at the bottom of the box. The PRIORITY fields configure the input clock priorities for the selected DPLL. The SEL REF field shows the selected reference for the DPLL, while the REF 1, REF 2, and REF 3 fields display the three highest priority valid inputs for the DPLL. The FREQ and PHASE fields show the real-time frequency and phase reported by the DPLL. In future releases of the DS3100DK software, the More button will open a secondary window with additional configuration and status fields. Table 4-1. Mapping Between Input Clock Software Fields and DS3100 Register Fields SOFTWARE FIELD DS3100 REGISTER FIELDS IC1 Signal Format (CMOS or CC) MCR5:IC1SF IC2 Signal Format (CMOS or CC) MCR5:IC2SF IC5 Signal Format (LVDS or PECL) MCR5:IC5SF IC6 Signal Format (LVDS or PECL) MCR5:IC6SF Input Clock Status LEDs ISR1–ISR7 registers LED red when ACT = 1, HARD = 1 LED yellow when ACT = 0, HARD = 1 LED green when ACT = 0, HARD = 0, LOCK = 0 LED magenta when ACT = 0, HARD = 0, LOCK = 1 FREQ ICR1–ICR14, FREQ[3:0] LK MODE ICR1–ICR14, LOCK8K, and DIVN PRIORITY IPR1–IPR7 SEL REF PTAB1:SELREF REF 1 PTAB1:REF1 REF 2 PTAB2:REF2 REF 3 PTAB3:REF3 FREQ (ppm) FREQ1, FREQ2 and FREQ3 registers concatenated PHASE (deg) PHASE1 and PHASE2 register concatenated
4.3 T0 DPLL
The state of the T0 DPLL (free-run, locked, holdover, etc.) is shown in the STATE field. The STATE CHG, SRFAIL and PHMON fields are buttons that represent latched status bits in the device. When the button is raised in the middle, the corresponding latched status bit has been se t in the DS3100. Pressing the button clears the latched status bit. STATE CHG indicates the state of the T0 DPLL has changed since the last time the button was pressed. SRFAIL indicates the selected reference has failed since the last time the button was pressed. PHMON indicates the phase monitor limit (set by PMLIM) has been exceeded. The state of the T0 DPLL can be forced using the combo box to the left of the STATE field, and the selected reference can be forced using the CLK SEL field. Below the CLK SEL field is a field that configures the T0 DPLL for revertive or nonrevertive input reference switching. The frequency of the T0 DPLL is displayed in the FREQ field (fixed at 77.76MHz for the DS3100 T0 DPLL). The acquisition and locked bandwidths are set by the ABW a nd LBW fields, respectively, and the damping factor is set by the DAMP field. The acquisition bandwidth is only us ed if AUTOBW is checked. If the frequency of the T0 DPLL’s selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY LIMITS box at the top of the window), the SOFTLIM LED turns red. The PALARM status LED and the PHASE MONITOR an d BUILDOUT fields ar e advanced topics. See Table 4-2 and the DS3100 data sheet for more details. In future releases of the DS3100DK software, the More button will open a secondary window with additional configuration and status fields. Table 4-2. Mapping Between T0 DPLL Software Fields and DS3100 Register Fields SOFTWARE FIELD DS3100 REGISTER FIELDS STATE combo box MCR1:T0STATE STATE status box OPSTATE:T0STATE CLK SEL MCR2:T0FORCE Revertive/Nonrevertive MCR3:REVERT FREQ Fixed by T0 DPLL architecture ABW T0ABW LBW T0LBW DAMP T0CR2:DAMP STATE CHG MSR2:STATE SRFAIL MSR2:SRFAIL PHMON MSR3:PHMON PALARM TEST1:PALARM SOFTLIM OPSTATE:T0SOFT AUTOBW MCR9:AUTOBW LIMINT MCR9:LIMINT PMLIM PHMON:PMLIM PMEN PHMON:PMEN PMPBEN PHMON:PMPBEN PBOEN MCR10:PBOEN PBOFRZ MCR10:PBOFRZ RECAL FSCR3:RECAL MANUAL PBO OFFSET1 and OFFSET2
4.4 T4 DPLL
The state of the T4 DPLL (locked or not locked) is show n in the STATE field. The LOCK and NO INPUT fields are buttons that represent latched status bi ts in the device. When the button is raised in the middle, the corresponding latched status bit has been set in the DS3100. Pressing the button clears the latched status bit. LOCK indicates the state of the T4 DPLL has changed since the last time the button was pressed. NO INPUT means the T4 DPLL has no valid inputs available. The selected reference for the T4 DPLL can be forced using the CLK SEL field. The frequency of the T4 DPLL is displayed in the FREQ fi eld. When the FREQ field is changed, the frequency of the T4 option listed in the T4 APLL combo box automatically changes to match. If the T4 option in the T4 APLL box is currently selected, the frequencies of all of the T4 options in the OC1–OC7 output clock combo boxes automatically change to frequencies derived from t he new T4 APLL frequency. These changes match what happens inside the DS3100 device. The bandwidth of the T4 DPLL is set by the BW field, wh ile the damping factor is set by the DAMP field. If the frequency of the T4 DPLL’s selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY LIMITS box at the top of the window ), the SOFTLIM LED turns red. Digita l feedback (vs. analog feedback through the T4 APLL) can be selected using the DIGFB checkbox. The LKT4T0 and T4MT0 fields are advanced topics. See Table 4-3 and the DS3100 data sheet for more details. In future releases of the DS3100DK software, the More button will open a secondary window with additional configuration and status fields. Table 4-3. Mapping Between T4 DPLL Software Fields and DS3100 Register Fields SOFTWARE FIELD DS3100 REGISTER FIELDS STATE OPSTATE:T4LOCK CLK SEL MCR4:T4FORCE FREQ T4CR1:T4FREQ BW T4BW DAMP T4CR2:DAMP LOCK MSR3:T4LOCK NO INPUT MSR3:T4NOIN SOFTLIM OPSTATE:T4SOFT DIGFB MCR4:T4DFB LKT4T0 MCR4:LKT4T0 T4MT0 T0CR1:T4MT0
4.5 T0 APLL
The T0 APLL can be connected to the output of the T0 Output DFS or to the T0 Low-Frequency DFS (see DS3100 data sheet for details). The frequency options listed in the T0 APLL field are all APLL input frequencies. The APLL output frequency is always four times the input frequency. The difference between the “77.76 Analog” and “77.76 Digital” options is whether or not the feedback path of the T0 DPLL includes the T0 feedback APLL. The non-77.76 options in the T0 APLL field are all frequencies from the T0 Low-Frequency DFS. When the T0 APLL setting is changed, the frequencies of all the T0 options in the OC1–OC7 output clock combo boxes automatically change to frequencies derived from the new T0 APLL frequency. These changes match what happens inside the DS3100 device. Table 4-4. Mapping Between T0 APLL Software Fields and DS3100 Register Fields SOFTWARE FIELD DS3100 REGISTER FIELDS T0 APLL T0CR1:T0FREQ
4.6 T4 APLL
The T4 APLL can be connected to the output of the T4 DPLL or to the output of the T0 DPLL (specifically the T0 low-frequency DFS; see DS3100 data sheet for details). The frequency options listed in the T4 APLL field are all APLL input frequencies. The APLL output frequency is always four times the input frequency. When the FREQ field is changed in the T4 DPLL box, the frequency of the T4 option listed in the T4 APLL combo box automatically changes to match. If the T4 option in the T4 APLL box is currently selected, the frequencies of all the T4 options in the OC1–OC7 output clock combo boxes automatically chan ge to frequencies derived from the new T4 APLL frequency. These changes match what happens inside the DS3100 device. Similarly, if the T4 APLL option is changed, the frequencies of all the T4 options in the OC1–OC7 output clock combo boxes automatic change to frequencies derived from the new T4 APLL frequency. Table 4-5. Mapping Between T4 APLL Software Fields and DS3100 Register Fields SOFTWARE FIELD DS3100 REGISTER FIELDS T4 APLL T0CR1:T4APT0, T0CR1:T0FT4
4.7 Output Clocks
The fields in this box configure the DS3100’s 11 output clocks. The 2K8K field specifies the source (T0 path or T4 path) for the 2kHz and 8kHz clock options for output cl ocks OC1–OC7. Similarly the DIG1 and DIG2 fields configure the Digital1 and Digital2 frequency options for OC1–OC7 (see the DS3100 data sheet for details). The OC1–OC7 fields specify the output frequencies for out puts OC1–OC7. Note that when the T0 APLL setting is changed, the frequencies of all the T0 options in the OC1–OC7 fields automatically change to frequencies derived from the new T0 APLL frequency. Similarly, when the T4 APLL setting is changed, the frequencies of all the T4 options in the OC1–OC7 fields automatically change to frequencies derived from the new T4 APLL frequency. These changes match what happens inside the DS3100 device. The OC89 field specifies whether the T0 path or the T4 path is the source for output clocks OC8 and OC9. OC8 is the 64kHz composite clock output. The OC8 field configur es the OC8 output clock for 50% or 5/8 duty cycle, and also for whether or not the output si gnal has 8kHz BPVs and optionally 400Hz absence-of-BPVs per ITU-T G.703 Appendix II options a) and b). The “8K” options in the list enable the 8kHz BPVs but not the 400Hz absence-of- BPVs. The “400” options enabl e both the 8kHz BPVs and the 400Hz absence-of-BPVs. OC 9 is a dedicated 1.544MHz or 2.048MHz output. When OC 89 specifies that OC8 and OC9 are sourced from the T4 path, the Auto Squelch checkbox specifies whether or not OC8 and OC9 are automatically sq uelched when T4 has no valid input references. When OC89 indicates T0 path, Auto Squelch is not available to match DS3100 behavior. OC10 is an 8kHz output that can be configured as a 50% duty cycle clock or a frame pulse and can optionally be inverted. OC11 is a 2kHz output that can be similarly configured. Table 4-6. Mapping Between Output Clock Software Fields and DS3100 Register Fields SOFTWARE FIELD DS3100 REGISTER FIELDS 2K8K FSCR1:2K8KSRC DIG1 MCR6:DIG1SS, MCR7:DIG1F DIG2 MCR6:DIG2SS, M CR7:DIG2F, MCR7:DIG2AF OC1–OC7 OCR1–OCR4 OC89 MCR4:OC89 Auto Squelch T4CR1:ASQUEL OC8 OCR4:OC8EN, T4CR1:OC8DUTY MCR8:OC8NO8, MCR8:OC8400 OC9 OCR4:OC9EN, T4CR1:OC9SON OC10 OCR4:OC10EN, FSCR1:8KPUL, FSCR1:8KINV OC11 OCR4:OC11EN, FSCR1:2KPUL, FSCR1:2KINV
4.8 DPLL Frequency Limits, Phase Detectors, DPLL Lock Criteria
The DPLL frequency limits specify the hard and soft limit s of the DPLL frequency range. When the selected reference for a DPLL exceeds the soft limit, the SOFTLIM LED for that DPLL turns red but the selected reference is not disqualified. If the FLLOL (frequency lim it loss of lock) box is checked in th e DPLL Lock Criteria box, when the selected reference for a DPLL exceeds the hard limit the DPLL will lo se lock (T4 transitions to Not Locked state, and T0 transitions to LOL state). The remaining fields are advanced topics. See Table 4-7 and the DS3100 data sheet for more details. Table 4-7. Mapping Between DPLL Software Fields and DS3100 Register Fields SOFTWARE FIELD DS3100 REGISTER FIELDS HARD LIMIT HARDLIM[9:0] in DLIMIT1 and DLIMIT2 SOFT LIMIT DLIMIT3:SOFTLIM MCPDEN PHLIM2:MCPDEN USEMCPD PHLIM2:USEMCPD D180 TEST1:D180 COURSELIM PHLIM2:COARSELIM FINELIM PHLIM1:FINELIM FLEN PHLIM1:FLEN CLEN PHLIM2:CLEN FLLOL DLIMIT3:FLLOL NALOL PHLIM1:NALOL
4.9 BITS Receivers and BITS Transmitters
The Mode fields in these boxes set the basic line mode for each port (DS1 ESF or SF, E1, 2048kHz, and—for receivers only—6312kHz). The termination fields specify t he line termination for the receiver or transmitter port. The DS3100 supports either internal termination (inside the device) or external termination (resistors on the board). As shipped from the factory the demo kit hardware does not have external terminati on resistors populated, and therefore only the internal termination options should be se lected in the software. The input clock (IC1–IC14) to which each BITS receiver should be connected is specifi ed in the CLOCK DEST fields. The output clock to which each BITS transmitter should be connected is specified in the CLOCK SOURCE fields. In the BITS Transmitters box, when a transmitter is in DS1 ESF or E1 mode, the SSM value to be transmitted can be specified in the SSM fields below the TX1 and TX2 headings. In E1 mode, the Sa bit channel in which to transmit SSMs can be specified (for both transmitters) in the small combo box next to the SSM label. In the BITS Receivers box, when a receiver is in DS1 ESF or E1 mode, the received SSM values are displayed in the SSM fields below the RX1 and RX2 headings. In E1 mode, the Sa channel in which to look for incoming SSMs can be specified (for both receivers) in the small combo box next to the SSM label. In future releases of the DS3100DK software, the headings RX1, RX2, TX1, and TX2 will also be buttons that open secondary windows with additional configuration and status fields.
4.9.1 Note About Working with the BITS Receivers and Transmitters
1) When switching BITS transmitter or receiver modes, the termination must be changed to match: internal 100Ω for DS1, internal 75Ω or 120Ω for E1 and 2048kHz, internal 75Ω for 6312kHz. 2) When switching BITS transmitter modes between DS1 and E1/2048kHz modes, the rate of the transmit clock source (typically OC9) must be chang ed to match: 1.544MHz for DS1 and 2.048MHz for E1/2048kHz. 3) Enabling analog loopback between BITS transmitter 1 and BITS receiver 1 and between BITS transmitter 2 and BITS receiver 2 can be useful in evaluating the DS3100. During device initialization the DS3100DK software enables analog loopback for both BITS transmitte r/receiver pairs by setting ALB = 1 in registers B1BLCR4 (address 93h) and B2BLCR4 (address 113h). Table 4-8. Mapping Between BITS Software Fields and DS3100 Register Fields SOFTWARE FIELD DS3100 REGISTER FIELDS BITS RECEIVERS Mode BMCR:RMODE, BCCR3:MCLKFC, BRMMR, BRCR1:RB8ZS, BRCR1:RFM, BRCR3:RHDB3, BRCR3:RCRC4 See APPENDIX 2: BITS MODE WRITE SEQUENCES for exact write sequences for each mode Termination BLCR3:RION, BLCR3:RIMP Clock Dest BCCR2:RCLKD Left-Hand SSM Combo (E1 Only) BRMCR:SSMCH SSM Textboxes DS1 ESF: BTBOC:TBOC E1: BRMSR, BRSSM:SSM BITS TRANSMITTERS Mode BMCR:TMODE, BTMMR, BTCR1:TB8ZS, BTCR3:TFM, BTCR4:THDB3, BTCR4:TCRC4, 60, 61 See APPENDIX 2: BITS MODE WRITE SEQUENCES for exact write sequences. Termination BLCR2:TION, BLCR2:TIMP Clock Source BCCR1:TCLKS Left-and SSM Combo (E1 Only) Indicates which of BTSa4–BTSa8 to use Main SSM Combos DS1 ESF: BRBOC:RBOC E1: BTSa4–BTSa8
4.10 Composite Clock Receivers
The AMI and LOS fields are buttons that represent latched status bits in the device. When the button is raised in the middle, the corresponding latched status bit has been set in the DS3100. Pressing the button clears the latched status bit. The AMI buttons indicate a deviation from the expected one-BPV-in-eight pattern has occurred since that button was last pressed. The LOS buttons indicate no pulses were detected in the input signal in a 32 μs period (i.e., after two missing pulses). In future releases of the DS3100DK software, the More button will open a secondary window with additional configuration and status fields. Table 4-9. Mapping Between CC Software Fields and DS3100 Register Fields SOFTWARE FIELD DS3100 REGISTER FIELDS IC1 AMI MSR3:AMI1 IC1 LOS MSR3:LOS1 IC2 AMI MSR3:AMI2 IC2 LOS MSR3:LOS2
4.11 REFCLK Calibration
Any known frequency error in the local oscillator can be calibrated out inside the DS3100 by setting the ppm value in the REFCLK box. Also the significant edge of the REFCLK signal can be selected in XOEDGE field. Table 4-10. Mapping Between REFCLK Software Fields and DS3100 Register Fields SOFTWARE FIELD DS3100 REGISTER FIELDS REFCLK slider/textbox MCLKFR EQ[15:0] in MCLK1 and MCLK2 XOEDGE MCR3:XOEDGE
4.12 Register View Window
When the Register View button in the upper-right corner of the main window is pressed, the Register View window appears. In this window the DS3100’s entire register set can be viewed and manually written as needed. The large grid that takes up most of the window disp lays the DS3100 register map. For each register, its hexadecimal address in square brackets is followed by its register name and its contents in 2-digit hex format. The DS3100’s core register space is 00h to 7Fh, its BITS transceiver 1 register space is 80h to FFh, and its BITS transceiver 2 register space is 100h to 17Fh. To distingui sh between BITS1 and BITS2 registers, all BITS1 register names start with “B1” and all BITS2 register names start with “B2.” When a register is clicked on in the main register grid, its register description and fields are displayed at the bottom of the window. Due to the limited speed of the serial po rt, the demo kit software does not continually poll every register and make real-time updates to the data displayed on the Register View screen. Register of concern should be manually read as described below. The Register View window supports the following actions:
- Read a register. Select the register in the register map and click the Read button.
- Read all registers. Press the Read All button.
- Write a register field. Select the register, double-click the field, and enter the value to be written.
- Write a register. Double-click the register name in the register array and enter the value to be written.
- Write a multi-register field. Double-click on one of the register names in the register array and enter the value for the field. The software will not allow writes to read-only registers or fields, but it does allow writes to registers that have a mix of read/write and read-only fields.
4.13 Configuration Scripts and Log File
4.13.1 Configuration Log File
Every write command issued by the software to the DS310 0DK board is logged in file DS3100DKLog.mfg located in the same directory as the software executable. This file can be viewed in Notepad by pressing the Log File button in the upper-right corner of the main window. Co mmand line option "-l <filepath>" can be used to cause the software to write to a different file than DS3100DKLog.mfg.
4.13.2 Configuration Scripts
All or part of the text in the Configuration Log File can be copi ed to a text file with a .mfg file extension for use as a configuration script. Configuration scripts are useful for quickly configuring the DS3100 without having to remember all of the required settings. Two types of configuration scripts are possible: full and partial. A full configuration script can start with the DS3100 in its power-on default state and configur e every aspect of the device to bring it to a desired state. To make a full configuration script, run the software, uncheck the De mo Mode checkbox, configure the device using the DK software fields (including Register View writes as needed) , press the Log File button, and use File->Save As in Notepad to save a copy of the entire log file to a different file name. A partial configuration file only affects a subset of the DS3100 device settings. To make a partial configuration script, press the Log File button to view the Log File, press Ctrl-End to jump to the end of the file, and add to the end of the file a carriage return or comment line (starting with a semicolon) to delimit the start of the configuration. Then save and exit the Log File. Next configure the device using the DK software fields (including Register View writes as needed). Finally view the log file again, jump to the end, and copy everything from the delimiter you made earlier to the end of the file into a new .mfg file. To run a configuration script, press the Config Script bu tton in the upper-right corner of the main window. In the script window, type the path to the file or press the Browse button to navigate to the file. Note that the browser window does not have Desktop and My Documents at the top of the file hierarchy like Windows XP does. Both Desktop and My Documents for <username> can be found under c:\\Documents and Settings\\<username>. Note that when the Demo Mode checkbox is unchecked, during the "Initializing the DS3100" step, the software runs configuration script startup.mfg located in the same directory as the software ex ecutable. Startup.mfg can be edited or replaced as needed to change the initial configuration of the device. 5. ADDITIONAL INFO RMATION AND RESOURCES
5.1 DS3100 Information
For more information about the DS3100, refer to the DS3100 data sheet at www.maxim-ic.com/DS3100.
5.2 DS3100DK Information
For more information about the DS3100DK including software downloads, refer to the DS3100DK Quick View page at www.maxim-ic.com/DS3100DK.
5.3 Technical Support
For additional technical support, e-mail your questions to telecom.support@dalsemi.com.
- APPENDIX 1: HARDWARE COMPONENTS DESIGNATION QTY DESCRIPTION SUPPLIER PART C1, C2, C3, C8, C42, C59–C138, C140, C142, C143, C145, C147, C149, C151, C155, C163–C166, C168, C169 99 0.1μF ±20%, 16V X7R ceramic capacitors (0603) AVX 0603YC104MAT C4, C5, C6, C27 4 Ceramic capacitors (0805) DO NOT POPULATE — — C6 1 470pF ±5%, 50V CGO ceramic capacitor (0805) AVX 08055A471JAT C7 1 68μF ±20%, 16V tantalum capacitor (D case) Panasonic ECS-T1CD686R C13, C14, C16, C41 4 4.7μF ±10%, 25V X5R ceramic capacitors (1206) Panasonic ECJ-3YB1E475K C17, C18, C20 3 6.8μF ±10%, 6.3V X5R ceramic capacitors (1206) Panasonic ECJ-3YB0J685K C28, C29 2 560pF ±5%, 50V NPO ceramic capacitor (0805) Panasonic ECJ-2VC1H561K C34–C38, C51–C58, C139, C141, C153, C154 17 10μF ±20%, 10V ceramic capacitors (1206) Panasonic ECJ-3YB1A106M C39, C40 2 22pF ±10%, 100V ceramic capacitors (1206) AVX Corp. 12061A220KAT2A C43 1 1μF ±10%, 16V ceramic capacitor (1206) Panasonic ECJ-3YB1C105K C48, C49 2 0.47μF ±10%, 16V ceramic capacitors (0805) Panasonic ECJ-2YB1C474K D1 1 1A, 50V general-purpose silicon diode Vishay General Semiconductor 1N4001 D7 1 1A, 40V Schottky diode International Rectifier 10BQ040 DS1–DS4 4 Green LEDs (SMD) Panasonic LN1351C DS5–DS10 6 Red LEDs (SMD) Panasonic LN1251C DS16 1 Green LED (SMD) Panasonic LN1351C J1, J2 2 6-pin socket strip (single row, vertical) Samtec SS-106-TT-2-N J3 1 2.1mm/5.5mm closed frame power jack, high current (right angle PCB, 24VDC at 5A) CUI Inc. PJ-002AH J6–J12, J20–J41 29 5-pin vertical SMB connectors (50Ω) AMP 413990-1 J13 1 Red socket (banana pl ug, horizontal) Mouser 164-6219 J14 1 5-pin vertical SMB connector (50Ω) DO NOT POPULATE AMP 413990-1 J15 1 10-pin terminal strip (dual ro w, vertical) Samtec TSW-105-07-T-D J19 1 Black horizontal banana plug socket Mouser 164-6218 J50 1 DB9 right-angle connector (long case) AMP 747459-1 J51 1 10-pin terminal strip (dual row, vertical) — — J54 1 USB Type B black connector (right angle) Molex 67068-0000 J55, J56, J85, J86, J89, J90, J117 7 Bantam jack connectors (right angle) Switchcraft RTT34B02 J57, J58, J83, J84 4 5-pin BNC connectors (50Ω, right angle) Trompeter CBJR220
DESIGNATION QTY DESCRIPTION SUPPLIER PART JMP1–JMP5, JMP8, JMP9, JMP11, JMP12, JMP36, JMP37 11 2-pin vertical headers, 0.100 " centers Samtec TSW-102-07-T-S JMP6, JMP7, JMP10, JMP62, JMP63 5 3-pin vertical headers, 0.100 " centers Samtec TSW-103-07-T-S R1 1 10kΩ ±5%, 1/10W resistor (0805) Panasonic ERJ-6GEYJ103V R2, R3, R6, R7, R9, R11, R16-R18 9 Resistors (0603) DO NOT POPULATE — — R4, R5, R8, R10, R12- R14, R20, R25, R42, R46, R84, R91, R92, R95-R97, R110, R113, R115, R116, R120- R123 25 10kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V R15, R22, R23, R24, R41, R43, R45, R47,R49, R51, R53, R55, R80, R81, R111, R112, R117, R118 18 0Ω ±1%, 1/16W resistors (0603) AVX CJ10-000F R19, R21, R40, R44 4 1.0kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ102V R26, R27, R48, R50, R52 5 470Ω ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ471V R28 1 33.2Ω ±1%, 1/16W resistors (0603) Panasonic ERJ-3EKF33R2V R29–R35, R59–R68 17 51.1Ω ±1%, 1/16W resistors (0603) Panasonic ERJ-3EKF51R1V R36–R39, R94, R108 6 330Ω ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ331V R54, R56, R57, R58, R74, R77, R89, R90 8 0Ω ±5%, 1/8W resistors (1206) Panasonic ERJ-8GEYJ0R00V R69, R72 2 110Ω ±1%, 1/10W resistors (0805) Panasonic ERJ-6ENF1100V R70, R93 2 10.0Ω ±1%, 1/10W resistors (0805) Panasonic ERJ-6ENF10R0V R71, R73 2 13.0Ω ±1%, 1/10W resistors (0805) Panasonic ERJ-6ENF13R0V R75, R76 2 90.9Ω ±1%, 1/10W resistors (0805) Panasonic ERJ-6ENF90R9V R78 1 357Ω ±1%, 1/10W resistor (0805) Panasonic ERJ-6ENF3570V R79 1 301Ω ±1%, 1/10W resistor (0805) Panasonic ERJ-6ENF3010V R82, R83 2 0.0Ω ±5%, 1/10W resistors (0805) Panasonic ERJ-6GEY0R00V R85–R88 4 Resistors (0805) DO NOT POPULATE — — SW5 1 4-pin single-pole switch Panasonic EVQPAE04M SW6 1 6-pin, through-hole, DPDT slide switch Tyco SSA22 SW7, SW8, SW9 3 3-pin, through-hol e, SPDT slide switches Tyco SSA12 T1, T2 2 16-pin SMT T1 transformers (1CT:1CT and 1CT:2CT, 1500V) Pulse Engineering PE-68678 T3 1 12-pin dual SMT transformer (64kbps, 1CT:2CT, 1500V) Pulse Engineering T7015 T4 1 64kbps interface transformer (1CT:1CT, 1500V, 6-pin DIP) Pulse Engineering PE-65540 TP1–TP10, TP18– TP42, TP49–TP61, TP65–TP84 68 1 plated hole test points DO NOT STUFF — — U1 1 High-frequency, surface-mount socket (1mm, 256-pin BGA) Ironwood Electronics SG-BGA-6017 U2, U3, U5, U7, U9–U26 22 TinyLogic ultra-high-speed 2-input OR gates (5-pin SOT23) Fairchild Semiconductor NC7SZ32M5
DESIGNATION QTY DESCRIPTION SUPPLIER PART U4, U6 2 3.3V linear regulator (16-pin TSSOP-EP) Maxim MAX1793EUE-33 U8 1 1.8V linear regulator (16-pin TSSOP-EP) Maxim MAX1793EUE-18 U27 1 3-line to 8-line decoder/demultiplexer (16-pin SO ) Texas Instruments SN74HC138NSR U41 1 Dual RS-232 transmitter/receiver (16-pin, 300-mil SO) Dallas Semiconductor DS232AS U42 1 High-speed microcontroller (44-pin TQFP, 0°C to +70°C) Dallas Semiconductor DS87C520-ECL U44 1 Microprocessor voltage monitor (3.08V reset threshold) (4-pin SOT143) Maxim MAX811TEUS-T U45 1 Microprocessor voltage monitor (4.38V reset threshold) (4-pin SOT143) Maxim MAX812MEUS-T U46 1 Single-chip USB to UART bridge (28-pin QFN) Silicon Laboratories CP2101 Y1 1 3.3V, 12.8MHz OCXO (5-pin) through-hole DO NOT POPULATE Vectron MC853X4-035W Y2 1 3.3V, 12.8MHz TCXO (4-pin SMD) Vectron C22601A1-0028 Y3 1 3.3V, 12.8MHz OCXO (4-pin SMD) DO NOT POPULATE Vectron C4400A1-0044 Y7 1 Low-profile 11.0592MHz crystal Pletronics LP49-33-11.0592M
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. 7. APPENDIX 2: BITS MODE WRITE SEQUENCES BITS Transmitter DS1 ESF address 04h, set TMODE[1:0]=00 address 21h, write 02h address 21h, write 00h address 27h, write 0Ch address 29h, write 00h address 21h, write 80h address 21h, write C0h DS1 SF/D4 address 04h, set TMODE[1:0]=00 address 21h, write 02h address 21h, write 00h address 27h, write 0Ch address 29h, write 04h address 21h, write 80h address 21h, write C0h address 04h, set TMODE[1:0]=01 address 21h, write 02h address 21h, write 00h address 29h, write 00h address 2Ah, write 05h address 21h, write 81h address 21h, write C1h address 60h, write 1Bh address 61h, write 40h 2048kHz address 04h, set TMODE[1:0]=10 address 21h, write 02h address 21h, write 00h BITS Receiver DS1 ESF address 04h, set RMODE[1:0]=00 address 0Ah, write 40h address 20h, write 02h address 20h, write 00h address 22h, write 40h address 20h, write 80h address 20h, write C0h DS1 SF/D4 address 04h, set RMODE[1:0]=00 address 0Ah, write 40h address 20h, write 02h address 20h, write 00h address 22h, write 60h address 20h, write 80h address 20h, write C0h address 04h, set RMODE[1:0]=01 address 20h, write 02h address 20h, write 00h address 24h, write 68h address 20h, write 81h address 20h, write C1h 2048 kHz address 04h, set RMODE[1:0]=10 address 20h, write 02h address 20h, write 00h 6312 kHz address 04h, set RMODE[1:0]=11 address 20h, write 02h address 20h, write 00h 8. SCHEMATICS The DS3100DK schematics are featured in the following 13 pages. 9. DOCUMENT REVISION HISTORY REVISION DATE DESCRIPTION 091806 Initial DS3100DK data sheet release. 110206 Updated document to describe software v0.7 features: (page 1) Features section; (page 6) table captions.
Wed May 10 13:21:44 2006
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21 R84
0.0 0L_SMT0603_1PCTCJ10-000F OC6NEG NA RESREF TM1 TM2 GPIO3 DNP RD WR ALE REFCLK AD7 AD6 AD5 AD4 AD3 OC10 OC8POS OC3 SRCSW 10K OC9 INTREQ SONSDH IC1A JTDO NASRCSW CS_3100 WDT PORNOT HIZ IFSEL0 RDY INTREQ NC1 NC2 NC3 JTDI JTRST JTCLK GPIO2 IC14 IC11 IC12 IC10 IC9 IC5NEG IC5POS IC6POS IC3 IC2 IC1 SYNC2K OC4 OC5 OC6POS OC7POS OC7NEG OC1 OC2 NA NA 10K 0.0 0.0 NA NA NA NA NA NA NANA NA NA 10K RED .1UF 330 10K WDT MASTSLV SONSDH NA MASTSLV IC8 IC7 IC2A IFSEL2 SRFAIL PAGE: DATE:TITLE: ENGINEER: A A B B C C D D VCC VCC SPDT SPDT SPDT VCC CONTROL DS3100_U1 SRCSW SRFAIL ALE WR_RW* CS* WDT SONSDH MASTSLV IFSEL<2> JTDO RESREF REFCLK RST* HIZ* IFSEL<0> IFSEL<1> RD_DS* RDY* INTREQ NC1 NC2 NC3 JTDI JTRST* JTCLK JTMS AD<4> AD<5> AD<6>_CPHA GPIO1 GPIO3 GPIO2 GPIO4 TM1 TST_RA1 TM2 TST_RB2 TST_RB1 TST_RA2 TST_RC2 TST_RC1 TST_TA2 TST_TA1 TST_TC1 TST_TB2 TST_TB1 TST_TC2 A<1> IC14 IC13 IC11 IC12 IC10 IC8 IC9 IC6NEG IC7 IC5NEG IC5POS IC6POS IC3 IC4 IC2 IC1A IC2A IC1 SYNC2K A<0> A<8> A<5> A<7> A<6> A<3> A<4> A<2> OC3 OC4 OC5 OC6POS OC6NEG OC7POS OC7NEG OC8POS OC8NEG OC9 OC10 AD<0>_SDO AD<1>_SDI AD<2>_SCLK AD<3> AD<7>_CPOL OC1 OC2 OC11
Wed May 10 13:21:51 2006 110705
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AVDD_PLL4 AVDD_PLL2AVDD_PLL3 AVDD_PLL1 NA RTIP2 RRING2 TTIPA2 TRINGA2 TRINGA2 THZE2 TTIPA2 ROUT2 RCLK2 MCLK2 RSER2 TSER2 TOUT2 TIN2 TCLK2 NA RTIP1 RRING1 TTIPA1 TRINGA1 TRINGA1 THZE1 TTIPA1 ROUT1 RCLK1 MCLK1 RSER1 TSER1 TOUT1 TIN1 TCLK1 DUT33 10K10K RSER2 ROUT2 TSER2 RCLK2 TIN2 NA RSER1 ROUT1 TSER1 RCLK1 TIN1 I31 I14 I30 0.0 0.0 0.0 0.0 .1UF .1UF .1UF AVDD_PLL4.1UF AVDD_PLL3 AVDD_PLL1 AVDD_PLL2 I15 DUT33 GND PAGE: DATE:TITLE: ENGINEER: A A B B C C D D CONN_6P_U CONN_6P_U DS3100_U1 PWR & GND VDD3VDD2VDD1 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO11 VDDIO10 VDDIO12 VDDIO13 VDDIO16 VDDIO14 VDDIO15 VDDIO18 VDDIO17 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28 VSS1 VSS2 VSS4 VSS3 VSS7 VSS6 VSS5 VSS9 VSS8 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS22 VSS21 VSS24 VSS23 VSS25 VSS26 VSS28 VSS27 VDDIO5 VDD_OC7VDD_OC6VDD_ICDIFF TVDD_P2TVDD_P1RVDD_P2RVDD_P1 DVDD AVDD_PLL4 AVDD_PLL2AVDD_PLL3 AVDD_PLL1 VDD24VDD23VDD22VDD21VDD20 VDD17VDD16 VDD11 VDD9VDD10 VDD8VDD7VDD6VDD5VDD4 VSS55VSS56 VSS54VSS53VSS52VSS51VSS50VSS49VSS48VSS47VSS46VSS45VSS44VSS43VSS42VSS41VSS40VSS39VSS38VSS37VSS36VSS35VSS34VSS33VSS32VSS31VSS30VSS29 DVSS VSS_OC7VSS_OC6VSS_ICDIFF TVSS_P2TVSS_P1RVSS_P2RVSS_P1 AVSS_PLL4AVSS_PLL3AVSS_PLL2AVSS_PLL1 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDD12VDD13VDD14VDD15 VDD19VDD18 DS3100_U1 PORTRTIP RRING TTIPB TRINGA TRINGB THZE TTIPA ROUT RCLK MCLK RSER TSER TOUT TIN TCLK DS3100_U1 PORTRTIP RRING TTIPB TRINGA TRINGB THZE TTIPA ROUT RCLK MCLK RSER TSER TOUT TIN TCLK
ALL SIGNAL TRACKS ARE 50 OHM WITH RESPECT TO PLANE INPUT CLOCKS Wed May 10 13:21:45 2006 DS3100DK01B0 JML 110705
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12.8MHZ DNP DNP DNP DNP DNP DNP DNP IC9 IC8 IC7 IC4 IC3 IC2 IC1 DNP 12.8MHZ_3.3V .1UF 33.2 .1UF 12.8MHZ_3.3V 12.8MHZ_3.3V OSC33 REFCLK DNP DNP .1UF OSC33 PAGE: DATE:TITLE: ENGINEER: A A B B C C D D VCC OSC_OCXO RF_OUT EFC GND RF_OUT OSC_TCXO VC VS GND OSC_MC853X4 GND RF_OUT SUPPLY_V DS4026_U VOSC VCCD VCC VREF GNDOSC GNDA GND GNDD FOUT SCL SDA
ALL SIGNAL TRACKS ARE 50 OHM WITH RESPECT TO PLANE PLACE TESTPOINTS ON 100 MIL CENTER PLACE TESTPOINTS ON 100 MIL CENTER INPUT CLOCKS Wed May 10 13:21:49 2006 DS3100DK01B0 JML 110705
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51.1 51.1 NA 51.1 51.1 NA PAGE: DATE:TITLE: ENGINEER: A A B B C C D D
PLACE TESTPOINTS ON 100 MIL CENTER DS3100DK01B0 Thu Oct 13 10:14:03 2005 JML 092205
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1 U24
1 U23
1 U22
1 U2121
1 U20
1 U1921
1 U18
1 U1721
1 U16
1 U1521
1 U14
1 U1321
1 U12
1 U1121
1 U10
1 U9 1
50 OHM VERT
0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 PAGE: DATE:TITLE: ENGINEER: A A B B C C D D NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B
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Thu Oct 13 10:14:03 2005 R25 2 1JMP2 4 1 U7 R21 2 1 DS6 21 R27 R46 2 1 DS8 21 R50
1 U25
1 U26GPIO1
1.0K SRFAIL GPIO4 GPIO3 GPIO2 10K RED I36 I31 I27 I24 I20 I11 470 RED 1.0K 470 10K 1.0K 470 RED 10K 470 RED 1.0K10K PAGE: DATE:TITLE: ENGINEER: A A B B C C D D NC7SZ32 A C B VCC NC7SZ32 A C B VCC NC7SZ32 A C B VCC NC7SZ32 A C B VCC NC7SZ32 A C B
BITS TRANSCEIVER DS3100DK01B0
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Wed May 10 13:21:42 2006 110705 JML J58 J56 R88 116 314 215 2 1 C27 R87 R90 C29 116 107
21 JMP12
21 JMP11
0.0 ERJ-8GEYJ0R00V 0L_SMT1206_5PCT 560PF DNP DNP DNP 0.0 ERJ-8GEYJ0R00V 0L_SMT1206_5PCT 560PF PAGE: DATE:TITLE: ENGINEER: A A B B C C D D 1:2 CONN_BANTAM T R 1:1 1:2 CONN_BANTAM T R CONN_BANTAM T R 1:1 CONN_BANTAM T R
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0.0 NA 0.0 0.0 .47UF NA DNP DNP 0.0
90.9 NA 357NA
1:1 301 NA IC2A OC8NEG OC8POS 0.0 .47UF NA 90.9 0.0 NA IC1A NA 330PF 330PF 2424 2.42.4 4.74.7 .01UF PAGE: DATE:TITLE: ENGINEER: A A B B C C D D CONN_BANTAM T R 2:1 1:1CONN_BANTAM T R 2:1 CONN_BANTAM T R
(SDIO) (SCLK)
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Thu Oct 13 10:14:03 2005 21 R6 21 R5 21R4 21R3 21R2 1 U5 SW6 155 U27 109 J15 JMP633 JMP62 J50 2 1C39 2 1 C40 1 2 2 1C34 2 1C36 2 1C37 2 1C35 2 710 1411 1213 U41 2 1C38 R110 R108 2 1 DS16 U42 ALE NA AD1 AD2 SLAVE AD1 RXD0 TX232 TX232 POR TXD0 INTREQ AD0 AD1 AD2 AD4 AD6 AD7 A12 RD WR AD3 AD5 CSM CSS CS_3100 A12 SCS GND DNP 0.0 11.0592MHZ 22PF 22PF 10UF 10UF 10UF 10UF 10UF RXD0 USB_RXD RX232 RX232 RS232 SLAVE CSS 330 NA 0.0 0.0 USB_TXD TXD0 SCS AD2 NA SLAVE CSM 10K GREEN 74AHC138 0.0 PAGE: DATE:TITLE: ENGINEER: A A B B C C D D VCC NC7SZ32 A C B V5_0 DPDT B C G2B* Y0* Y1* Y2* Y4* Y5* Y6* Y3* A Y7*G2A* 1 2 CONN_10P CONN_DB9P H G F C A B D E J DS87C520_TQFP P1_5 GND<2-0> XTAL2 VCC AD0 AD1 AD2 AD4 AD6 AD7 ALE PSEN P2_7 P2_6 P2_5 P2_3 P2_4 P2_2 P2_1 P2_0 P1_4 RST P1_6 P3_1 P3_0 P3_2 P3_4 P3_3 P3_7 P3_6 P3_5 XTAL1 AD3 P1_3 P1_1 P1_2 P1_7 EA AD5 P1_0 DS232A T2IN T1IN R1IN R2IN T2OUT T1OUT R2OUT R1OUT C1POS C1NEG VNEG VPOS C2NEG GND C2POS VCC V5_0 V5_0
Thu Oct 13 10:14:03 2005
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21 R123
21 R122
21 R121
21 R120
.1UF USB_TXD USB_RXD0.0 0.0 NA NA NA NA 10K 10K 10K 10K 10K 4.7UF 10K 10K JTMS JTDI JTRST JTDO JTCLK 0.0 I374.38V 0.0 I403.08V I42 PORPORNOT PAGE: DATE:TITLE: ENGINEER: A A B B C C D D MAX811_U RESET* VCC GND MR* VCC MAX812_UVCC GND MR* RESET V5_0 CP2101_U1 USBDM VBUS USBDP RTS* DTR* CTS* DSR* DCD* RI* NC7 NC8 NC9 NC10 NC11 RST* REGIN NC6 NC4 NC5 NC3 NC2 NC1 GND VDD TXD RXD SUSPEND_HIGH SUSPEND_LOW* USBGND SH DAT+ DAT- VDD VCC 1 2 CONN_10P
Wed May 10 13:21:47 2006 JML 110705
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1 U28
NA6.8UF NA 2.1MM/5.5MM DUT33 330 330 330 V5_0 4.7UF 4.7UF 6.8UF
1 AMP
4.7UF 6.8UF PAGE: DATE:TITLE: ENGINEER: A A B B C C D D NC7SZ32 A C B MAX1793_U2 IN2 IN3 GND SHDN* IN4 IN1 SET RST* OUT1 OUT4 OUT2 OUT3 CONN_BANANA_2P B A V5_0 V5_0 CONN_BANANA_2P B A VCC MAX1793_U2 IN2 IN3 GND SHDN* IN4 IN1 SET RST* OUT1 OUT4 OUT2 OUT3 V5_0 V5_0 V5_0 MAX1793_U2 IN2 IN3 GND SHDN* IN4 IN1 SET RST* OUT1 OUT4 OUT2 OUT3
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.1UF .1UF .1UF .1UF .1UF .1UF.1UF .1UF I60 .1UF .1UF I69 I70 .1UF .1UF .1UF.1UF .1UF I71 I76 .1UF .1UF I77 .1UF .1UF I79 I78 .1UF I90 I91 .1UF I92 .1UF I97I96 .1UF .1UF I98I99 .1UF I111 .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF I112 .1UF.1UF .1UF .1UF I113 10UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF DUT33 DUT18 .1UF .1UF .1UF .1UF VCC GND .1UF .1UF .1UF .1UF 10UF 10UF 10UF 10UF 10UF10UF 10UF .1UF .1UF .1UF .1UF .1UF V5_0 10UF 10UF PAGE: DATE:TITLE: ENGINEER: A A B B C C D D V5_0 VCC VCC
02 - 111905 - FIX TRANSFORMER ISSUES,ADDED POWER JACK,FIXED CSM/CSS LOGIC,ADDED TPS REVISION HISTORY - 01 - 110705 - RELEASE FOR REVIEW MOVED CSM TO 1000 AND CSS TO 0 ADDED INTEL BUS CONNECTIONS ADDED 0 OHM RESISTORS AT SDIO,SCLK,SCS ADDED BUFFER TO 1.8V LED 05 - 011306 - REMOVED 5V CAPS, LEDS AND SWITCHES FROM MICRO, LOW Z TP FROM ICN ADDED SHORTED JUMPERS AT REGULATORS FOR ACCESS CHANGED CAP ON COMPOSITE CLOCK TX TO .01UF MOVED UP OK LED TO P1.1 AND REVERSED LOGIC ADDED 330PF CAPS AT COMPOSITE CLOCK INPUT CHANGED 138 TO AHC FROM HC FIXED COMPOSITE CLOCK TERMINATION RES MADE INTEL MUX MODE DEFAULT B0 - 050206 - A0 - 012106 - RELEASE TO FAB 03 - 112105 - MOVED MEMORY MAP,OTHER MISCELLANEOUS 04 - 010406 - CHANGED REF DESIGNATORS TO MATCH EE ADDED DS4026 TCXO AND SUPPORTING COMPONENTS Thu Oct 13 10:14:03 2005 092205 JML 13 OF 13 DS3100DK01B0 PAGE: DATE:TITLE: ENGINEER: A A B B C C D D