DS3045W-100

DS3045W MAXIM | Alldatasheet

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Features

♦ Single-Piece, Reflowable, 27mm x 27mm BGA Package Footprint ♦ Internal Manganese Lithium Battery and Charger ♦ Integrated Real-Time Clock ♦ Unconditionally Write-Protects the Clock and SRAM when VCC is Out-of-Tolerance ♦ Automatically Switches to Battery Supply when VCC Power Failures Occur ♦ Reset Output can be Used as a CPU Supervisor ♦ Interrupt Output can be Used as a CPU Watchdog Timer ♦ Industrial Temperature Range (-40°C to +85°C) ♦ UL Recognized DS3045W 3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock CE DATA ADDRESS INT RST A0–16 DQ0–7 CE

17 BITS

8 BITS

Rev 0; 6/05 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

Pin Configuration appears at end of data sheet. PART TEMP RANGE PIN-PACKAGE SPEED SUPPLY VOLTAGE DS3045W-100 -40°C to +85°C 256-ball 27mm x 27mm BGA Module 100ns 3.3V ±0.3V

3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +85°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC 3.0 3.3 3.6 V Input Logic 1 V IH 2.2 VCC V Input Logic 0 V IL 0.0 0.4 V PIN CAPACITANCE (TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Capacitance C IN Not production tested 15 pF Input/Output Capacitance C OUT Not production tested 15 pF DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±0.3V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage Current I IL -1.0 +1.0 µA I/O Leakage Current I IO CE = CS = VCC -1.0 +1.0 µA Output-Current High I OH At 2.4V -1.0 mA Output-Current Low I OL At 0.4V 2.0 mA Output-Current Low RST IOL RST At 0.4V (Note 1) 8.0 mA Output-Current Low IRQ/FT IOL IRQ/FT At 0.4V (Note 1) 7.0 mA ICCS1 CE = CS = 2.2V 0.5 7Standby Current ICCS2 CE = CS = VCC - 0.2V 0.2 5 mA Operating Current I CCO1 tRC = 200ns, outputs open 50 mA Write Protection Voltage V TP 2.8 2.9 3.0 V

3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±0.3V, TA = -40°C to +85°C.) DS3045W-100PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Read Cycle Time tRC 100 ns Access Time tACC 100 ns OE to Output Valid tOE 50 ns RTC OE to Output Valid tOEC 60 ns CE or CS to Output Valid tCO 100 ns OE or CE or CS to Output Active tCOE (Note 2) 5 ns Output High Impedance from Deselection tOD (Note 2) 40 ns Output Hold from Address tOH 5n s Write Cycle Time tWC 100 ns Write Pulse Width tWP (Note 3) 75 ns Address Setup Time tAW 0n s tWR1 (Note 4) 5Write Recovery Time tWR2 (Note 5) 20 ns Output High Impedance from WE tODW (Note 2) 40 ns Output Active from WE tOEW (Note 2) 5 ns Data Setup Time tDS (Note 6) 40 ns tDH1 (Note 4) 0Data Hold Time tDH2 (Note 5) 20 ns Chip-to-Chip Setup Time tCCS 40 ns POWER-DOWN/POWER-UP TIMING (TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC Fail Detect to CE, CS, and WE Inactive tPD (Note 7) 1.5 µs VCC Slew from VTP to 0V tF 150 µs VCC Slew from 0V to VTP tR 150 µs VCC Valid to CE, CS, and WE Inactive tPU 2m s VCC Valid to End of Write Protection tREC 125 ms VCC Fail Detect to RST Active tRPD (Note 1) 3.0 µs VCC Valid to RST Inactive tRPU (Note 1) 40 350 525 ms

3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock Note 1: IRQ/FT and RST are open-drain outputs and cannot source current. External pullup resistors should be connected to these pins to realize a logic-high level. Note 2: These parameters are sampled with a 5pF load and are not 100% tested. Note 3: tWP is specified as the logical AND of CE with WE for SRAM writes, or CS with WE for RTC writes. t WP is measured from the latter of the two related edges going low to the earlier of the two related edges going high. Note 4: tWR1 and tDH1 are measured from WE going high. Note 5: tWR2 and tDH2 are measured from CE going high for SRAM writes or CS going high for RTC writes. Note 6: tDS is measured from the earlier of CE or WE going high for SRAM writes, or from the earlier of CS or WE going high for RTC writes. Note 7: In a power-down condition, the voltage on any pin may not exceed the voltage on VCC. Note 8: The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. Minimum expected data-retention time is based upon a maximum of two +230°C convection reflow exposures, fol- lowed by a fully charged cell. Full charge occurs with the initial application of VCC for a minimum of 96 hours. This parame- ter is assured by component selection, process control, and design. It is not measured directly during production testing. Note 9: WE is high for any read cycle. Note 10: OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. Note 11: If the CE or CS low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high-impedance state during this period. Note 12: If the CE or CS high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period. Note 13: If WE is low or the WE low transition occurs prior to or simultaneously with the related CE or CS low transition, the output buffers remain in a high-impedance state during this period. DATA RETENTION (TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Expected Data-Retention Time (Per Charge) tDR (Notes 7, 8) 2 3 Years

3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock Read Cycle OUTPUT DATA VALID tRC tACC tCO tOE tOEC tOH tOD tODtCOE tCOE VIH VIH VIL VOH VOL VOH VOL VIL VIH ADDRESSES CE OR CS OE D OUT (SEE NOTE 9.) VIH VIH VIH VIH VIL VIL VIL

3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock Write Cycle 1 DATA IN STABLE ADDRESSES WE DOUT DIN tWC VIH VIH VIH VIH VIL VIL VIL HIGH IMPEDANCE VIH VIH VIL VIL VIH VIL VIL VIL VIL tAW tWP tOEW tDH1tDS tODW tWR1 (SEE NOTES 2, 3, 4, 6, 10–13.) CE OR CS Write Cycle 2 tWC tAW tDH2tDS tCOE tODW tWP tWR2 VIH VIL VIHADDRESSES WE DOUT DIN VIL VIH VIL VIH VIL VIL VIL VIL VIH VIH VIL VIH DATA IN STABLE VIL VIH VIL (SEE NOTES 2, 3, 5, 6, 10–13.) CE OR CS

3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock Power-Down/Power-Up Condition tDR tPU tF tPD tRPUtRPD SLEWS WITH VCC tR VOL VIH VOL tREC VCC VTP ~2.5V CE, WE RST BACKUP CURRENT SUPPLIED FROM LITHIUM BATTERY (SEE NOTES 1, 7.) AND CS Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. OPERATING FREQUENCY DS3045W toc01 VCC (V) SUPPLY CURRENT (mA) 3.0 3.6 TA = +25°C5MHz CE-ACTIVATED 50% DUTY CYCLE 1MHz ADDRESS-ACTIVATED 100% DUTY CYCLE 1MHz CE-ACTIVATED 50% DUTY CYCLE 5MHz ADDRESS-ACTIVATED 100% DUTY CYCLE SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3045W toc02 VCC (V) SUPPLY CURRENT (µA) 600 700 800 900 1000 500 3.0 3.6 VCC = CE = 3.3V, VBAT = VCHARGE, OSC = ON BATTERY CHARGER CURRENT vs. BATTERY VOLTAGE DS3045W toc03 DELTA V BELOW VCHARGE (V) BATTERY CHARGER CURRENT, ICHARGE (mA) 0.80.2 0.6 0.4 0 1.0 VCC = CE = 3.3V VCHARGE = 2.86V

3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock VCHARGE PERCENT CHANGE vs. TEMPERATURE DS3045W toc04 TEMPERATURE (°C) VCHARGE PERCENT CHANGE FROM 25°C (%) 603510-15 -0.5 0.5 1.0 -1.0 -40 85 VCC = 3.3V, VBAT = VCHARGE WRITE PROTECTION VOLTAGE vs. TEMPERATURE DS3045W toc05 TEMPERATURE (°C) WRITE PROTECT, VTP (V) 603510-15 2.85 2.90 2.95 3.00 2.80 -40 85 DQ OUTPUT-VOLTAGE HIGH vs. DQ OUTPUT-CURRENT HIGH DS3045W toc06 IOH (mA) VOH (V) -1-2-3-4 2.7 2.9 3.1 3.3 3.5 2.5 -5 0 VCC = 3.3V DQ OUTPUT-VOLTAGE LOW vs. DQ OUTPUT-CURRENT LOW DS3045W toc07 IOL (mA) VOL (V) 4321 0.1 0.2 0.3 0.4 VCC = 3.3V IRQ/FT OUTPUT-VOLTAGE LOW vs. OUTPUT-CURRENT LOW DS3045W toc08 IOL (mA) VOL (V) 15105 0.1 0.2 0.3 0.4 0.5 0.6 02 0 VCC = 3.3V RST OUTPUT-VOLTAGE LOW vs. OUTPUT-CURRENT LOW DS3045W toc09 IOL (mA) VOL (V) 15105 0.1 0.2 0.3 0.4 0.5 0.6 02 0 VCC = 2.8V Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) RST VOLTAGE vs. VCC DURING POWER-UP DS3045W toc10 VCC POWER-UP (V) RST VOLTAGE W/PULLUP RESISTOR (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 4.0 TA = +25°C

3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock Pin Description BALLS NAME DESCRIPTION A1, A2, A3, A4 GND Ground B1, B2, B3, B4 IRQ/FT Interrupt/Frequency Test Output C1, C2, C3, C4 A15 Address Input 15 D1, D2, D3, D4 A16 Address Input 16 E1, E2, E3, E4 RST Reset Output F1, F2, F3, F4 VCC Supply Voltage G1, G2, G3, G4 WE Write Enable Input H1, H2, H3, H4 OE Output Enable Input J1, J2, J3, J4 CE SRAM Chip Enable Input K1, K2, K3, K4 DQ7 Data Input/Output 7 L1, L2, L3, L4 DQ6 Data Input/Output 6 M1, M2, M3, M4 DQ5 Data Input/Output 5 N1, N2, N3, N4 DQ4 Data Input/Output 4 P1, P2, P3, P4 DQ3 Data Input/Output 3 R1, R2, R3, R4 DQ2 Data Input/Output 2 T1, T2, T3, T4 DQ1 Data Input/Output 1 U1, U2, U3, U4 DQ0 Data Input/Output 0 V1, V2, V3, V4 GND Ground W1, W2, W3, W4 GND Ground Y1, Y2, Y3, Y4 GND Ground A17, A18, A19, A20 GND Ground B17, B18, B19, B20 N.C. No Connection C17,C18,C19, C20 N.C. No Connection D17, D18, D19, D20 A14 Address Input 14 E17, E18, E19, E20 A13 Address Input 13 F17, F18, F19, F20 A12 Address Input 12 G17, G18, G19, G20 A11 Address Input 11 H17, H18, H19, H20 A10 Address Input 10 J17, J18, J19, J20 A9 Address Input 9 K17, K18, K19, K20 A8 Address Input 8 L17, L18, L19, L20 A7 Address Input 7 M17, M18, M19, M20 A6 Address Input 6 BALLS NAME DESCRIPTION N17, N18, N19, N20 A5 Address Input 5 P17, P18, P19, P20 A4 Address Input 4 R17, R18, R19, R20 A3 Address Input 3 T17, T18, T19, T20 A2 Address Input 2 U17, U18, U19, U20 A1 Address Input 1 V17, V18, V19, V20 A0 Address Input 0 W17, W18, W19, W20 GND Ground Y17, Y18, Y19, Y20 GND Ground A5, B5, C5, D5 N.C. No Connection A6, B6, C6, D6 N.C. No Connection A7, B7, C7, D7 N.C. No Connection A8, B8, C8, D8 N.C. No Connection A9, B9, C9, D9 N.C. No Connection A10, B10, C10, D10 V CC Supply Voltage A11, B11, C11, D11 N.C. No Connection A12, B12, C12, D12 N.C. No Connection A13, B13, C13, D13 N.C. No Connection A14, B14, C14, D14 N.C. No Connection A15, B15, C15, D15 N.C. No Connection A16, B16, C16, D16 N.C. No Connection U5, V5, W5, Y5 CS RTC Chip Select Input U6, V6, W6, Y6 N.C. No Connection U7, V7, W7, Y7 N.C. No Connection U8, V8, W8, Y8 N.C. No Connection U9, V9, W9, Y9 N.C. No Connection U10, V10, W10, Y10 N.C. No Connection U11, V11, W11, Y11 N.C. No Connection U12, V12, W12, Y12 N.C. No Connection U13, V13, W13, Y13 N.C. No Connection U14, V14, W14, Y14 N.C. No Connection U15, V15, W15, Y15 N.C. No Connection U16, V16, W16, Y16 N.C. No Connection

3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock Functional Diagram CURRENT-LIMITING RESISTOR BATTERY-CHARGING/SHORTING PROTECTION CIRCUITRY (U.L. RECOGNIZED) REDUNDANT LOGIC DELAY TIMING CIRCUITRY CHARGER CURRENT-LIMITING RESISTOR VTP REF VSW REF GND ML CE RST CE REDUNDANT SERIES FET SRAM DQ0–7OE WE VCC VCC UNINTERRUPTED POWER SUPPLY FOR THE SRAM AND RTC IRQ/FT DS3045WOE WE A0–A16 A0–A3 REAL-TIME CLOCK 32.768kHz WE OE CSCS

CC for an out-of-tolerance condition. place of SRAM, EEPROM, or flash components. face to many 3.3V microprocessor devices. watchdog timer, battery monitor, and power monitor. state until normal power returns. be handled with standard BGA assembly techniques. Table 1. RTC/Memory Operational Truth Table X = Don’t care. (1) = See Figure 4.

and OE (output enable) access times are also satisfied. CE or tOE for OE rather than address access. x = Don’t care address bits. X = Unused. Read/writeable under write and read bit control. OSC = Oscillator start/stop bit. WDS = Watchdog steering bit. BMB0–BMB4 = Watchdog multiplier bits. RB0, RB1 = Watchdog resolution bits. Y = Unused. Read/writeable without write and read bit control. ABE = Alarm in backup mode enable. 0 = Reads as a 0 and cannot be changed. Table 2. RTC Register Map

3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock RTC Read Mode The DS3045W executes an RTC read cycle whenever CE (SRAM chip enable) and WE (write enable) are inactive (high) and CS (RTC chip select) is active (low). The least significant 4 address inputs (A0 to A3) define which of the 16 RTC registers is to be accessed (see Table 2). Valid data is available to the eight data output drivers within t ACC (access time) after the last address input signal is stable, providing that CS and OE (output enable) access times are also satisfied. If CS and OE access times are not satisfied, then data access must be measured from the later occurring signal ( CS or OE) and the limiting parameter is either t CO for CS or tOEC for OE rather than address access. RTC Write Mode The DS3045W executes an RTC write cycle whenever CE is inactive (high) and the CS and WE signals are active (low) after address inputs are stable. The later- occurring falling edge of CS or WE determines the start of the write cycle. The write cycle is terminated by the earlier rising edge of CS or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t WR) before another cycle can be initiated. The CE and OE control signals should be kept inactive (high) during RTC write cycles to avoid bus contention. However, if the out- put drivers have been enabled (CS and OE active) then WE disables the outputs in t ODW from its falling edge. Clock Oscillator Mode The oscillator can be turned off to minimize battery cur- rent drain. The OSC bit is the MSB of the SECONDS register, and must be initialized to a 0 to start the oscil- lator upon first power application. The OSC bit is facto- ry set to a 1 prior to shipment. Oscillator operation and frequency can be verified by setting the FT bit to a 1 and monitoring the IRQ/FT output for 512Hz. Reading the Clock When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC reg- isters. This puts the external registers into a static state, allowing the data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state. External updates are halted by writing a 1 to the read bit (R). As long as a 1 remains in the R bit, updating is inhibited. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command was issued. Normal updates to the external set of registers resume within 1 second after the R bit is set to a 0 for a minimum of 500µs. The R bit must be a 0 for a minimum of 500µs to ensure the external registers have fully updated. Setting the Clock As with a clock read, it is also recommended to halt updates prior to setting new time values. Setting the write bit (W) to a 1 halts updates of the external RTC registers 8h to Fh. After setting the W bit to a 1, the RTC registers can be loaded with the desired count (day, date, and time) in BCD format. Setting the W bit to a 0 then transfers the values written to the internal registers and allows normal clock operation to resume. Frequency Test Mode The DS3045W frequency test mode uses the IRQ/FT open-drain output. With the oscillator running, the IRQ/FT output toggles at 512Hz when the FT bit is a 1, the alarm-flag enable bit (AE) is a 0, and the watchdog- enable bit (WDS) is a 1 or the WATCHDOG register is written to 00h (FT • AE • (WDS + WATCHDOG)). The IRQ/FT output and the frequency test mode can be used to measure the actual frequency of the 32.768kHz RTC oscillator. The FT bit is reset to a 0 on power-up. Using the Clock Alarm The alarm settings and control for the DS3045W reside within RTC registers 2h–5h. The INTERRUPTS register (6h) contains two alarm-enable bits: alarm enable (AE) and alarm in backup enable (ABE). The AE and ABE bits must be set as described below for the IRQ/FT out- put to be activated when an alarm match occurs. The alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the DS3045W is in the Data Retention Mode to serve as a system wake-up. Alarm mask bits AM1 to AM4 control the alarm mode (see Table 3). Configurations not listed in the table will default to the once-per-second mode to notify the user of an incorrect alarm setting.

alarm generated during power-up will set AF to a 1. during battery backup mode and power-up states. Table 3. Alarm Mask Bits Figure 1. Clearing Active IRQ Waveforms

3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock Using the Watchdog Timer The watchdog timer can be used to detect an out-of- control processor. The user programs the watchdog timer by setting the desired timeout delay into the WATCHDOG register. The five high-order WATCHDOG register bits store a binary multiplier and the two lower- order WATCHDOG bits select the resolution, where 00 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The watchdog timeout value is then determined by multiplication of the 5-bit multiplier value with the 2-bit resolution value. (For example: writing 00001110 (0Eh) into the WATCHDOG register = 3 x 1 second, or 3 seconds.) If the processor does not reset the timer within the specified period, the watchdog flag (WF) is set to a 1 and a processor interrupt is generat- ed and stays active until either WF is read or the WATCHDOG register is read or written. The MSB of the WATCHDOG register is the watchdog steering bit (WDS). When WDS is set to a 0, the watch- dog activates the IRQ/FT output when the watchdog times out. WDS should not be written to a 1, and should be initialized to a 0 if the watchdog function is enabled. The watchdog timer resets when the processor per- forms a read or write of the WATCHDOG register. The timeout period then starts over. The watchdog timer is disabled by writing a value of 00h to the WATCHDOG register. The watchdog function is automatically dis- abled upon power-up and the WATCHDOG register is cleared to 00h. Power-On Default States Upon each application of power to the device, the fol- lowing register bits are automatically set to 0: WDS = 0, BMB0–BMB4 = 0, RB0, RB1 = 0, AE = 0, ABE = 0. All other RTC bits are undefined. Data-Retention Mode The DS3045W provides full functional capability for VCC greater than 3.0V and write-protects by 2.8V. Data is maintained in the absence of V CC without additional support circuitry. The NV SRAM constantly monitors V CC. Should the supply voltage decay, the NV SRAM automatically write-protects itself. All inputs become don’t care, and all data outputs become high imped- ance. As V CC falls below approximately 2.5V (VSW), the power-switching circuit connects the lithium energy source to the clock and SRAM to maintain time and retain data. During power-up, when V CC rises above VSW, the power-switching circuit connects external VCC to the clock and SRAM, and disconnects the lithium energy source. Normal clock or SRAM operation can resume after V CC exceeds VTP for a minimum duration of tREC. Battery Charging When VCC is greater than V TP an internal regulator will charge the battery. The UL-approved charger circuit includes short-circuit protection and a temperature-sta- bilized voltage reference for on-demand charging of the internal battery. Typical data retention expectations greater than 2 years per charge cycle are achievable. A maximum of 96 hours of charging time is required to fully charge a depleted battery. System Power Monitoring When the external V CC supply falls below the selected out-of-tolerance trip point, the output RST is forced active (low). Once active, the RST is held active until the VCC supply has fallen below that of the internal bat- tery. On power-up, the RST output is held active until the external supply is greater than the selected trip point and one reset timeout period (t RPU) has elapsed. This is sufficiently longer than t REC to ensure that the RTC and SRAM are ready for access by the micro- processor. Freshness Seal and Shipping The DS3045W is shipped from Dallas Semiconductor with the RTC oscillator disabled and the lithium battery electrically disconnected, guaranteeing that no battery capacity has been consumed during transit or storage. As shipped, the lithium battery is ~60% charged, and no pre-assembly charging operations should be attempted. When V CC is first applied at a level greater than V TP, the lithium battery is enabled for backup operation. The user is required to enable the oscillator (MSB of SEC- ONDS register) and initialize the required RTC registers for proper timekeeping operation. A 96 hour initial bat- tery charge time is recommended for new system installations. Applications Information Power-Supply Decoupling To achieve the best results when using the DS3045W, assure that all V CC and GND balls are connected and decouple the power supply with a 0.1µF capacitor. Use a high-quality, ceramic surface-mount capacitor if pos- sible. Surface-mount components minimize lead induc- tance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications.

its lifetime depends primarily on the V CC duty cycle. extending the service life well beyond 40 years. when cleaning boards containing a DS3045W module. Figure 4. SRAM/RTC Data Bus Control sured on the package body surface.

3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. Heaney DS3045W BGA modules are recognized by Underwriters Laboratory (UL) under file E99151. Pin Configuration A 12 34 789 05 6 7 8 90 1 2 34 56 1 2 34 1 1 1 25 678 9 1 1 1 1 1 1 1 11 1 21 1 1 11 1 1 7 8 9 00 1 2 3 4 5 6 DS3045W B C D E F G H J K L M N P R T U V W Y A B C D E F G H J K L M N P R T U V W Y TOP VIEW GND IRQ/FT A15 A16 RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND GND GND GND N.C. N.C. A14 A13 A12 A11 A10 GND GND CS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VCC N.C. N.C. N.C. N.C. N.C. N.C.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline info rmation go to www.maxim-ic.com/DallasPackInfo.)