DS28E15P+T

DS28E15_V01 MAXIM | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 5

Technical content

DeepCover™ embedded security solutions cloak sensi - tive data under multiple layers of advanced physical security to provide the most secure key storage possible. The DeepCover Secure Authenticator (DS28E15) com - bines crypto-strong bidirectional secure challenge-and- response authentication functionality with an imple - mentation based on the FIPS 180-3-specified Secure Hash Algorithm (SHA-256). A 512-bit user-program - mable EEPROM array provides nonvolatile storage of application data. Additional protected memory holds a read-protected secret for SHA-256 operations and set - tings for memory protection control. Each device has its own guaranteed unique 64-bit ROM identification number (ROM ID) that is factory programmed into the chip. This unique ROM ID is used as a fundamental input parameter for cryptographic operations and also serves as an electronic serial number within the application. A bidirectional security model enables two-way authen - tication between a host system and slave-embedded DS28E15. Slave-to-host authentication is used by a host system to securely validate that an attached or embed - ded DS28E15 is authentic. Host-to-slave authentication is used to protect DS28E15 user memory from being modi- fied by a unauthentic host. The DS28E15 communicates over the single-contact 1-Wire M bus at overdrive speed. The communication follows the 1-Wire protocol with the ROM ID acting as node address in the case of a multi- device 1-Wire network.

Applications

Authentication of Consumables Secure Feature Control Benefits and Features

• 512-Bit EEPROM with SHA-256 Authentication for Reads and Writes
• Symmetric-Key-Based Bidirectional Secure Authentication Model Based on SHA-256
• Strong Authentication with a High-Bit-Count User Programmable Secret and Input Challenge
• 512 Bits of User EEPROM Partitioned Into Two Pages of 256 Bits
• User-Programmable and Irreversible EEPROM Protection Modes Including Authentication, Write and Read Protect, and OTP/EPROM Emulation
• Unique Factory-Programmed, 64-Bit Identification Number
• Minimalist 1-Wire Interface Lowers Cost and Interface Complexity
• Reduces Control, Address, Data, Power, and Programming Signals to a Single Data Pin
• ±8kV HBM ESD Protection (typ)
• 2-Pin SFN, 6-Pin TDFN-EP, and 6-Pin TSOC Packages
• Operating Range: 3.3V ±10%, -40°C to +85°C Typical Application Circuit Ordering Information appears at end of data sheet. DeepCover is a trademark and 1-Wire is a registered trademark of Maxim Integrated Products, Inc. 219-0018; Rev 3; 3/15 DS28E15 DeepCover Secure Authenticator with 1-Wire SHA-256 and 512-Bit User EEPROM SDA VCC SCL SLPZ IO RP RP = 1.1kΩ MAXIMUM I2C BUS CAPACITANCE 320pF 3.3V 1-Wire LINE µC (I2C PORT) DS2465 DS28E15

Lead Temperature (TDFN, TSOC only; soldering, 10s) ..+300NC Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Electrical Characteristics

(TA = -40NC to +85NC, unless otherwise noted.) (Note 1) Note: The SFN package is qualified for electro-mechanical contact applications only, not for soldering. For more information, refer to Application Note 4132: Attachment Methods for the Electro-Mechanical SFN Package . DS28E15 DeepCover Secure Authenticator with 1-Wire SHA-256 and 512-Bit User EEPROM www.maximintegrated.com Maxim Integrated │ 2 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: GENERAL DATA 1-Wire Pullup Voltage VPUP (Note 2) 2.97 3.63 V 1-Wire Pullup Resistance RPUP VPUP = 3.3V Q10% (Note 3) 300 1500 I Input Capacitance CIO (Notes 4, 5) 1500 pF Input Load Current IL IO pin at VPUP 5 19.5 FA High-to-Low Switching Threshold VTL (Notes 6, 7) 0.65 x VPUP V Input Low Voltage VIL (Notes 2, 8) 0.3 V Low-to-High Switching Threshold VTH (Notes 6, 9) 0.75 x VPUP V Switching Hysteresis VHY (Notes 6, 10) 0.3 V Output Low Voltage VOL IOL = 4mA (Note 11) 0.4 V Recovery Time tREC RPUP = 1500I (Notes 2, 12) 5 Fs Time Slot Duration tSLOT (Notes 2, 13) 13 Fs IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE Reset Low Time tRSTL (Note 2) 48 80 Fs Reset High Time tRSTH (Note 14) 48 Fs Presence-Detect Sample Time tMSP (Notes 2, 15) 8 10 Fs IO PIN: 1-Wire WRITE Write-Zero Low Time tW0L (Notes 2, 16) 8 16 Fs Write-One Low Time tW1L (Notes 2, 16) 1 2 Fs IO PIN: 1-Wire READ Read Low Time tRL (Notes 2, 17) 1 2 - d Fs Read Sample Time tMSR (Notes 2, 17) tRL + d 2 Fs

Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed. Note 2: System requirement. Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. Note 4: Typical value represents the internal parasite capacitance when V PUP is first applied. Once the parasite capacitance is charged, it does not affect normal communication. Note 5: Guaranteed by design and/or characterization only. Not production tested. Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of V PUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected. Note 8: The voltage on IO must be less than or equal to V IL(MAX) at all times the master is driving IO to a logic 0 level. Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected. Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least V HY to be detected as logic 0. Note 11: The I-V characteristic is linear for voltages less than 1V. Note 12: Applies to a single device attached to a 1-Wire line. Note 13: Defines maximum possible bit rate. Equal to 1/(t W0L(MIN) + tREC(MIN)). Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired. Note 15: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E15 present. The power-up pres - ence detect pulse could be outside this interval but will be complete within 2ms after power-up. Note 16: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V IL to VTH. The actual maximum duration for the master to pull the line low is t W1L(MAX) + tF - ε and tW0L(MAX) + tF - ε, respectively. Note 17: d in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V IL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is t RL(MAX) + tF. Note 18: Current drawn from IO during the EEPROM programming interval or SHA-256 computation. The pullup circuit on IO during the programming interval and SHA-256 computation should be such that the voltage at IO is greater than or equal to 2.0V. Note 19: Refer to the full data sheet. Note 20: Refer to the full data sheet. Note 21: Write-cycle endurance is tested in compliance with JESD47G. Note 22: Not 100% production tested; guaranteed by reliability monitor sampling. Electrical Characteristics (continued) (TA = -40NC to +85NC, unless otherwise noted.) (Note 1) DS28E15 DeepCover Secure Authenticator with 1-Wire SHA-256 and 512-Bit User EEPROM www.maximintegrated.com Maxim Integrated │ 3 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM Programming Current IPROG VPUP = 3.63V (Notes 5, 18) 1 mA Programming Time for a 32-Bit Segment or Page Protection tPRD Refer to the full data sheet. ms Programming Time for the Secret tPRS ms Write/Erase Cycling Endurance NCY TA = +85NC (Notes 21, 22) 100k — Data Retention tDR TA = +85NC (Notes 23, 24, 25) 10 Years SHA-256 ENGINE Computation Current ICSHA Refer to the full data sheet. mA Computation Time tCSHA ms

Electrical Characteristics (continued) (TA = -40NC to +85NC, unless otherwise noted.) (Note 1) Note 23: Data retention is tested in compliance with JESD47G. Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the - data sheet limit at operating temperature range is established by reliability testing. Note 25: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem - peratures is not recommended. Note 26: Refer to the full data sheet. Pin Configurations Pin Descriptions DS28E15 DeepCover Secure Authenticator with 1-Wire SHA-256 and 512-Bit User EEPROM www.maximintegrated.com Maxim Integrated │ 4 PIN NAME FUNCTIONSFN TDFN-EP TSOC — 1, 4, 5, 6 3– 6 N.C. Not Connected 1 2 2 IO 1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor. 2 3 1 GND Ground Reference — — — EP Exposed Pad (TDFN Only). Solder evenly to the board’s ground plane for proper operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information. TOP VIEW N.C. IO GND N.C. N.C. N.C. TSOC DS28E15 BOTTOM VIEW NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO- MECHANICAL CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE. 16N.C. N.C. 25IO N.C. 34GND N.C. TDFN-EP (3mm × 3mm) TOP VIEW DS28E15 28E15 ymrrF *EP *EXPOSED PAD IO GND DS28E15 SFN (3.5mm × 6.5mm × 0.75mm)

Ordering Information

+Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad.

Package Information

For the latest package outline information and land patterns (foot- prints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Note to readers: This document is an abridged version of the full data sheet. Additional device infor - mation is available only in the full version of the data sheet. To request the full data sheet, go to www.maximintegrated.com/DS28E15 and click on Request Full Data Sheet. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. DS28E15 DeepCover Secure Authenticator with 1-Wire SHA-256 and 512-Bit User EEPROM © 2015 Maxim Integrated Products, Inc. │ 42 PART TEMP RANGE PIN-PACKAGE DS28E15G+ -40NC to +85NC 2 SFN DS28E15G+T -40NC to +85NC 2 SFN (2.5k pcs) DS28E15Q+T -40NC to +85NC 6 TDFN-EP* (2.5k pcs) DS28E15P+ -40NC to +85NC 6 TSOC DS28E15P+T -40NC to +85NC 6 TSOC (4k pcs) PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

2 SFN T23A6N+1 21-0575 —

6 TDFN-EP T633+2 21-0137 90-0058

6 TSOC D6+1 21-0382 90-0321

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.