DS28E10P+T

DS28E10 MAXIM | Alldatasheet

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S Dedicated Hardware-Accelerated SHA-1 Engine for Generating SHA-1 MACs S One Page of 28 Bytes User OTP EPROM S Irreversible Write Protection S Unique, Factory-Programmed 64-Bit Identification Number S 1-Wire Interface for Standard and Overdrive Speed S Communicates with Host at Up to 15.4kbps at Standard Speed or Up to 125kbps in Overdrive Mode S Operating Range from 2.8V to 3.6V, -40 NC to +85NC S 3-Lead SOT23, 6-Lead TSOC Package S 8kV Human Body Model (HBM) ESD Protection (typ) on 1-Wire and VCC Pin +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. Typical Operating Circuit 1-Wire is a registered trademark of Maxim Integrated Products, Inc. EVALUATION KIT AVAILABLE IO RPUP 3.3V µC Px.1 1-Wire VCC VCC GNDGND DS28E10PART TEMP RANGE PIN-PACKAGE DS28E10R+T -40NC to +85NC 3 SOT23 DS28E10P+ -40NC to +85NC 6 TSOC DS28E10P+T -40NC to +85NC 6 TSOC

1-Wire SHA-1 Authenticator ABRIDGED DATA SHEET Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(TA = -40NC to +85NC, see Note 1.) ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC PIN Supply Voltage VCC During nonprogramming state (Note 2) 2.8 3.6 V Standby Current ICCS VCC = 3.6V 0.5 4.0 FA Operating Current ICCO VCC = 3.6V, reading (Note 3) 30 FA IO PIN: GENERAL DATA 1-Wire Pullup Voltage VPUP (Note 4) 2.8 3.6 V 1-Wire Pullup Resistance RPUP (Notes 4, 5) 0.3 2.2 kI Input Capacitance CIO (Note 3) 50 pF Input Load Current IL (IO pin at VPUP) (Note 3) 2 FA Input Low Voltage VIL (Notes 4, 6, 7) 0.3 O VCC V Input High Voltage VIH (Notes 3, 8) 0.7 O VCC V Switching Hysteresis VHY (Notes 3, 9) 0.05 O VCC V Output Low Voltage VOL At 4mA load (Note 10) 0.3 V Recovery Time (Notes 4, 11) tREC Standard speed, RPUP = 2.2kI 5 FsOverdrive speed, RPUP = 2.2kI 2 Rising-Edge Hold-Off Time (Notes 3, 12) tREH Standard speed 0.5 5 FsOverdrive speed Not applicable (0) Timeslot Duration (Notes 4, 13) tSLOT Standard speed 65 FsOverdrive speed 8 IO PIN: 1-Wire RESET, PRESENCE DETECT CYCLE Reset Low Time (Note 4) tRSTL Standard speed 480 640 FsOverdrive speed 48 80 Presence-Detect High Time tPDH Standard speed 15 60 FsOverdrive speed 2 6 Presence-Detect Low Time tPDL Standard speed 60 240 FsOverdrive speed 8 24 Presence-Detect Sample Time (Notes 4, 14) tMSP Standard speed 60 75 FsOverdrive speed 6 10 IO PIN: 1-Wire WRITE Write-Zero Low Time (Notes 4, 15) tW0L Standard speed 60 120 FsOverdrive Speed 6 16 Write-One Low Time (Notes 4, 15) tW1L Standard speed 1 15 FsOverdrive speed 1 2

1-Wire SHA-1 Authenticator ABRIDGED DATA SHEET ELECTRICAL CHARACTERISTICS (continued) (TA = -40NC to +85NC, see Note 1.) Note 1: Specifications at TA = -40NC are guaranteed by design only and not production tested. Note 2: Refer to the full data sheet for this note. Note 3: Guaranteed by design, characterization, and/or simulation only. Not production tested. Note 4: System requirement. Note 5: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00 might be required. Note 6: Voltage below which, during a falling edge on IO, a logic 0 is detected. Note 7: The voltage on IO needs to be less than or equal to V ILMAX at all times while the master is driving IO to a logic 0 level. Note 8: Voltage above which, during a rising edge on IO, a logic 1 is detected. Note 9: After VIH is crossed during a rising edge on IO, the voltage on IO has to drop by at least V HY to be detected as logic 0. Note 10: The I-V characteristic is linear for voltages less than 1V. Note 11: Applies to a single DS28E10 attached to a 1-Wire line. Note 12: The earliest recognition of a negative edge is possible at t REH after VIH has been reached on the preceding rising edge. Note 13: Defines maximum possible bit rate. Equal to 1/(t W0LMIN + tRECMIN). Note 14: Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28E10 present. Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN. Note 15: ε in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from V IL to VIH. The actual maximum duration for the master to pull the line low is t W1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. Note 16: d in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from V IL to the input high threshold of the bus master. The actual maximum duration for the master to pull the line low is t RLMAX + tF. Note 17: Data retention is degraded as TA increases. Note 18: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing. Note 19: Refer to the full data sheet for this note. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: 1-Wire READ Read Low Time (Notes 4, 16) tRL Standard speed 5 15 - d FsOverdrive speed 1 2 - d Read Sample Time (Notes 4, 16) tMSR Standard speed tRL + d 15 FsOverdrive speed tRL + d 2 EPROM Programming Current IPROG VPP = VPP(MAX) (Note 3) Refer to the full data sheet. mA Programming Time tPP ms Programming Voltage VPP (Note 2) V Data Retention tDR At +85NC (Notes 17, 18) 10 Years SHA-1 Engine SHA-1 Computation Current ICCSHA VCC = 3.6V Refer to the full data sheet. mA SHA-1 Computation Time tCSHA (Note 19) ms

1-Wire SHA-1 Authenticator ABRIDGED DATA SHEET Detailed Description The DS28E10 combines a 512-bit SHA-1 engine, security data, 224 bits of one-time programmable (OTP) EPROM, and a 64-bit ROM ID in a single chip. Data is transferred serially through the 1-Wire protocol, which requires only a single data lead and a ground return. In addition to its important use as a unique data value in cryptographic SHA-1 computations, the device’s 64-bit ROM ID can be used to electronically identify the equipment in which the DS28E10 is used. The ROM ID also serves as node address in a multidrop 1-Wire network environment where multiple devices reside on a common 1-Wire bus and operate independently of each other. Overview The block diagram in Figure 1 shows the relationships between the major control and memory sections of the device. The device has six main data components: 64-bit ROM ID, security data, challenge buffer, 28 bytes of OTP user EPROM memory, special function registers, and a 512-bit SHA-1 engine. Figure 2 shows the hierarchical structure of the 1-Wire protocol. The bus master must first provide one of the seven ROM (network) function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume (communication), 6) Overdrive-Skip ROM or 7) Overdrive-Match ROM. Upon completion of an Overdrive-Skip ROM or Overdrive- Match ROM command executed at standard speed, the device enters overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 8. After a ROM function command is success - fully executed, the memory and SHA-1 functions become accessible and the master can provide any one of the six available function commands. The protocol for these commands is described in Figure 6. All data is read and written least significant bit first. Pin Configurations Pin Description VCC IO GND N.C. N.C. N.C. TSOC DS28E10 VCC

3 GND

PIN NAME FUNCTIONSOT23 TSOC 1 2 IO 1-Wire Bus Interface. Open drain; requires external pullup resistor. 2 3 VCC Supply Pin for Operating Power 3 1 GND Ground Supply for the Device — 4, 5, 6 N.C. Not Connected

Figure 1. Block Diagram Figure 2. Hierarchical Structure for 1-Wire Protocol Figure 3. 64-Bit ROM ID Refer to the full data sheet.

224 BITS USER

one or more devices on the bus could be reset.

• Initialization
• ROM Function Command
• Memory/SHA-1 Function Command
• Transaction/Data Initialization All transactions on the 1-Wire bus begin with an initializa- tion sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The pres - ence pulse lets the bus master know that the DS28E10 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM Function Commands Once the bus master has detected a presence, it can issue one of the seven ROM function commands that the DS28E10 supports. All ROM function commands are 8 bits long. A list of these commands follows (see the flowchart in Figure 8). Read ROM [33h] The Read ROM command allows the bus master to read the DS28E10’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC.

Figure 7. Hardware Configuration

1-Wire SHA-1 Authenticator ABRIDGED DATA SHEET Match ROM [55h] The Match ROM command, followed by a 64-bit ROM ID, allows the bus master to address a specific DS28E10 on a multidrop bus. Only the DS28E10 that exactly matches the 64-bit ROM ID responds to the following memory or SHA-1 function command. All other slaves wait for a reset pulse. This command can be used with a single or multiple devices on the bus. Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their ROM ID numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the ID of all slave devices. For each bit of the ID number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participat - ing in the search outputs the true value of its ID number bit. On the second slot, each slave device participating in the search outputs the complemented value of its ID number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participat - ing in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the search tree. After one complete pass, the bus master knows the ROM ID number of a single device. Additional passes identify the ID numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. Skip ROM [CCh] This command can save time in a single-drop bus sys - tem by allowing the bus master to access the memory or SHA-1 functions without providing the 64-bit ROM ID. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). Resume Command [A5h] To maximize the data throughput in a multidrop environ - ment, the Resume command is available. This command checks the status of the RC bit and, if it is set, directly transfers control to the memory and SHA-1 functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive-Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume command. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultaneously responding to the Resume command. Overdrive-Skip ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM ID. Unlike the normal Skip ROM command, the Overdrive-Skip ROM sets the DS28E10 in the overdrive mode (OD = 1). All communi - cation following this command must occur at overdrive speed until a reset pulse of minimum 480 Fs duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus, this command sets all overdrive-supporting devices into overdrive mode. To subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed must be issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search pro - cess. If more than one slave supporting overdrive is pres- ent on the bus and the Overdrive-Skip ROM command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open- drain pulldowns produce a wired-AND result). Overdrive-Match ROM [69h] The Overdrive-Match ROM command followed by a 64-bit ROM ID transmitted at overdrive speed allows the bus master to address a specific DS28E10 on a multidrop bus and to simultaneously set it in overdrive mode. Only the DS28E10 that exactly matches the 64-bit number responds to the subsequent memory or SHA-1 function command. Slaves already in overdrive mode from a previous Overdrive-Skip ROM or successful Overdrive-Match ROM command remain in overdrive mode. All overdrive-capable slaves return to standard speed at the next reset pulse of minimum 480 Fs dura- tion. The Overdrive-Match ROM command can be used with a single or multiple devices on the bus.

1-Wire SHA-1 Authenticator ABRIDGED DATA SHEET Figure 8a. ROM Functions Flowchart DS28E10 Tx PRESENCE PULSE BUS MASTER Tx RESET PULSE BUS MASTER Tx ROM FUNCTION COMMAND DS28E10 Tx CRC BYTE DS28E10 Tx FAMILY CODE (1 BYTE) DS28E10 Tx SERIAL NUMBER (6 BYTES) RC = 0 MASTER Tx BIT 0 RC = 0 RC = 0 RC = 0 OD = 0 YY Y Y Y Y Y Y 33h READ ROM COMMAND? N 55h MATCH ROM COMMAND? BIT 0 MATCH? BIT 0 MATCH? N N N N N N N F0h SEARCH ROM COMMAND? OD RESET PULSE? N N CCh SKIP ROM COMMAND? N RC = 1 MASTER Tx BIT 1 MASTER Tx BIT 63 BIT 1 MATCH? BIT 63 MATCH? Y Y RC = 1 FROM MEMORY AND SHA-1 FUNCTION FLOWCHART (FIGURE 6) TO MEMORY AND SHA-1 FUNCTION FLOWCHART (FIGURE 6) DS28E10 Tx BIT 0 DS28E10 Tx BIT 0 MASTER Tx BIT 0 BIT 1 MATCH? BIT 63 MATCH? DS28E10 Tx BIT 1 DS28E10 Tx BIT 1 MASTER Tx BIT 1 DS28E10 Tx BIT 63 DS28E10 Tx BIT 63 MASTER Tx BIT 63 Y TO FIGURE 8b TO FIGURE 8b FROM FIGURE 8b FROM FIGURE 8b

1-Wire SHA-1 Authenticator ABRIDGED DATA SHEET Figure 8b. ROM Functions Flowchart (continued) MASTER Tx BIT 0 RC = 0; OD = 1 RC = 0; OD = 1 OD = 0 (SEE NOTE) NOTE: THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVERDRIVE SPEED BEFORE THE OVERDRIVE-MATCH ROM COMMAND WAS ISSUED. (SEE NOTE) (SEE NOTE) RC = 1? Y Y A5h RESUME COMMAND? N Y 3Ch OVERDRIVE- SKIP ROM? N Y 69h OVERDRIVE- MATCH ROM? N N OD = 0N OD = 0N MASTER Tx BIT 1 MASTER Tx BIT 63 Y Y RC = 1 Y BIT 0 MATCH? MASTER Tx RESET? BIT 63 MATCH? BIT 1 MATCH? N Y N YMASTER Tx RESET? N TO FIGURE 8a FROM FIGURE 8a FROM FIGURE 8a TO FIGURE 8a

Figure 10. Read/Write Timing Diagrams

tREC before it is ready for the next time slot. A read-data time slot begins like a write-one time slot. the data line, the master must wait until tSLOT is expired. Refer to the full data sheet for this information. Figure 11. Programming Pulse Timing Refer to the full data sheet for this information.

is received in the true (noninverted) form. details, refer to the full data sheet. Figure 14. CRC-16 Hardware Description and Polynomial Refer to the full data sheet for this information.

1-Wire SHA-1 Authenticator ABRIDGED DATA SHEET

Package Information

For the latest package outline information and land pat terns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suf fix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

6 TSOC D6+1 21-0382

3 SOT23 U3+2 21-0051

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

24 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. DS28E10 1-Wire SHA-1 Authenticator ABRIDGED DATA SHEET

Revision History

0 6/10 Initial release —